2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

Leakage Reduction in Differential lOT SRAM

Cell using Gated VDD Control Technique
Sapna Singhl, Neha Arora 2, Neha Gupta\ Meenakshi Suthar4
FET, Mody Institute of Technology and Science, Lakhmangarh, Sikar
322331, INDIA

Email: singh.sapna067@gmail.com.neha.241986@gmail.com.wdnehagupta@gmail.com
meenakshi.suthar32@gmail.com

Abstract- In modern era, the demand for memory has reduced at the same time. In this diagram, bit lines have
been increases tremendously. Due to reduction in distinct read and write ports.
SRAM operating voltage, cell stability degradation and
the increase in process variation with process scaling.
This paper presents a proposed lOT SRAM cell based
on a gated-ground nMOS transistor technique and
reduces the total leakage power consumption of SRAMs
while maintaining their performance. Simulation results
with 90nm, 4Snm and 32nm process demonstrate that
this technique can reduce the total power consumption.

Keywords -leakage power, power optimization, JOT

SRAM

I. INTRODUCTION

The importance of reducing power consumption in

digital systems is increasing as the range of complexity
of applications in terms of system level issues such as
battery life , weight and size are directly affected by
power consumption .To improve the performance and
capabilities of the system, leakage power reduction is Fig.! Schematic of Differential lor SRAM Cell
needed. As the density of SRAM increased, the leakage
power has become a significant component in chip
B. Gated Differential lOT SRAM Cell
design. In this paper, Differential lOT SRAM cell are
proposed by Gated Vdd control power reduction Differential lOT SRAM cell with an nMOS Gated­
technique with improved parameters. Hence. due to low
VDD is shown in Fig.2 reduces the leakage power.
power consumption, system performance can also
Due to this approach, we can conclude that circuit
improve. In this circuit, the power consuming is reduced
using power-gating technique has better results as
by reducing supply voltage and applying low power
compared to previous circuit. However, the data in
technique. Thus, the main objective is to provide low
power solutions for (VLSI) designers. SRAM cell is lost because of cross coupled inverter
which increases the access time and threshold
II. VARIOUS SRAM CELL FOR LOW voltages and reduces the leakage.
LEAKAGE SRAM CELL This technique may not lead to optimal
reduction as active-mode leakage is not addressed
A. Differential lOT SRAM Cell and bitlines leakage through the NMOS pulldown
transistors is not reduced much. However, this
Differential lOT SRAM cell am as shown in
approach retains the value of the data stored in the
Fig.1.Differential lOT SRAM consists lOT SRAM with
memory cells and does not affect the read or write
differential read bit lines (BL and BLB) .. The lOT cell
access times.
permits bit interleaving and exhibits superior sense
An improvement of the above is proposed to reduce
margin with a differential read path based on a DCVSL
gate leakage power and increase the stability of the
(differential cascade voltage-switch-logic level)
SRAMs. However, both these work assume a strong
structure at the column periphery. There is a
bias towards zero. A single Vt data Retention Gated­
performance degradation from stacked transistors that
Ground (DRG) design to reduce power by setting the
requires boosted WL voltages, but BL leakage is

978-1-4673-0210-4112/$31.00 ©2012 IEEE 610

 2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

unused portions of the memory core to a low leakage written to the bit lines. If we want to write O,we would
mode. DRG uses an nMOS transistor as a gated­ apply a 0 to the bit lines.WL is asserted and the value that
�
ground transistor to turn o f the supply voltag�. to be latched in the bit line input drivers are deSIgned to be
much stronger than the weak transistors in the cell itself so
However, for data retention m the sleep mode this
careful sizing of the transistors in a SRAM cell is needed.
approach requires proper sizing of the gated-gr�und
transistor and an optimum value for the transistor
threshold voltage. Moreover, when the gated-ground B. Challenging Issues from the Current and the
transistor is turned off, the virtual ground node is left
Future Low Leakage SRAM Cell
floating and this may result in a no se source �
degrading the stability of the data stored m the cell. This section provides a various device and circuit
Also, as mentioned by, if the sub-threshold resistan�e design challenges for designers interested to work
of the gated-ground transistor is very less, the data is
with energy-constrained applications.
either lost or the leakage savings is not optimal.

a) Sensitive to Process and Temperature Variation

Integrated circuits with low voltage power
supplies are highly sensitive to process supplies are
highly sensitive to process and temperature
variations. Due to this MOSFET threshold, voltage
degrades and the thermal voltage is enhanced as the
temperature increases. Higher voltage circuits
designed for high speed, low voltage circuits
optimized for minimum energy operate faster when
the temperature increases.
BLB
b) Power Overhead associated with Change in
Supply Voltage
Power overhead associated with changing the
supply voltage level should at least be compensated by
the energy savings in the low-voltage mode. So,
understanding necessary as energy overhead is a
fundamental issue and cannot be avoided.

c) Device Scaling
Device scaling offers a reduction in gate
capacitance and at super sub-threshold voltages, it
Fig.2 Schematic of Gated Differential lOT SRAM Cell (Proposed)
reduces the switching energy and gate delay. Due to
exponential sensltlvltJes to Vt and Vdd in sub
threshold region, circuit may work properly under
III. RELATED WORK
device scaling.

III. SIMULAnON AND ANALYSIS

A. Operation of SRAM cell
A. Simulation Environment
SRAM (Static random access memory) cells use a
All the circuits have been simulated using BSIM
simple bistable circuit to hold data bit. RAM cell can
3V3 90nm.45nm and 32nm technology on Tanner
hold the stored data bit so long as the power is
EDA tool. To make the impartial testing environment
applied to the circuit. RAM cell has three operational
all the circuits has been simulated on the same input
modes:
patterns.

a) Standby mode B.Simulation Comparison

When the cell is in hold state, the value of the bit is
In this section, proposed design using low power
stored in the cell for future usage.
technique is presented for enhancing compared with
differential SRAM lOT cell in terms of power, delay
b) Read mode
and temperature at varying supply voltages. All the
During read operation, the stored bit is transmitted to the
circuits have been simulated with supply voltage
outside world. Q and QB are transferred to the bit lines
ranging Iv to 1.65v. Fig.3, 4 and 5 shows Power
as outputs.
Consumption Vs Vdd for different SRAM cells at
c) Write mode
different technologies.Fig.6, 7 and 8 shows Delay Vs
The start of a write cycle begins by applying the value to be

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 2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

Vdd for different SRAM cells at different 1.01E'()8

technologies. Fig.9, 10 and 11 shows Power 1.0DE·08

�
Consumption Vs Operating Temperature for different
9.90E·09
SRAM cells at different technologies. ."
8 9.80E·09

'"'
•

>- 9.70E'()9 -+- D10T

2.00E·06 ..,
1.80E·06
� 9.60E'()9 ....... G D10T(Proposed)
·
1.60E'()6
· 9.50E·09
! 1.40E·06
.g
·
9.40E·09
1.20E'()6
15. 1.07 1. 3 2
E 1.00E'()6
�· -+-D10T VDD(Volt,)
8.00E·07
8
6.00E'()7 ....... GD10T(Proposed)
0; FIg. 6 Delay Vs Vdd for different SRAM Cells at 90 nm
3 4.00E·07
8. technology.
2.00E'()7

O.OOE+OO
1.2 0E-08
1.07 1.32

Vdd(Vo lt ,) 1.00E· 08 ..

Fig_ 3 Power Consumption Vs Vdd for Different SRAM Cells at ." 8.00E'()9

90nm technology. 8.
'"'
6.00E-09
-+- D10T
..,
>-

� 4.00E-09
• •
....... G D10T(Proposed)
6.00E·05 •
2.00E'()9

·
� 500E'()5
� O.OOE+ OO
•

s 1. 32 1.65
.. 4.00E·05
,g V,,(Volt,)
a
E 3 00E·05
�• -+-D10T
Fig.7 Delay Vs Vdd for different SRAM Cells at 45 nm technology
8
"
2.00E'()5
• l. O :' E- 0 6
...... GDIOT(Proposed)
3
8. 1.00E-D5 1.00E<J8

. 9.90E<J9
O.OOE+OO 6 9.80E<J9
1.32
g
a 9.70E<J9
,
165

Voo (Volts) 9. 6 {1 E.J J 9

� -+- Dl OT
.9 9.50E<J9
....... GD10T
Fig_ 4 Power Consumption Vs Vdd for Different SRAM Cells at 0;
S 9.40E<J9
45nm technology. � 9.30E<J9

9.20E<J9

1.8 E-O S
1.l2 1.6 ,

Voo ( V o � ,)
1.60E-05
,
;; lAOE-05
Fig_8 Delay Vs Vdd for different SRAM Cells at 32nm technology
? 12 0 E·0 5
:3
:- 1.OOE-05
....... DI OT
4.50E-07

� E .OOE-06

___ G ) lOT
4.00E-07
( , O E -06

.-/
.9 t!
"
3.50E-07

� 4 . 0 0 E-0 6
�
C
.2
3.00E-07
,t 2 .00E-06 a
E
2.50E-07

o O C E+OO �c 2.00E-07
-+-D10T

l.l2 l.6 '

0
u

�
1.50E-07
___ GDIOT(Propo,ed)
v o . ( V ol t ,) � 1.00E-07
� 5.00E-08

Fig_ 5 Power Consumption Vs Vdd for Different SRAM Cells at O.OOE+OO

32nm technology. 27 60

Temperature{OC)

Fig_9 Power Consumption Vs Operating Temperature for Different

SRAM Cells at 90nm technology

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 2012 International Conference on Computing, Electronics and Electrical Technologies [ICCEET]

1.20E-D5 Table II: Comparison of Power Delay Product between DIOT and
• GDIOT (Proposed) SRAM Cells at 45 nm technology
....
l.00E·05

i 8 .00E·06
Different Power Delay Product ( WaU
; SRAM Seconds)
'S.
6.00E·06
Cells
� __ D10T
.9 4 .00E-D6 Vdd =lv Vdd=1.32 Vdd=1.6S
....... G D10T( P ropo'e d )
0;
� ....
v v
8- 2.00E·06
• •
DlOT 1.0SE-13 2.S0E-13 5.3SE-13
O.OOE+ OO

27 60
GDIOT S.68E-14 2.49E-14 6.82E-14

Tem perot ure( O C)

Table lll: Comparison of Power Delay Product between DIOT and
Fig.!O Power Consumption Vs Temperature for
GDIOT (Proposed) SRAM Cells at 32 nm technology
Different SRAM Cells at 45nm technology

Different Power Delay Product ( WaU

j .:' Ut-Uf
SRAM Seconds)
J .0 0 [-0 7
� Cells
2.5{1 E"{) 7
�... Vdd =lv Vdd=1.3 Vdd=1.6Sv
'S. 2 .00E·Q7
2v
....... n1 f T
� 1 .50E·Q7
DlOT 2.52E-15 4.91E-14 1.54E-13
� l.UUt-Uf
....... G)1 0T

� GDIOT S.74E-18 7.20E-18 6.89E-17

�

f � .OO[-OI3

{I.{I0E·;.Q O

17 60 V. CONCLUSION
T� m l=eri31t urel °(l As the battery-operated devices are in great demand
Fig.!l Power Consumption Vs Operating Temperature for to increase their reliability, the life time of battery is a
Different SRAM Cells at 32nm technology prime concern but this is done at the cost of speed. In
this paper, proposed circuit is presented for reducing
c. Simulation Environment power consumption through scaling the supply
Tables I, II and III shows that the comparison for voltage as compared to conventional circuit by
both the SRAM cell at different Vdd. It can be applying various technologies.
concluded that the proposed design has considerable
better results. By comparing the Differential lOT ACKNOWLEDGEMENT
SRAM cell and the Gated Differential lOT SRAM
cell design, the power consumption of the Gated We would like to sincerely thank Prof. B.P Singh,
Differential SRAM cell is very less than that of the Head of Department of Electronics &
Differential lOT SRAM cell by adding gated-ground
Communication, Mody Institute of Technology and
nMOS transistor. The Differential lOT SRAM cell is
Science, Lakshmangarh who inspired us to do this
simulated with different technologies by considering
work. In addition, we would like to thank Prof P.K
different parameters. Differential lOT SRAM Cell
shows the least power delay product over a range of Das, Dean, Faculty of Engineering, Mody Institute of
supply voltages. For low power memory applications, Technology and Science for providing us resources to
the Gated Differential SRAM memory cell is carry out our work.
appreciable.

REFERENCES
Table I: Comparison of Power Delay Product between D1OT and
GDIOT (Proposed) SRAM Cells at 90 nm technology
[I] Kang, Sung-Mo, Leblebici and Yusuf (1999), "CMOS
Different Power Delay Product ( WaU
Digital integrated Circuits Analysis and Design",
SRAM Seconds) McGraw-Hill International Editions, Boston, 2nd
Cells Edition.
Vdd =lv Vdd=1.07 Vdd=1.32 [2] C-T. Chu. X. Zhang. L. He and T. Jing. "Temperature
aware microprocessor floor planning considering
v v
application dependent power load", in Proc. of
DlOT 3.04E-15 4.S4E-15 1.78E-14 ICCAD.2007. pp. 586-589.
[3] MI.Sreenivasa Rao. S.Raghavendra. B.S.N.S.P.
GDIOT 2.23E-17 4.60E-17 1.07E-16 Kumar,"low power sram design technique". 1st

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international conference on Signal processing and VLSI

design, June 2001.
[41 S. Dutta, S. Nag, K. Roy, "ASAP: A Transistor Sizing
tool for speed, area, and power optimization of static
CMOS circuits", IEEE International Symposium on
Circuits and Systems, pp. 61-64, June, 1994.
[5] Hiroki Noguchi et aI., "Which is the best dual port
SRAM in 45nm process technology? 8T, l OT single
end and lOT differential" Renesas Technology
corporation, 2008.
[6] A. P. Chandrakasan, S. Sheng, and R. W.
Brodersen,"Low-power CMOS digital design,' IEEE 1.
Solid-StateCirc.,vol. 27, no. 4, pp. 473-484, Apr. 1992.
[7] 1. Chen, L.I. Clark and I.-H. Chen, "An ultra-Iow­
power memory with a subthreshold power supply
Voltage," IEEE Journal of Solid-State Circuits,vol. 41,
no. 10, Oct. 2006, pp. 2344-2353. no. 2, Feb. 2000,
pp.175-185.
[8] 1. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated Circuits, Prentice-Hall,2003. Amrutur and
M. Horowitz, "Speed and power scaling of
SRAM's,"IEEE Journal ofSolid-State Circuits, vol. 35.
No.2, Feb. 2000 , pp.175-185.
[9] Andrei Pavlov & Manoj Sachdev, "CMOS SRAM
Circuit Design and Parametric Test in Nano-Scaled ".
Intel Corporation, University of Waterloo, 2008
Springer Science and Business Media B.Y., pp: 1 202

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