1) Design a D-FF with asynchronous reset and convert D-FF into T-FF.

Write a Verilog module and

test bench to verify the performance.

`timescale 1ns / 1ps

module dff (clk, reset, d, q);

input clk;

input reset;

input d;

output q;

reg q;

always @(posedge clk or posedge reset)

begin

if (reset)

// Asynchronous reset when reset goes high

q <= 1'b0;

else

// Assign D to Q on positive clock edge

q <= d^q; // just d on rhs for d FF

end

endmodule
// Testbench #11 D=1; // t=11

module test; #9 reset=1;

#1 reset=0; // t=21

reg clk = 0; #40 D=1; // t=61

reg reset; #7 reset=1;

reg D; #2 reset = 0; // t=70

wire q; #10 D=1; // T=80

#10 D=0; // T=90

// Instantiate design under test end

dff DFF(.clk(clk), .reset(reset), always

.d(D), .q(q)); #5 clk = ~clk; // 100 Mhz clock

initial begin initial

$monitor("%b %b %b %b",$time,clk,D,q); #200 $finish; // Run for 200 ns

// Provide some input bits endmodule

2) Design a mod-4 binary counter using T-FF in behavioral style. Use this mod-4 counter to design a

mod-64 counter in a structural fashion. Write a verilog code for the mod-64 counter and show with

the waveforms that your design operates correctly.

3) Design a state-machine for the sequential circuit shown in Fig.1. Write a verilog module and show

with the waveforms that your state-machine operates correctly.

4) Design a state-machine for the sequential circuit shown in Fig.2. Write a verilog module and show

with the waveforms that your state-machine operates correctly.

5) Design a 4-bit binary ripple counter using D-FFs. Develop a verilog module and verify the perfor-

mance through a verilog test bench.

6) Design a 4-bit 4-state ring counter. Write a verilog module of your design and verify the performance

through a verilog test bench.

7) Design a 4-bit self-correcting ring counter. Write a verilog module of your design and verify the

performance through a verilog test bench.

8) Design a 4-bit binary serial-in, serial-out shift register using D-FFs. Write a verilog module of your

design and verify the performance through a verilog test bench.

9) Design a 4-bit binary serial-in, parallel-out shift register using D-FFs. Write a verilog module of

your design and verify the performance through a verilog test bench.

`timescale 1ns/1ps

// 4-bit shift register

module shift (

input clk, // system clock

input D,

output reg [3:0] Q=0);

always @(posedge clk) begin

Q[3]<=D;

Q[2]<=Q[3];

Q[1]<=Q[2];

Q[0]<=Q[1];

end

endmodule

`timescale 1ns/1ps

//Test shift register

module testbench;

reg clk=1;

reg D=0;

wire [3:0] Q;

wire Q0,Q1,Q2,Q3;

assign Q0=Q[0];
assign Q1=Q[1];

assign Q2=Q[2];

assign Q3=Q[3];

// Instantiate shift register

shift s1(

.clk(clk),

.D(D),

.Q(Q));

initial begin

$monitor("%d %b %b %d",$time,clk,D,Q);

// Provide some input bits

#11 D=1; // t=11

#10 D=0; // t=21

#40 D=1; // t=61

#10 D=0; // t=71

#10 D=1; // T=81

#10 D=0; // T=91

end

always

#5 clk = ~clk; // 100 Mhz clock

initial

#200 $finish; // Run for 200 ns

endmodule
10) Design a 4-bit binary parallel-in, serial-out shift register using D-FFs. Write a verilog module of

your design and verify the performance through a verilog test bench.

11) Design a 4-bit binary parallel-in, parallel-out shift register using D-FFs. Write a verilog module of

your design and verify the performance through a verilog test bench.