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    @ CHAPTER | O ADDERS AND SIMPLE ALU, "| wrote this book and compiled in it everything that is necessary for the computer, avoig, boring verbosity and misleading brevity.” Af in ag —Ghiyath al-Din Jamshid al-Kashi, The Key to Computing (Miftah al-Hisabi), 1427 Thus it appears that whatever may be the number of digits the Analytical Engine isc holding ifit is required to make all the computations with k times that number ofdigig eof be executed by the same Engine, but in the amount of time equal to k° times the formers ey — charles Babbage, Passages from the Life ofa Philosopher, 1864 TOPICS IN THIS CHAPTER 10.1 Simple Adders 10.2 Carry Propagation Networks 10.3 Counting and Incrementation 10.4 Design of Fast Adders 10.5 Logic and Shift Operations 10.6 Multifunction ALUs ‘Addition is the most important arithmetic operation in digital computers. Even the simp embedded computers have an adder, whereas hardware multipliers and dividers are fon only in higher performance microprocessors. In this chapter, we begin by considering he sign of single-bit adders (half- and full adders) and show how these building blocks cai cascaded to build ripple-carry adders. We then proceed to the design of faster adders buy means of carry lookahead, the most widely used carry prediction method. Other topics o ered include counters, shift and logic operations, and multifunction ALUs. f@ 10.1 Simple Adders In this chapter, we cover only binary integer addition and subtraction. Fixed-point nuntes that are both in the same format can be added or subtracted like integers by simply ignore the implied radix point. Floating-point addition will be covered in Chapter 12. When two bits are added, the sum is a value in the range [0, 2] that can be represented) ‘a sum bit and a carry bit. The circuit that can compute the sum and carry bits is known ast 10.1 Simple Adders 179 x) yy Inputs Outputs 1 @ ofo o a Chiat -O) 1 ier) Hs 1 iti o | Figure 10.1. Truth table and schematic diagram for Ui a binary half-adder. Inputs Outputs o 0 oo 0 0 1 0 1 Oe eOseOn 1 cee nein TpaO 1 0 oO co) 1 1 0 1 i oO i. oa Figure 10.2 Truth table and schematic diagram for a binary full adder. binary half-adder (HA), with its truth table and symbolic representation shown in Figure 10.1 The carry output is the logical AND of the two inputs, while the sum output is the exclusive OR (XOR) of the inputs. By adding a carry input to a half-adder, we get a binary full adder (FA) whose truth table and schematic diagram are depicted in Figure 10.2. Several imple- mentations of a full adder are shown in Figure 10.3 A full adder, connected to a flip-flop for holding the carry bit from one cycle to the next, functions as a bit-serial adder. The inputs of a bit-serial adder are supplied in synchrony with aclock signal, one bit from each operand per clock cycle, beginning from the least significant bits. One bit of the output is produced per clock cycle, and the carry from one cycle is held and used as input in the next cycle. A ripple-carry adder, on the other hand, unfolds this sequen- tial behavior into space, using a cascade of k full adders to add two k-bit numbers (Figure 10.4). The ripple-carry design of Figure 10.4 becomes a radix-r adder if each binary full adder is replaced by a radix-r full adder that accepts two radix-r digits (each encoded in binary) and a carry-in signal, producing a radix-r sum digit and a carry-out signal. Clearly, when all the intermediate carry signals c; are known, the sum bits/digits are eas ily computed. For this reason, discussions of adder design usually focus on how alll the intermediate carries can be derived, given the input operands and cjg. Because the carry signals are always binary and their propagation can be made independent of the radix r, as discussed in Section 10.2, from this point on, we often do not deal with radices other than 2. Note that any binary adder design can be conyerted to a 2’s-complement adder/subtractor through the scheme shown in Figure 9.6. For this reason, we will not discuss subtraction as a Separate operation. 180 Chapter 10/ Adders and Sim ple ALUS {b) CMOS mux-based FA 10.3 Full adder implemented with two half-adders, by means of two 4-inpt om les are generated at certain digit positions. which the sum of operand digits is 10 or mi t both operand bits be 1. We define the au at which a carry is generated and 0 else’ logical AND of the operand bits x, incoming carry is propagated, For h the Operand digits equals 9; an incoming ¢ to ar poziein g carry from that position, Of con 81 10.2 Carry Propagation Networks ihilated orkilled propagated 0 | generated impossible) 0 0 1 1 5 Figure 10.5 The main Part of an adder is the carry network.The rest is just a set of gates toproduce the g and P signals and the sum bits. carry-in, there won't be a carry-out for such positions. In binary addition, carry propagation Tequires that one operand bit be 0 and the other one be 1. The auxiliary binary signal p,, de- nyed as pi = x; © y; for binary addition, is defined as being 1 iff digit position i propagates an incoming carry. Now, given the carry-in cy of an adder and the auxiliary signals g; and p, for all of the k digit positions, the intermediate carries ¢, and the outgoing carry c; can be derived indepen- dently from input digit values. In a binary adder, the sum bit in position i is then derived as S = % Oy Be, = pi Ge; general structure of a binary adder is shown in Figure 10.5. Variations in the carry net= srk result in many designs that differ in their implementation costs, ‘operational speed, zy consumption, and so on. e Each full adder requires some time to generate its carry output based on its carry input in that position, Cascading k such units together implies k times as much ystem that is dedicated to a single task and is not expected to be fast. ipple-carry adder in the general framework of Figure 10.5, we note that the carry inple-canyiadder is based on the recurrence: iH = BLY Dice VB2_—_ Chapter 10 / Addets and Simple ALUs + Be Pes fh Pr ans ry - cH Figure 10.6 The carry propagation network of a ripple-carry adder. This recurrence simply says that a carry will go into position i + 1 if it ig position ior ia cary that enters position fs propagated by postion i. This observaign to Figure 10.6 as the carry network of a ripple-carry adder. The linear lateney of adder (2k gate levels for the carry network, plus a few more for deriving the and producing the sum bits) is evident from Figure 10.6. Example 10.1:Variations in adder design We say that in digit position #, a tran a carry is generated or propagated. For binary adders, the auxiliary transfer signal 4 can be derived by an OR gate, given that gi V pi = xiyi + (1 ® 1) = 3, Vie gate is faster than an XOR gate, so t; can be produced faster than pj. ‘a, Show that the carry recurrence c1 = gi V pic; remains valid if we repla b, How does the change of part a affect the design of a carry network? ¢. In what other ways does the change of part a affect the design of a binary | solution Li Ia. We show thatthe two expressions gy ¥ prev and gr V ti; are equivalent to the other: g V pici = gi V gici V Pici = Bi V (Bi Y Pic: = Bi Vie the first step of our conversion, inclusion of the additional term gic) BY Bic; = 8i(1V c)) = gi; in other words, the term gic; is redundant, b, Because changing p; to 4) does not affect the relationship between ci) a the carry network will change if we supply it with 1; instead of p,. The speed between f; and p; leads to slightly faster production of the carry s ©. We need to include k additional two-input OR gates to produce the signals the signals p, for the sake of producing the sum bits s; = p; ® ¢; once all Known. Nonetheless, the adder will be slightly faster overall, because the derived concurrently with the functioning of the carry network, which is be longer. There are a number of ways to speed up carry propagation, leading to method, which is conceptually quite simple, is providing skip paths in a rip For example, a 32-bit carry network can be divided into eight 4-bit se AND gate allowing the incoming carry of position 4 to go directly to the en case P4j = P4j+1 = Paj+2 = P4j+3 = 1. One 4-bit section of the resulting © spanning bit positions 4/ through 4j + 3, is depicted in Figure 10.7, Note that such an adder with 4-bit skip paths is still linear in k, although it is much lows simple ripple-carry adder, Faster propagation of carries through skip paths 103 Counting and ncrementation 183 a Bisa Pasa Buys Pyar by Pete or oh a as iss cys Cre cyuY % Figure 10.7 A4-bit section of a ripple-carry network with skip paths. a ee wee Freeway Figure 10.8 Driving analogy for carry propagation in adders with skip paths. Taking the freeway allows a driver who wants to travel a long distance to avoid excessive delays at many traffic lights. drivers reducing their travel times by using a nearby freeway whenever the desired destination "_ ismore than a few blocks away (Figure 10.8). Example 10.2: Carry equation for skip adders We saw that a ripple-carry adder directly | implements the carry recurrence ¢;.-1 = g; V pic;. What is the corresponding equation for the ripple-carry adder with 4-bit skip paths, depicted in Figure 10.7? Solution: It is evident from Figure 10.7 that the carry equation remains the same for any position Whose index iis notamultiple of 4. The equation for the incoming carry into position i = 4) +4 becomes c4j+4 = 84j43 V P4j+3C4)43 V Paj43 P4j42P4j+1P4jcsy- This equation essentially says that there are three ways (not mutually exclusive) in which a carry can enter position 4) +4: by being generated in position 4) +3, through the propagation of a carry entering position 47 +3, or via the carry into position 4j being passed along the skip path. > discussing some of the common ways in which the process of addition is speeded up nodern computers, let us consider an important special case of addition, that of one of the ‘ands being a constant. If we initialize a register to a value x and then repeatedly add a to it, the sequence of values x, x + a, x + 2a, x +3a, ... will be obtained. This is known as counting by a. Figure 10.9 shows a hardware implementation of this Chapter 10/ Adders and Simple ALUs Data in Iner'Init Update Figure 10.9 Schematic diagram of an initializable counter. i Se-2 % 10.10 Carry propagation network and sum logic for an incrementer. using an adder whose lower input is permanently connected to the ca ‘counter can be updated in two different modes: incrementation causes the co unter “next value in the sequence above, and inifialization causes an input data value the register. The special case of a=1 corresponds to standard up countei x,x+1,x+2,x+3,..., whereas a =—1 produces a down counte the order x, x — 1, x —2,x —3, ...; an up/down counter can count upwi depending on the value of a direction control signal. If in the process o ing we go past 0, the counter is conveniently set to the appropriate 2’ tive value. Both up and down counters may overflow when the co or too small to be represented within the number representation for of unsigned up counters, overflow is indicated by the carry-out of the ad serted. In other cases, counter overflow is detected in the same manner as Section 10.6). Let us now focus on an up counter with a stant | to the lower input of the adder as in Figure 10.9, we can set Cia lower adder input. Then, the adder becomes an incrementer whose design SI pler than an ordinary adder. To see why, note that in adding y = Oto x, nals g; = x;y; = 0 and propagate signals p; = x; @ y; = x;. Hence, propagation network of Figure 10.6, we see that all the OR gates as well gate can be eliminated, leading to the simplified carry network in wekaias aah 10.4 Design of Fast Adders 185 Jater that methods used to faster incrementers as wel] Amachine’s program Counter is an exa ; "the next instruction as the BUR i example of an up counter that is incremented to point to Rieerlice cuily ihithe ip iaichian ay cae executed. The PC incrementation usually pletion, implying that a superfast in the PC is incremented not by 1 but such as 2" is the same as ignoring part. Peed up carry propagation adders can be adopted for designing A variety of fast g 'y of fast adders can be designed that require logarithmic, rather than linear, time. In t eet marae’ of such fast adders grows as the logarithm of &. The best-known and eet ¥ used such adders are carry-lookahead adders whose design is discussed in this ‘ )_ The basic idea in carry-lookahead addition is to form the required intermediate carries directly from the inputs gi, p,, and cq to the carry network, rather than from the previous carries, as done in ripple-carry adders. For example, the carry cy of the adder in Figure 10.4, __ which was previously expressed in terms of c> using the carry recurrence f 3 = 82 prez can be directly derived from the inputs based on the logical expression: 63 = 82 V P2gi Y p2Pig0 V prPi Poco _ This expression is easily obtained by unrolling the original recurrence, that is, replacing c2 _ with its equivalent expression in terms of c; and then expressing c in terms of cp. In fact, one "could write this expression directly based on the following intuitive explanation. A carry into _ position 3 must have been originated at some point to the right of bit position 3 and propagated fom there to bit position 3. Each term on the right-hand side of the foregoing equation covers ‘one of the four possibilities. Theoretically, one can unroll all carry equations and obtain each of the carries as a two- Jevel AND-OR expression. However, the fully unrolled expression would grow quite large for wider adder that requires ¢31 oF ¢52, say, to be derived. A variety of lookahead carry networks ist that systematize the preceding derivation for all the intermediate carries in parallel and ake the computation efficient by sharing parts of the required circuits whenever possible. ious designs offer trade-offs in speed, cost, VLSI chip area, and energy consumption. In-~ ation on the design of lookahead carry networks and other types of fast adder can be found in books on computer arithmetic [Parh00]. Here, we present just one example of a lookahead carry network. The building blocks of this network consist of the carry operator, which combines the generate and propagate signals for two adjacent blocks {i + 1, j] and (h,é] of digit positions into the respective signals for the wider combined block {/, j]. In other words, (+L let i=h fl re ¢ designates the carry operator and [a, 5] stands for (8{a,0); Pla.o)) Tepresenting the air of generate and propagate signals for the block extending from digit position a to digit 186 Chapter 10/ Adders and Simple ALUs V7) 16,6) 15,5) 14,4) 3,3) 2,2) 1,1) 10,0) 80.11 Pony Y Y 17) (0,6) 10,5) (0,4) 10,3) 10,2) [0,11 10,01 } Figure 10.11 Brent-Kung lookahead carry network for an 8-digit adder, along with details, the carry operator blocks. nan Of ney agi i sition b. Because the problem of determining all the carries ¢41 is the same. the cumulative generate signals gjo,), network built of ¢ operator blocks icted in Figure 10.11, can be used to derive all the carries in parallel. espond to generate and propagate signals for a radix-4 a consists of 2 bits in the original binary number. The re the last row, compute all the required intermediate carrie basically consist of every other carry (even-numbered one n, All that remains is for the bottom row of carry operators to su d-numbered carries. Ook Figure 10.12 accentuates this recursive structure by showing how the 8 network of Figure 10.11 is composed of a 4-input network of the same type “carry operators, one row at the top and one at the bottom. This leads to @| “ing to roughly 2log,k carry operators (2 rows, times logak levels of Fe proximate cost of 2k operator blocks (roughly k blocks in the two rows at blocks, k/4 blocks, ete), The exact values are slightly less: 2 logk = 2 le 2k — log)k — 2 blocks for cost, é Instead of combining the auxiliary carry signals two at a time, lea can do four-way combining for faster operation. Within a 4-bit group, 10.4 Design of Fast Adders 187 17,71 1661 15,5) 14,4) BA 221 nn 10,0) | | | oF « 4-input Brent-Kung carry network ‘ ¢ Figure 10.12 Brent-Kung look- ahead carry network for an &-digit adder, with only its top and bottom rows of carry operators (0,7) (0,6) [0,51 (0,4) (0,31 {0,21 (0,1) (0,0) shown, 0 to 3, the group generate and propagate signals are derived as: 8(0,3] = 83 V P382 V P3p281 V Psp2Pi80 P03) = P3P2P1 Po Once g and p signals for 4-bit groups are known, the same process is repeated for the result- ing k/4 signals pairs. This eventually leads to the derivation of the intermediate carries C4, C8, C12, Cis, and So on; that is, one in every four positions. The remaining problem is deter- mining the intermediate carries within 4-bit groups. This can be done with full lookahead, For example, the carries c), ¢2, and cy in the rightmost group are derived as: ©1 = 80 Poco 2 = 81 V PiBo V Pi poco 82 V p281 V p2P180 V P2P1 Poco C3 The resulting circuit will be very similar in structure to the Brent-Kung carry network, except that the top half of rows will consist of group g and p production blocks and the bottom half will be intermediate carry production blocks just defined. Figure 10.13 shows the designs of these two block types. An important method for fast adder design, which often complements the carry-lookahead scheme, is carry-select. In the simplest application of the carry-select method, a k-bit adder is built of a (k/2)-bit adder in the lower half, two (k/2)-bit adders in the upper half (form- ing two versions of the k/2 upper sum bits with cx2 = 0 and c,y2 = 1), and a multiplexer for choosing the correct set of values once cj/2 becomes known. A hybrid design, in which some of the carries (say, cg, c16, and c2¢ in a 32-bit adder) are derived via carry-lookahead and are then used to select one of two versions of the sum bits that are produced for 8-bit blocks concurrently with the operation of the carry network, is quite popular in modern arithmetic units. Figure 10.14 shows one part of such a carry-select adder, which chooses the correct version of the sum for bit positions a through b after the intermediate carry cg becomes known, 188, Chapter 10 / Adders and Simple ALUs S| sy g18 ce tad eins 5s SE giz i Pui) Bi i331 Cis ae a "Figure 10.13 Blocks needed in the design of carry-lookahead adders with four-way group a Version 0 of sum bits: 5. For example, the ang, or, 20) y implemented in this way. Cont another matter that will be 105 Logicand Shift Operations 189 Right-shifted \ Left shifted values values _— j HA 00...0, x(31) ih x{0}, 00...0 right'left 00, x{30, 2) ; x{1, 01, 00...0 Shiftamount 9, x13 11| me a | x131, 0) \ 5 | x{31, 0) | os a 32 32 a 32 a a Lasldeat son Puree Po EL See 62 63 a Multiplexer E-bit code specifying shift direction & amount 32, Figure 10.15 Multiplexer-based logical shifting unit. S-bit binary number (0 to 31 bits) Conceptually, this can be accomplished by using a 64-to-1 multiplexer with 32-bit inputs (Figure 10.15), Practically, however, the resulting circuit is too complex, particularly when other types of shift (arithmetic, cyclic) are also included. Practi- cal shifters use a multilevel implementation. After discussing the notion of arithmetic shifts, we will describe such an implementation. Shifting a k-bit unsigned number x to t E he left by h bits multiplies its value by 2", provided of course that 2/ * Is representable in k bits. This is because each 0 appended to the right of a _ binary number doubles its value (in the same way that decimal numbers are multiplied by 10 with each 0 appended to their right end). Somewhat surprisingly, this observation applies to k-bit 2’s-complement numbers as well. Given that the sign of a number should not change _ when multiplying it-by 2", the 2’s-complement number must have h + 1 identical bits at its _ leftend if itis to be multiplied by 2" in this manner. This will ensure that after h bits have been - discarded as a result of left shifting, the bit value in the sign position will not change. Logical right shifting affects unsigned and 2’s-complement numbers differently. An un- signed number x is divided by 2 when it is right-shifted by h bits, This is akin to moving the decimal point to the left by one position to divide a decimal number by 10. However, this method of dividing by 2! does not work for negative 2’s-complement numbers: such numibers become pi e when Os are inserted from the left in the c shifting. Proper division of a 2's-co1 number Tequires that the hits that enter from the left _ be the same as the sign bit (0 for positive and 1 for negative numbers). This process is know! a as arithmetic right shift, Given that dividing numbers by powers of 2 is quite useful, and very efficient when done through shifting, most computers have provisions for two types of right shift: logical right shift, which views the number as a bit-string whose bits are to be reposi- "tioned via shifting, and arithmetic right shift, whose purpose is to divide the numerical value "of the operand by a power of 2. _ MiniMIPS has two arithmetic shift instructions: “shift right arithmetic” and “shift right arithmetic variable.” These are defined similarly to logical tight shifts, except that sign exten- ‘sion occurs during shifting, as discussed earlier. sra $t0,/uSsiypq2i # set $t0 to ($s1) right-shifted by 2 Srav $t0;'$sl;, $s0 # set $t0 to ($s1) right-shifted by ($s0) Figure 10.16 shows the machine representations of these two instructions, Chapter 10 / Adders and Simple ALUs | Zz rs rt rd sh | 31 nd 25 20. 15 10 | 7 ofolofojofjofojo}ojo)oj1{o)° o]1]o]i|o/o]o}o|0}0\1lo}oJo Jia o ALU Unused Source Destination Shift - instruction regist register amount 3 oj ts rt rd sh 31 r 25 20 15 10 5 fn 7 7 7 7 T - ojofo}ofolo}i 0) 0)0)0)1 o}ojo}1}o)1 0|0)0}0/0)0 Ojo 0/09 Ll 1 ALU. ‘Amount Source Destination Unused = ! instruction register register register av Figure 10.16 The two arithmetic shift instructions of MiniMIPS. | 00 No shift 01 Logical left 10. Logical right ] ¥B1,9 11 Arith right x31), xB1, 1) 1 0, x(31, 1] x(30, 0], 0 x(31, 01 (0 or 1)-bit shit (a) Single-bit shifter (b) Shifting by up to 7 is Figure 10.17 Multistage shifting in a barrel shifter. We are now ready to discuss the design of a shifter for both logical and arithmetic sis First, consider the case of single-bit shifts. We want to design a circuit that can perform !*it logical left shift, 1-bit logical right shift, or 1-bit arithmetic right shift based on control signals provided, It is convenient to consider the case of no shifting as a fourth possibility and use tt encoding shown in Figure 10.17a to distinguish the four cases. If the input operandis +8) 0 the output should be x{31, 0] for no shift, x{30, 0] appended with 0 for logical left shift, aGhll preceded by 0 for logical right shift, and x{31, 1] preceded by x[31] (i.e., a copy of the signbi for arithmetic right shift. Hence, a 4-input multiplexer can be used to perform any of tet shifts, as depicted in Figure 10.17a. Multibit shifts can be performed in several stages using replicas of the circuit sh Figure 10.17a for each stage. For example, suppose logical and arithmetic shifts are beret formed with shift amounts between 0 and 7, provided as a 3-bit binary number: 7 nS stages shown in Figure 10.17b realize the desired shift orming a-bit shill based on the most significant bit of the shift amount. This converts the ii jown it 10.6 Multifunction ALUs 191 32-pixel (4 8) block of al | black-and-white image: Representation _Row0 as32-bitword: 1010 000 Hex equivalent 80617 Figure 10.18 A 4 x 8 block 32-bit word. ck of a black-and-white image represented as a [31,0 i 04 2! re memnediate value y is then subjected to a 2-bit shift if the middle bit of the caesar SHORTS to the result z. Finally, z is shifted by [bit if the least significant bit ofthe shift amount is 1. The multistage design of Figure 10.17b is known as a barrel shifer Itisa simple matter to add cyclic shifts, or rotations, to the designs of Figure 10.17. ; __ Logical and shift instructions find many applications. For example, they can be used for identifying and manipulating fields or individual bits within words. Suppose that you want to pease 10 through 15 in a 32-bit word. One way to do it is to AND the word with the 0000 0000 0000 0000 1111 1100 .0000 0000, which has Is in the bit positions of interest and Os elsewhere, and then shift the result right _ (logically) by 10 bits to bring the bits of interest to the right end of the word. At this point, the resulting word will have a numerical value in the range (0, 63] depending on the contents of the original word in bit positions 10-15. ‘Asa second example, consider a 32-bit word as representing a4 x 8 block of a black-and- “white image, with 1 representing a dark pixel and a white pixel (Figure 10.18). The pixel values can be individually identified by alternately performing 1-bit left shifts and checking the sign of the number. An initial test identifies the first pixel (a negative number means 1), ‘After one left shift, the second pixel can be identified by testing the sign. This can be contin- ued until all the pixel values are known. fifunction ALUs "We can now put everything we have discussed in this chapter together and present the design ‘ofa multifunction ALU that can perform add/subtract, logic, and shift operations. We consider only the arithmetic/logic operations needed for executing the instructions in Table 5.15 that “is, add, subtract, AND, OR, XOR, NOR. The overall structure of the ALU is shown in igure 10.19, It consists of three subunits for shifting, adition/subiraction, and logic operations. ¢ output of one of these subunits, or the MSB of the adder output (the sign bid), O-extended oa full 32-bit word, can be chosen as the ALU output by asserting the “function class” control ignals of the 4-input multiplexer, In the remainder of this section, we describe each of the subunits in the ALU. First, let us focus on the adder. This is the 2’ What has been added here is a 32-input NOR circuit w 's-complement adder described in Figure 9.6. hose output is 1 iff the adder output is 192 ——_ Chapter 10 / Adders and amount J simple ALUs 00. No shift Const'Var shit function [9 Topical et ‘ de 10. Logical right coo Amount 1 bia Arith right iiblepaes shitter |) amount| > pass a 32 eT Function ¢ 00. Shift BEG class} 01 Set less 5 1sBsf ae | 42 li Arithmetic | [ \ shifted 11. Logic | a a Shorthand 2 symbol eehssaia aa nost be aes Logic |} | input ea unit ee AND 00) Fr i ' ' ' ! ' or 01 a \ y XOR 10 { NOR. 11 J Logic function Zero ovil Figure 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic 3 shiq 2 logic) specifying the operation. serves to detect overflow. Overflow in 2’s-complement perands are of the same sign and the adder outpatsol teil 0 (all-Os detector) and an XOR gate that arithmetic occurs only when the input 0} the opposite sign. Thus, denoting the Signs of the inputs and output by 31,31, and rowing expression for the overflow signal is easily derived: Ovfl = x51 Yar831 V *41 951531 is that an overflow occu ‘An equivalent formulation, whose proof is left as an exercise, arry-out (32): Thisist when the next to the last carry of the adder (c3,) is different from its c way overflow detection is implemented in Figure 10.19. Next, we consider again the barrel shifter (Figure 10.17). Because MiniMIPS has te classes of shift instruction with constant shift amount (given in the “sh” field of the inst tion) or variable shift amount (supplied in a designated register), a multiplexer is used! cree the appropriate amount to the shifter. Note that when the shift amount is giverin aegis only the least significant 5 bits of the amount are relevant (why). ‘ “The logic unit realizes one of the four bitwise logical operations of AND, OR xor,NO! So, the design of the logic unit essentially consists of four arrays of logic functions and a 4-input multiplexer that allows us to choose which set of re warded to the unit’s output, gates computing sults 1S Finally, supplyin plexer needs some value is 0 if the si, menting the s Msttuction of depending on Whether oF not x + looking at the sign bit of the result it in the designated register; citedliu 0 as its output when its “function, class” the MSB of the explanation, ‘The gh bitis 0 and | can be realized with an AND gate and gate, Show that it can also be realized with: input NAND gates and an inverter (or gihno inverter if the Cou: Signal is produced in yerted form) oe ee 2-input NOR gates and two inverters (or sh no inverter if X and’y inputs are available in (0.36 and derive the delay of the critical, gure 10.4 in terms of mux and inverter it was shown that inserting an of | through the adder’s carry-i lesign. Show that similar simplifica- ible for unit decrement (addition of —1). Versatile building blocks ider can be used to realize many ons besides its intended function of ample, the adder implementing (€453525150) wo if the sign bitis 1 MiniMIps, Which re This condition the sign bitis 1, then x 0 must be Stored. This is Problems 193 Adder’s output as one of the inputs to the 4-input multi Sign bit is 0 D-extended to form a full 32-bit word whose his allows us to use our ALU for imple- quires that 1 or 0 be stored in a register can be checked by computing x ~ y and < y holds and 1 must be stored exactly what the ALU provides Signals that control the output multiplexer are set to O1 4®b@cOd Ge by setting xy (these lead t0 $ =a Gb c), x; lead toc = d), xy =e, Yo = b,c yi =d (these and using 52 as t binary adder can be A 5-input AND circuit A S-input OR circuit A circuit to realize the 4-variable logic function abv ed Two independent single-bit full adders, each with its own carry-in and carry-out A multiply-by-15 circuit for a 2-bit unsigned binary number (14,40)40 : AS-input “parallel counter” producing the 3-bit sum of five 1-bit numbers 10.5 Two’s-complement numbers Prove the following for k-bit 2’s-complement numbers x and y. a. A L-bit arithmetic right shift of x always produces |x/21, regardless of the sign of x. b. In the addition s = x + y, overflow occurs iff, Chal F Ck. ¢, Inan adder computing s = x + y but not producing a carry-out signal cy, the latter can be derived extemally as cy = Xp_,Yp-1 Vf yy Vy)» 10.6 Brent-Kung carry network Draw a diagram similar to Figure 10.11 that corresponds to the carry network of a 16-digit adder. Hint: Use the recursive construction depicted in, Figure 10.12, simple ALUS 194 Chapter 10 Adders and ookahead subtractor the carries i j, with no modi snd the borrows Bi 10.7 Borrow-l network producin e used At based on. Any carry : n a fication, 4 g, and p, Signals can b ‘borrow propagation circult © fi and borrow- ; _generate Yi a. Define the borrow-generale } si propagate; signals for bina) input operands: By Design a circuit to compute the difference digit di pom a7, and the ancoming POT b, Jos Carry lookahead incrementer a. In Section 10.3, we noted that an incrs computing x + 1, is much simpler than an adder and presented the design of a ripple carry incrementer. Design @ carry-lookahead incrementer, taking advantage of any simplification due to one operand being 0. b. Repeat part a for a porrow-lookahead decrementer. ementer, 10.9 Fixed-priority arbiter ‘A fixed-priority arbiter has k request input lines Rey -- Ri, Ro, and k grant output lines Gi- At each arbitration cycle, at most one of the grant signals is 1 and that corresponds to the highest priority request signal; ie. G; = 1 iff Ri = 1 and R= O for j

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