Da1 Verification

1.
Create a self-checking test-bench to verify the functionality of

a “101” sequence detector (DUT). The testbench should generate
random data and drive the random data as inputs to the DUT.
Simulate your design and show the results (screenshot of
transcript with valid display messages and waveform) for the
correct RTL code
VERILOG CODE FOR 101 SEQUENCE DETECTOR

module seq_detector(clk,rst,q,a);
input clk,a,rst;
output q;
reg q;
reg [1:0] cs=2'b00, ns=2'b00;
parameter s0=2'b00, s1=2'b01, s2=2'b10;
always@(posedge clk)
begin
if(rst)
cs=2'b00;
else
cs=ns;
end
always@(a or cs)
begin
case(cs)
s0:begin
if(a)
begin
ns=s1;
q=0;
end
else
begin
ns=s0;
q=0;
end
end
s1:begin
if(a)
begin
ns=s1;
q=0;
end
else
begin
ns=s2;
q=0;
end
end
s2:begin
if(a)
begin
ns=s1;
q=1;
end
else
begin
ns=s0;
q=0;
end
end
endcase
end
endmodule
SELF-CHECKING TESTBENCH
module seqtestbench();
reg a,clk,rst;
wire q;
reg [1:0] cs=2'b00,ns=2'b00;
parameter s0=2'b00,s1=2'b01,s2=2'b10;
reg new_q;
seq_detector dut (clk,rst,q,a);
initial
begin
rst=1'b1;
clk=0;
#20 rst=1'b0;
end
always #5 clk=~clk;
initial
begin
repeat(30)
begin
test_vector();
if(q==new_q)
begin
if(q==1 && new_q==1)
$display("101 sequence deteced");
end
else
$display("wrong sequence detected");
end
$stop;
end
task test_vector();
begin
a=$random;@(posedge clk);
end
endtask
begin
if(rst)
cs=2'b00;
else
cs=ns;
end
always@(a or cs)
begin
case(cs)
s0:begin
if(a)
begin
ns=s1;
new_q=0;
end
else
begin
ns=s0;
new_q=0;
end
end
s1:begin
if(a)
begin
ns=s1;
new_q=0;
end
else
begin
ns=s2;
new_q=0;
end
end
s2:begin
if(a)
begin
ns=s1;
new_q=1;
end
else
begin
ns=s0;
new_q=0;
end
end
endcase
end
endmodule
OUTPUT WAVFORM FOR 101 SEQUENCE DETECTOR
a is the input sequence, q is the output of the DUT and q_out is the self-checking test bench output to
compare with the actual output of DUT.
TRANSCRIPT WINDOW
Every time the sequence detected the above message is displayed

2. Insert a bug in the DUT and show the self-checking testbench
can identify the bug
VERILOG CODE WITH A BUG
module seq_detector_100(clk,rst,q,a);
input clk,a,rst;
output q;
reg q;
reg [1:0] cs=2'b00,ns=2'b00;
parameter s0=2'b00,s1=2'b01,s2=2'b10;
begin
if(rst)
cs=2'b00;
else
cs=ns;
end
always@(a or cs)
begin
case(cs)
s0:begin
if(a)
begin
ns=s1;
q=0;
end
else
begin
ns=s0;
q=0;
end
end
s1:begin
if(a)
begin
ns=s1;
q=0;
end
else
begin
ns=s2;
q=0;
end
end
s2:begin
if(a)
begin
ns=s1;
q=0;
end
else
begin
ns=s0;
q=1;
end
end
endcase
end
endmodule
OUTPUT WAVFORM OF SEQUENCE DETECTOR WITH A BUG
Here the sequence detected by sequence detector is 100 instead of 101.

the actual sequence detector needed to detect 101, this is verified by the self-checking testbench which compares the
incorrect output with the correct output and displays error message
TRANSCRIPT WINDOW
Here we can see the testbench indicates wrong sequence is being detected
3. Simulate the bug free DUT by enabling code coverage and

show the coverage results
COVERAGE REPORT IN TEXT FORMAT

This shows the DUT coverage and the testbench coverage.
4. a) Generate Netlist for the bug free RTL and perform Logic
equivalence check between the bug free RTL code and the
corresponding netlist using formality and show the results.
NETLIST GENERATED FOR BUG FREE RTL

module seq_detector ( clk, rst, q, a );
input clk, rst, a;
output q;
wire cs_1_, N7, N8, n5, n7, n8;
DFFX1_HVT cs_reg_0_ ( .D(N7), .CLK(clk), .QN(n7) );
DFFX1_HVT cs_reg_1_ ( .D(N8), .CLK(clk), .Q(cs_1_), .QN(n8) );
AND3X1_HVT U10 ( .A1(a), .A2(cs_1_), .A3(n7), .Y(q) );
INVX0_HVT U12 ( .A(rst), .Y(n5) );
OA221X1_HVT U13 ( .A1(1'b0), .A2(a), .A3(n8), .A4(n7), .A5(n5), .Y(N7) );
NOR4X1_HVT U14 ( .A1(n7), .A2(cs_1_), .A3(a), .A4(rst), .Y(N8) );
Endmodule
LOGIC EQUIVALENCE CHECKING BETWEEN BUGFREE RTL AND ITS NETLIST

Matching of 101 SEQUENCE DETECTOR AND ITS NETLIST
ALL THE PORTS OF RTL CODE AND ITS NETLIST ARE MATCHED
VERIFICATION OF RTL AND IMPLEMETED DESIGN
REFERENCE DESIGN
IMPLEMENTED DESIGN
b) Perform Logic equivalence check between the buggy RTL code
and the netlist generated using bug free RTL code and show the
results.
LOGIC EQUIVALENCE CHECKING BETWEEN RTL WITH BUG AND BUGFREE RTL NETLIST
Matching analysis
Here the 3 ports of reference are not matched to the implemented design.
Verification analysis

Da1 Verification

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1.

Create a self-checking test-bench to verify the functionality of

VERILOG CODE FOR 101 SEQUENCE DETECTOR

reg [1:0] cs=2'b00, ns=2'b00;

parameter s0=2'b00, s1=2'b01, s2=2'b10;

seq_detector dut (clk,rst,q,a);

if(q==1 && new_q==1)

$display("101 sequence deteced");

$display("wrong sequence detected");

OUTPUT WAVFORM FOR 101 SEQUENCE DETECTOR

Every time the sequence detected the above message is displayed

reg [1:0] cs=2'b00,ns=2'b00;

Here the sequence detected by sequence detector is 100 instead of 101.

3. Simulate the bug free DUT by enabling code coverage and

COVERAGE REPORT IN TEXT FORMAT

NETLIST GENERATED FOR BUG FREE RTL

input clk, rst, a;

wire cs_1_, N7, N8, n5, n7, n8;

DFFX1_HVT cs_reg_0_ ( .D(N7), .CLK(clk), .QN(n7) );

DFFX1_HVT cs_reg_1_ ( .D(N8), .CLK(clk), .Q(cs_1_), .QN(n8) );

AND3X1_HVT U10 ( .A1(a), .A2(cs_1_), .A3(n7), .Y(q) );

INVX0_HVT U12 ( .A(rst), .Y(n5) );

OA221X1_HVT U13 ( .A1(1'b0), .A2(a), .A3(n8), .A4(n7), .A5(n5), .Y(N7) );

NOR4X1_HVT U14 ( .A1(n7), .A2(cs_1_), .A3(a), .A4(rst), .Y(N8) );

LOGIC EQUIVALENCE CHECKING BETWEEN BUGFREE RTL AND ITS NETLIST

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