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1999 - Fully-Depleted SOI CMOS
1999 - Fully-Depleted SOI CMOS
1999 - Fully-Depleted SOI CMOS
F. SILVEIRA
Instituto de IngenierõÁa EleÁctrica, Universidad de la RepuÁblica Casilla de Correos 30, Montevideo, Uruguay
Received December 7, 1995; Revised September 3, 1996; Accepted December 12, 1996
Abstract. This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique
opportunities in the ®eld of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic
capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold
slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit
studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low
supply voltage of analog, digital and microwave components with properties signi®cantly superior to those
obtained on bulk CMOS. Experimental circuit realizations support the analysis.
capacitance reduction and the other 60% from the channel devices to suppress edge leakage currents and
drive current increase. A threefold enhancement of the growing a ®eld oxide to consume the remaining
power times speed ®gure of merit has been silicon in the ®eld area. A 30 nm-thick gate oxide is
demonstrated for 1 V supply voltage, in particular in grown and boron is implanted to adjust the threshold
the case of a 512 K SRAM [5]. Frequency dividers voltages, which for zero back gate-to-source bias, lie
operating at 1 GHz with a 1 V supply voltage have around 400 mV for the n-channel inversion-mode
also been realized in a 0.12 mm SOI CMOS process, devices and ÿ 700 mV for the p-channel accumula-
consuming only 50 mW [6]. tion-mode devices. When the devices are in operation,
The challenges for LVLP analog and microwave the threshold voltage of the p-channel devices
SOI CMOS circuits, however, have not been as increases through a back-gate bias effect, and the
widely investigated so far. Preliminary theoretical threshold voltages of both n- and p-channel devices
results nevertheless show that analog circuits, in become symmetrical ( + 400 mV for 3 V supply
particular op-amps, will bene®t from the lower body voltage and back substrate contact commun to all
effect and load capacitances in FD SOI CMOS [7±10]. devices ®xed at 0 V) [3]. Polysilicon is then deposited
On the other hand, preliminary experimental results and N-type doped using a solid phosphorous source.
also show that submicron FD SOI MOSFETs may After gate patterning, arsenic is implanted to form the
achieve transition frequencies in excess of 20 GHz for sources and drains, and 150 nm-thick spacers are
supply voltages on the order of 3 V [11]. Combined formed through oxide deposition and reactive ion
with the ability to realize low-loss matching or etching. A 30 nm-thick layer of titanium is then
interconnection lines on high-resistivity SOI sub- deposited and 2-step annealed in a rapid thermal
strates [12] and the drastic reduction of substrate annealing furnace to form TiSi2 on the gates, sources
crosstalk ®gures [13], these properties may lead to the and drains. This silicidation process allows for a sheet
future development of single-chip mixed digital/ resistance reduction from 35 to 6.2 O/square for the
analog/microwave solutions. gate material and from 300 to 6.3 O/square for the
In the present paper, the properties which make FD sources and drains. A nitride/oxide layer is deposited
SOI CMOS process and devices attractive for LVLP and contact holes are opened to access the devices.
applications will be brie¯y recalled. Then the LVLP Aluminum/silicon is then sputtered, patterned, sin-
performances of digital and analog building blocks tered and capped with a passivation oxide to complete
will be analyzed and compared to bulk. Finally, the the process. The ®nal silicon ®lm thickness is
microwave properties of SOI MOSFETs operated at 80 nm + 5 nm. The ®lm thickness nonuniformity
low voltage will be described. does not impair however the realization and control
of low threshold voltage values. The threshold voltage
sensitivity to ®lm thickness, usually stated as an
2. Fully-Depleted SOI CMOS Process and important problem for FD SOI MOSFETs, can indeed
Devices be minimized holding the ®lm total dose constant
rather than the doping concentration [14]. Threshold
a. Fabrication Process voltage standard deviations similar to bulk devices
have been achieved for FD SOI MOSFETs.
The devices which will be described next are In Fig. 1 a cross section of the devices is presented,
fabricated using a standard fully-depleted SOI and Fig. 2 shows the symmetrical current-gate voltage
CMOS process with N polysilicon gate. P-type characteristics of the devices with reduced threshold
SIMOX substrates having a resistivity of 20 or voltage and low leakage current.
500 O cm (the latter being used for microwave
transistors) are used as starting material. The initial
200 nm-silicon ®lm thickness is reduced to 100 nm by b. Properties of Fully-Depleted SOI MOSFETs
oxidation and oxide strip. The buried oxide thickness
is 380 nm. Semi-recessed LOCOS is used to isolate the One interesting feature of FD SOI MOSFETs is the
devices, which implies the deposition and patterning low value of the body-effect coef®cient, which
of a 200 nm silicon nitride layer, etching half the in¯uences both the current drive of the device and
thickness, implanting boron around the edges of the n- its subthreshold swing. The body-effect coef®cient,
Fully-Depleted SOI CMOS Technology 215
between gate voltage and surface potential. It is well where Cox , Coxb and tsi are the gate oxide capacitance,
known that FD SOI devices offer near-ideal coupling, the buried oxide capacitance and the silicon ®lm
which yields a value of n close to unity. thickness, respectively. From the above equations, it
The in¯uence of the body-effect coef®cient on the follows that the saturation drain current may be 30±
current drive of the device can best be understood by 40% higher in a FD SOI device than in a bulk device
using a simple device model. The saturation drain with similar parameters [3].
current of a MOSFET is given by the following A more accurate model for submicron devices
expression: would include velocity saturation and series resistance
1 W effects [15]. These tend to somewhat degrade the
IDsat mC
V ÿ VTH 2
1 superior current drive capability of FD SOI
2n ox L GS
MOSFETs as short channel lengths are considered.
It has been shown however that non-optimally
designed FD SOI transistors still present a 25%
current drive improvement over comparable bulk
devices for gate lengths down to 0.2 mm which could
be restored to superior values after correct device
structure optimization [16].
The subthreshold swing (inverse subthreshold
slope) of a MOSFET is also affected by the body
effect. Indeed, the subthreshold swing is given by the
following expression [3]:
kT
S(mV/dec) n ln
10
4
q
if the in¯uence of the interface traps is neglected. The
low value of n in FD SOI devices yields an
improvement of the subthreshold slope over bulk
devices. Almost ideal subthreshold swings of 60 mV/
dec at room temperature corresponding to the
predicted n values have been experimentally demon-
strated for optimally designed FD SOI MOSFETs
Fig. 2. Experimental drain current vs. gate voltage characteristics
of n- and p-channel SOI MOSFETs with symmetrical low threshold
with channel lengthes down to 0.2 mm [17]. As a
voltages (W=L 3 mm=3 mm, VDS 100 mV, VTHn 0:4 V, result, a lower threshold voltage can be used in SOI
VTHp ÿ 0:45 V). devices without jeopardizing the OFF leakage current,
216 D. Flandre et al.
Table 1. Experimental SOI and simulated bulk design parameters and performance of the 1-stage CMOS OTA of Fig. 10
CL 10 pF. The
bulk simulations used the same technology parameters as SOI simulations in good agreement with the measurements, except for the body effect
and junction capacitances. The gate oxide thickness is 30 nm. The n body factor was equal to 1.1 in SOI and 1.5 in bulk, while the drain
extension bottom capacitance per unit area Cjp
n and sidewall capacitance per unit length Cjswp
n of a p(n)-type device were equal to, in the SOI
case, Cjn Cjp 0:06 fF=mm2 , Cjswn Cjswp 0:05 fF=mm and in the bulk case, Cjn 0:18 fF=mm2 , Cjp 0:4 fF=mm2 , Cjswn 0:4 fF=mm,
Cjswp 0:5 fF=mm typically.
SOI Bulk
sumption. These upper values are limited by stability Concerning the output swing and noise perfor-
considerations because as we increase gm =ID for a mance, the results of the above analysis as a function
®xed current, the transistor sizes and capacitances are of fT were used to compute the total input-referred
increased and the phase margin hence decreased. The thermal noise power spectral density in bulk and SOI
bias current and mirror transistors are operated in from equations (10)±(11). The bulk to SOI noise ratio
stronger inversion
gm =ID 8. ranges from 1.54 for 100 kHz to 3.11 for 10 MHz. To
This OTA experimentally achieved a 103 dB-DC achieve the same thermal noise performance, lower
open-loop gain and a 271 kHz-transition frequency gm =ID values could be used in bulk for the current
over a 12.3 pF-load capacitance with a 60 -phase
margin and a total bias current of only 2 mA under a
3 V-supply voltage, in accordance with the targeted
and simulated speci®cations. The output swing was
almost equal to 2 V. We estimated that to achieve a
similar fT performance with same CL and phase
margin, the bulk implementation could have only used
gm =ID ratios of 19 and 17 for the input differential pair
and output cascode devices respectively and would
then have dissipated 45% more supply current for a
DC open-loop gain reduced by 8 dB. Furthermore, we
simulated that for higher transition frequencies, the
FD SOI bene®ts over bulk increase up to a reduction
of the supply current by a factor larger than 3.5 and an
improvement of the gain by more than 20 dB for fT
equal to 10 MHz (Fig. 12), even though the active
device gm =ID values have to be reduced towards
strong inversion (13 and 3.5 in SOI and bulk
respectively at 10 MHz). Similar results were partly Fig. 12. Comparison of simulated total current dissipation and
demonstrated in a previous analysis of Miller OTAs DC open-loop gain performance of the bulk and SOI cascoded
CMOS OTAs of Fig. 11 (with B-mirror ratio equal to 2) as a
[10]. In these estimations, the gm =ID ratios of both SOI function of the transition frequency. The computations were based
and bulk current mirrors were taken constant and on the EKV model using similar sets of parameters as in Fig. 8
equal to 5. and Table 1.
222 D. Flandre et al.
6. Conclusions
``The EKV model and the associated parameter extraction.'' in MicroelectroÁnica, Barcelona, Spain, working on the
HP IC-CAP Users Meeting, 1995. characterization and numerical simulation of SOI
25. J. P. Colinge, ``Thin-®lm SOI technology: the solution to many
submicron CMOS problems.'' in IEDM Technical Digest MOS process and devices. He is now at the
(Washington DC), pp. 817±820, 1989. Laboratoire de MicroeÂlectronique (DICE), Louvain-
26. D. Flandre, C. Jacquemin, and J. P. Colinge, ``Design la-Neuve, Belgium, as a Research Associate of the
Techniques for High-Speed Low-Power and High- National Fund for Scienti®c Research (FNRS,
Temperature Digital CMOS Circuits on SOI.'' in Proc. IEEE
Belgium) and an Invited Lecturer at the UniversiteÂ
International SOI Conference (Ponte Vedra Beach FL),
pp. 164±165, 1992.
catholique de Louvain giving courses on ``Integrated
27. E. A. Vittoz, ``Design of low-voltage low-power IC's.'' in analog circuit design''. He is currently involved in the
Proc. 23rd ESSDERC (Grenoble, France), pp. 927±934, 1993. development of digital and analog SOI MOS circuits
28. A. K. Agarwal, M. C. Driver, M. H. Hanes, H. M. Hobgood, for special applications, more speci®cally high-speed,
P. G. McMullin, H. C. Nathanson, T. W. O'Keefe, T. J. Smith, J. low-voltage low-power, microwave, rad-hard and
R. Szedon, and R. N. Thomas, ``MICROXTM ÐAn advanced
silicon technology for microwave circuits up to X-band.'' in high-temperature electronics.
IEDM Technical Digest, pp. 687±690, 1991. Dr. Flandre is co-recipient of the 1992 Biennial
29. R. N. Simons, ``Novel coplanar stripline to slotline transition Siemens-FNRS Award for an original contribution in
on high resistivity silicon.'' Electronics Letters 30(8), pp. 654± the ®elds of electricity and electronics. He has
655, 1994. authored or co-authored more than 90 technical
30. G. Dambrine, H. Happy, F. Danneville, and A. Cappy, ``A new
method for on wafer noise measurements.'' IEEE Transactions papers or conference contributions. He is a member
on Microwave Theory and Techniques 41(3), pp. 375±381, of the Advisory Board of the EU Network of
1993. Excellence for High-Temperature Electronics
31. P. P. J. Tasker, W. Reinert, B. Hugues, J. Braunstein, and M. (HITEN).
Schlechtweg, ``Transistor noise parameter extraction using a
50 O measurement system,'' in IEEE MTT-Symposium Digest,
pp. 1251±1254, 1993.
32. S. W. Wedge and D. B. Rutledge, ``Wave techniques for noise
modeling and measurement.'' IEEE Transactions on
Microwave Theory and Techniques 40(11), pp. 2004±2012,
1992.
Jian Chen was born in February 26, 1996, in Luiz Fernando Ferreira was born in Canela, RS,
Zheng Jiang, China. He got his B.S. and M.S. degree Brazil, in 1962. He received a B.Sc. degree in
from the Electronics Engineering Department of electrical engineering from the Federal University of
Fudan University, Shanghai, China, in 1988 and Rio Grande do Sul, Porto Alegre, RS, Brazil, in 1986,
1992, respectively. He is currently working as a and a M.Sc. degree from the Graduate Division on
research assistant and a Ph.D. candidate in the Computer Science, Microelectronics Group, Federal
Microelectronics Laboratory of Universite University of Rio Grande do Sul.
Catholique de Louvain, Louvain-la-Neuve, Belgium. From 1990 to 1992, he worked at the same
His research subject is on the development of CMOS- University as an Associated Researcher,
compatible Thin-Film SOI technology for microwave Microelectronics Group. In December 1993, he
and high-temperature applications. joined the Microelectronics Laboratory of the
Applied Science Faculty, Universite Catholique de
Louvain, Louvain-la-Neuve, Belgium. He is now
D. De Ceuster is currently at the Microelectronics pursuing a Ph.D. degree there. His research interests
Laboratory, Universite Catholique de Louvain, Place are in high frequency modeling of MOS/SOI
du Levant 3, 1348 Louvain-la-Neuve, Belgium. transistors and design of VHF networks.