NCCN 2010

Design and Implementation of Low Jitter PLL

with Low Power Dissipation for SERDES Application
Ravi L.S*1, G.H Asha#2, Chethan K.S #3 and A.L Choodarathnakar#4
1
For Correspondence: Research Scholar (E-mail: 1ravils2010@gmail.com)
1 ,4
Dept. of Electronics & Communication Engineering, Rajeev Institute of Technology, Hassan, INDIA.
2,3
Dept. of Electronics & Communication Engineering, Malnad College of Engineering, Hassan, INDIA.

Abstract— The increase in the use of handheld
devises and development of smart devices implant on to
human body has in-turn demanded from the VLSI industry
to shrink the device geometrics and power consumed by the
devices, without compromising with the performance. In due
regard to attain this, an attempt is made to cater the needs of
industry. The project work emphasize on the design, model,
simulate and verify digital PLL operating at 2.4 GHz
frequency and optimizing the design for low power
applications
This project work implements PLL (Phase Locked
Loop) consisting of phase frequency detector, simplified
charge-pump, level shifter, VCO (Voltage Controlled
Oscillator) and divider. The simplified charge-pump consists
of only four transistors and is used to match the charging and
discharging currents into the loop filter from the phase
frequency detector, the use of this simplified charge-pump
has led to the reduction of power and area of the complete
PLL module. A level shifter, implemented in the design can
be used to control the VCO control voltage in-order to get the
desired frequency from the VCO. VCO with a capability of
producing frequencies ranging from 2.4GHz to 2.8GHz is
designed the VCO output frequency can be tuned to any of
the frequencies in the above mentioned range. The complete
design is carried out, once the complete design is verified,
GDS II is extracted for the complete design.
The entire design is first modeled in MATLAB and
then block level design is carried out in Synopsys™ HSpice®
and then the schematic level implementation in Cadence™
Virtuoso® tools and the technology used is 0.18μm. The input
frequency of PLL is 100MHz with 50% duty cycle and output
of the PLL from the divider is 100MHz, with locking time of
0.8ns, jitter of 15ps and the power consumption of 5.998mW.
By implementing these two modifications in the PLL design,
has led to the decrease of the power by 40% and jitter by
50%.
Keywords-, WLAN, PLL, MATLAB, Cadence VSE, Jitter,
Charge Pump, VCO, PFD.
transmission and reception can take place in both directions
simultaneously. These chips are used in Ethernet systems,
wireless network routers, fiber optic communication systems, and
data storage applications. Specifications and speeds vary
depending on the needs of the client and on the requirements of
application.
Fig 1. Application of PLL in SERDES
Figure 1 represents the SERDES application top-level
block diagram and its operation. Transmitter section converts
a parallel data to serial data and for transmission over a
communication channel using SERializer and at the receiver
section serial data is converted to parallel data using DESerializer
for further processing. Coding of the data at transmitter and
decoding of data at the receiver can be done efficiently.
The integral part of the SERDES system will be a PLL
which governs the conversion of parallel data to serial data and
vice-versa. It functions as a clock generator and as clock recovery
at the receiver sections.
The thesis work comprises of MATLAB™ Simulink®
modelling of the entire system and block level simulation in
Synopsys™ HSpice® and implementing using Cadence™
Virtuoso® tools.
Figure 1.2 gives the brief idea about the lock range,
pull-in-range and pull-out-range in the PLL as well as stable and
unstable regions of PLL

I. INTRODUCTION
A transceiver chip that converts parallel data to serial
and vice-versa, for the channel to transmit over a long distance,
such devices are known as SERDES IC’s. SERDES (SERializer
DESerializer) is housed at both transmitter as well as receiver
sections. SERDES behaves as parallel to serial converter in
transmitter section and serial to parallel in receiver section. N
number of SERDES can be integrated at both receiver and
transmitter sections.
SERDES chips assist the transmission of parallel data
between two points over a communication channel as serial data Fig.2 PLL frequency ranges [2]
stream, reducing the number of channel and in-turn reducing the
number of connection at transmitter and receiver. Certain
SERDES IC’s are capable of full-duplex operation, data II. PHASE LOCKED LOOP

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A phase-locked loop is a closed loop system with
negative feedback. As the name implies the output signal
“locks” onto an incoming reference signal.
The most widely used components for RF frequency
synthesis in WLAN applications is the Phased Locked
Loop (PLL). This is mainly due to the superior phase noise
characteristics and the possibility of implementing an
integrated frequency synthesizer at a very low cost. PLLs
are also used in a variety of other applications such as
coherent communication systems, synchronous digital
systems, high speed serial transmission links, clock
distribution networks etc. In all of these applications a PLL
is used as a frequency synthesizer or frequency source
whose phase is often synchronized with a reference signal
or clock.
The PLL is used for clock generation at the transmitter
and for data recovery at the receiver side. The major
requirement of PLL is to maintain the phase and frequency
of the clock throughout the functioning of the systems.
Nowadays these are used in all the devices which deal with
transmission and reception of data over a communication
channel.
Fig.3. PLL top level architecture
Fig 3.shows the top level architecture of the PLL.
PFD (Phase Frequency Detector), Charge pump, loop
filter, VCO (Voltage Controlled Oscillator) and divider are
the major building blocks of PLL. Vref is input reference
signals, the Vctrl is the voltage signal to control the VCO
and VCO output voltage of VCO and Vdiv is the output
voltage of the divider.
A. Classification of PLLs
PLLs are broadly classified into three categories
 Analog or Linear PLL (LPLL).
 Digital PLL (DPLL).
 All digital PLL (ADPLL).
 Charge Pump PLL (CPLL)
B. Merits and Demerits
+ PLL can be used a noise suppressors
+ PLL can be used as a frequency synthesizer
+ PLL can be used for data encoding and decoding in a
communication system
- Cannot be used for generation of different frequencies at a
given instant of time
- Once unlocked requires time to regain its locked state
- System is prone to noise because of the components
- May loose performance with time, because of aging of the
components used
III. METHODOLOGY
 Literature review carried out on SERDES, types of
PLL, architectures of low jitter, low power PLL to
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meet the requirement by referring journals, books,
websites and related documents
 Top level design specifications of low jitter PLL
formulated based on the SERDES application
 Modified architecture for low jitter and low power
PLL designed as per the specifications and
reviewed literature
 Software reference model for sub blocks of low
jitter PLL for the identified architecture analyzed
 Architecture of each sub block derived based on
its SW reference model and the block level
specifications
 The PLL sub blocks of the software reference
model of low jitter PLL integrated and simulated
 Sub blocks of the low jitter PLL modeled and
simulated in Hspice®/LTspice® to meet the block
level design requirements
 Sub blocks of the low jitter PLL are integrated and
simulated in Hspice®/LTspice® to meet the
design requirements
 Schematics for the low jitter low power PLL
implemented using Cadence™ tools
 Layouts for the low jitter low power PLL
implemented using Cadence™ Virtuoso®
 Functionality of the designed low jitter PLL
optimized for power verified with respect to the
specifications
 Final GDSII is extracted for the design
The Figure 4 represents the complete PLL system
design flow and the steps involved in arriving at end product
Fig.4 Design flow for complete PLL system
A. Software Implementation
The complete design of PLL is carried out in MATLAB for
getting a relevant software reference model. The software
reference model plays a major role in design of blocks for the
entire system. Once the system functioning is validated, further
designs can be carried out
Simulation of Complete PLL model:
The complete PLL is modelled in MATLAB and
verified for its functionality, the software reference is found to be
functioning as per the requirements
 NCCN 2010

Fig.9 VCO schematics from Cadence VSE

Fig.5 Software reference of PLL System

Fig.10.Final PLL Schematic in Cadence Virtuoso Editor

Fig6 Final complete simulation of PLL system

B. Design implementation in VSE :

Fig.7. Phase frequency detector schematic level implementation

Fig.11 Final PLL layout in Cadence Virtuoso Layout Editor

Fig.8 Schematics of charge pump PLL

Fig.12 GDSII extracted for the complete design

GDSII for the complete design is taken so that it can be
sent for fabrication. This is the format which is accepted by the
fabrication companies for fabrication of the complete design.

IV. RESULTS

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The complete system is modelled in MATLAB and REFERENCES

then block level design is carried out in the HSpice and then the [1] S. M. Metev and V. P. Veiko, Laser Assisted
complete design is implemented in the VSE and all the results are Microtechnology, 2nd ed., R Ronald E. Best, “Phase-Locked
validated with respect to the design specification. Loops” , McGraw-Hill Professional, ISBN: 007-149-3751,
2007
[2] Ronald E Best, “Phase-Locked Loops - Design Simulation and
Applications”, Mc-Graw Hill, 5e, ISBN: 0071412018, 2003
[3] H. Sjonald, “Improved Switched Tuning of Differential CMOS
VCO’s”, IEEE Journals of Circuits and Systems-II Analog and
Digital Signal Processing, vol. 49, No. 5, pp.352-355, May
2002
[4] Behzad Razavi, “Design of analog CMOS Integrated
circuits”, Tata Graw-hill Professional, ISBN:0-07-238032-2,
2002
[5] Phillip E. Allen and Douglas R. Holberg, “CMOS Analog
Circuit Design”, OXFORD University Press, ISBN:978-0-19-
568626-5, 2004
[6] Behzad Razavi, “RF Microelctronics”, prentice-hall, ISBN:0-
Fig.14 Post layout simulation of PLL in Spectre 13- 887571-5, 1998
[7] David A.Johns and Ken Martin, “Analog Integrated Circiut
The final results of the complete PLL is tabulated Design”,Tata Graw-hill Professional, ISBN:978-81-265-1778-
7, 2008
in Table 1 , which confirms the 50% reduction in Jitter, [8] Someshwar C. Gupta, “Phase-Locked Loops”, Proceedings
40% reduction in Power and 30% area of the final design of IEEE, vol. 63, No. 2, pp.291-306, February 1975
is reduced. Making the design better compared to the [9] W. P. Robins, “Phase Noise in signal sources”, Institution of
reference design. Engineering and Technology, ISBN: 0-906-04876-1, 1982
[10] W. P. Robins, “Phase Noise in signal sources”, Institution of
Engineering and Technology, ISBN: 0-906-04876-1, 1982
OUTCOMES SPECIFICATION OBTAINED ACHIEVEMENTS [11] Behzad Razavi, “Study of Phase Noise in CMOS
Ref Signal 100 MHz 100 MHz Oscillators”, IEEE Journals of Solid-State Circuits, vol. 31,
VCOFrequency 2.4 GHz 2.6 GHz No. 3, pp.331-343, March 1996
[12] Christopher Lam and Behzad Razavi “A 2.6GHz Frequency
Charge Pump 100 µA 100 µA Synthesizer in 0.4um CMOS Technology”, IEEE Journals of
Current Solid-State Circuits, vol. 31, No. 3, pp.331-343, May 2000

Jitter 30 ps 20 ps 33% better

Technology 0.18 µm 0.18 µm
Operating 1.8 V 1.8 V
Voltage
Power 10 mW 6.99 mW 30% better
Dissipation
TABLE 1. Final Results of PLL

CONCLUSIONS
In this project, the software reference model of the
complete PLL is modelled in MATLAB™ Simulink® and
verified The latch-based PFD is implemented which increases the
performance of the lock time by removing the dead-zone.The
hardware reference model of the individual blocks of PLL is
designed and verified in Synopsys™ HSpice®.The modified
Charge pump reduces the power of the design, as it consists of
only four transistors and in-turn reducing the area consumed by
the design. The introduction of the Level Shifter at the control
voltage input of the VCO assists in tuning the VCO for
generating different frequencies from the same VCO.The VCO
designed to generate a range of frequencies ranging from 2.4GHz
to 2.65GHz which is controlled by control voltage.Divide by 24
is implemented to match the VCO frequency output with the
reference input signal.The complete design is implemented in
Cadence™ Virtuoso® tools and the GDSII is extracted for the
design the complete area of the design is 0.0075μm. The jitter of
the complete design is calculated to be 20ps which is 33% less
than the reference design jitter of 30ps and power of the design is
6.99mW which is 30% less than the reference design power of
10mW

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