DEDAN KIMATHI UNIVERSITY OF TECHNOLOGY (b) How many data lines are there assuming same pins are

lines are there assuming same pins are used for data
ELEC & ELEC ENGINEERING DEPARTMENT
EEE, TIE & B.ED(EEE) III
EEE 3206 DIGITAL ELECTRONICS II SOLUTION TO CAT I
1). Given that in circuit in Figure 1; VREF = −1.175V , RC2 = 267Ω, RC3 =
300Ω, RE = 1.18kΩ, RE4 = 1.5kΩ, RE5 = 1.5kΩ,
in and out?
Since each word has a length of 8 bits, 8 data lines are required.
(c) ignoring the power pins, draw the memory package.
Since this device is a random access memory with rad and write
capabilities, the memory package is configured as below

A0
RC3 A1
RC2
A B Q5
VC3
VC2 F1
Q4

Q1 Q2 Q3 VREF F2 A15
D0
VE D1

RE RE4 RE5
R/W
VEE = -5.2V
D7 CS

Figure 1: A 2-input 2-output gate

Figure 2: 65, 536 × 8 memory

(a) Identify the logic family (d) Using the same packages, describe how you can achieve a capacity of
From the circuit, the logic family is Transistor-Transistor 147,456 words.
Logic(TTL). To achieve 147456 = 216 + 216 + 214 , three packages are required with
(b) Draw the truth table of outputs F1 and F2 with A and B as inputs. the third one have pins A14 and A15 not connected.
(e) Draw the timing diagram of the Read operation
A B F1 F2 READ Cycle
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
(c) Identify the logics represented.
From the truth table, the logics represented are OR and NOR gates
for F1 and F2 respectively.

2). The semiconductor random access memory of a computer has 65,536

words, each of 8-bits. It can perform two basic operations of Read and
Write.
Figure 3: SRAM READ cycle
(a) How many address lines are there?
To address 65536 = 216 , 16 address lines are needed.

1
 a). t0 : Address inputs change to a new address from which data is iii). tAS : Address set-up time - time taken by the RAM’s address
to be read. This is the beginning of a READ cycle. decoders to respond to the new address.
b). t1 : Chip Select input activated iv). t2 : Data to be written into the addressed memory location is
c). t2 : Data outputs change from High Impedance State to valid applied. The data has to be held stable for at least a time tDS ,
data outputs. data set-up time, before R/W and CS are returned HIGH. The
d). t3 : Chip Select input is de-activated. data also has to be held stable for at least a time tDH , data
hold time, after R/W and CS have returned HIGH. Similarly,
e). t4 : Data outputs change from valid data outputs to the High
the address inputs have to be maintained for a time tAH , ad-
Impedance State in response to the de-activation of the Chip
dress hold time after R/W and CS have returned HIGH. If
Select signal. Any device that needs to read data from the
any of these set-up or hold-time requirements are not met, the
memory device should do so between t2 and t4 .
WRITE operation will not occur reliably.
f). t5 : End of READ cycle. Address inputs change to a different
v). tW C : WRITE cycle time.
address for a another READ or WRITE cycle.
g). tCO : Minimum time taken for memory outputs to go from
High Impedance state to valid data outputs after Chip Select
input has been activated.
h). tOD : Minimum time taken for memory outputs to go from
valid data outputs to Impedance state after Chip Select input
has been de-activated.
i). tOD : READ cycle time.
(f) Draw the timing diagram of the Write optation.
WRITE cycle

Figure 4: SRAM WRITE cycle

i). t0 : Address inputs change to a new address to which data is

to be written. This is the beginning of a WRITE cycle.
ii). t1 : Chip Select input is activated and at the same time, the
R/W input is set LOW for a WRITE operation.