ANANTHA LAKSHMI

INSTITUTE OF TECHNOLOGY AND SCIENCES

(Approved by AICTE, New Delhi &Affiliated to JNTU,Ananthapuramu.)

TITLE
Design Of Efficient power gated compressor using ECRL
PROJECTASSOCIATE
B RAJKUMAR - 162G1A04C4
CHAPPIDI SREE VIDYA - 162G1A04C9
CHITTRA VIJAYKUMAR - 162G1A04D1
KURUBA RAVINDRA - 172G5A0407
PODICHERUVU AKHILA - 152G5A0434

UNDER THE GUIDANCE OF

Dr. Y. L. AJAY KUMAR M.Tech., Ph.D.,MIAENG (Associate Professor)
 ABSTRACT

Advent of new age technologies like augmented reality has made techniques like digital signal
processing DSP, image and speech processing one of the most frequently used and important
techniques. Multipliers are the fundamental components of these techniques which depend on
extensive multiplications and numerical manipulations. Compressors are a crucial and important unit
of multipliers that largely influence the speed and power consumption of multipliers. This paper
proposes a low power ECRL based compressors by employing power gating.
 Problem Definition

➢ CMOS logic family, one of the most popular logic families for integrated circuits, but suffers from

large power consumption at high frequencies.

➢ In order to address the disadvantages of CMOS technology the proposed technology which is called

ECRL Technology. Through ECRL Technology, we can overcome the drawbacks of CMOS

Technology.
 OBJECTIVE

➢ By using Adiabatic logic ECRL, This design reduces the power and delay when compared to

existing CMOS.

➢ Performance parameters like power and delay are analyzed.

 EXISTING APPROACH

➢ CMOS circuits have been an integral part of the modern day VLSI devices and one of the most

popular logic families for integrated circuits, but suffers from large power consumption at high

frequencies.

➢ Day by day popularly the demands and necessity for high speed and low power electronics

system are increasing.

 DRAWBACKS OF EXISTING APPROACH

➢ CMOS logic suffers from primarily three power losses, static or leakage, direct path and

dynamic or switching losses, latter dominating the overall power consumption in CMOS

devices.

➢ The path of multipliers processing is the most time consuming thereby requiring more power

to compute and evaluate data.

 IMPLEMENTED APPROACH

➢ Efficient Charge Recovery Logic (ECRL) has been employed in this work for its significant

improvement in power consumption and relative simplicity.

➢ In ECRL we are employing power gating techniques.

 METHODOLOGY

➢ This paper proposes a low power ECRL based compressors by employing power gating. Power gating

methodologies have been evaluated and compared, at varying load capacitances, supply voltage and frequency

of the power clock signal, using CMOS technology parameters.

➢ The small overhead observed in active state power dissipations is well compensated for by the significant

power savings in idle states.

 FOOTER

Footer have been used with ECRL based 4:2 compressors to

further minimize its power consumption in order to achieve low
power compressors. which would result in low power
multipliers, enabling increased amounts mathematical
manipulations, while dissipating less energy. which is required
for modern day technology.

Figure : Footer gating

 4:2 COMPRESSOR
➢Compressor is a crucial unit used in optimizing partial product addition aiding the complex design of
multiplier circuits.

➢ Compressors are needful in minimizing data i.e. compressing data.

➢ A 4:2 Compressor has 5 inputs, including4 input bits and one carry in or Cin and has 3 outputs i.e. sum,
carry out or Cout and final carry or Carry.

Figure : 4:2 compressor

 RESULT

ECRL Based 4:2 Compressor simulation

 COMPARISION

EXISTING METHOD PROPOSED METHOD

1. Area consumed is 88 transistors. 1. Area consumed is 122 transistors.

2. Power Consumption is 16.5 Mw 2. Power Consumption is 12.8 Mw

3. Delay is 19ns. 3. Delay is 19ns.

 APPLICATIONS

➢ Digital signal processing.

➢ Image processing.

➢ Filtering and Speech processing.

 CONCLUSION

➢ The gated counterparts result in better power analysis especially at higher frequencies and

load capacitance.

➢ A small overhead power dissipation is observed in the gated circuits which is compensated

for by the significant reduction in consumption power in idle states.

 REFERENCES

➢ P. Teichmann, “Adiabatic Logic” in Future Trend and System Level Perspective, Springer Series
in Advance Microelectronics, 2012.

➢ J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuits”, A Design

Perspective, Second Edition, 2003.

➢ P. Teichmann, J. Fischer and S. Henzler, “Power clock Gating in Adiabatic Logic Circuits”, in Proc.
PATMOS, pp. 638– 646, 2005.

➢ K. K. Sahu and M. N. Islam, “Adiabatic Logic Design for Low Power VLSI Applications”, 2015.