Shiv Nadar Institution of Eminence, Deemed to be University

Department of Electrical Document Number: Version: 1.2

Engineering SNU/MAN/EHS/EL/01 Effective Date:
02/01/2023
Title: Communication Engineering Lab Manuals Pages 7

LAB: 06
Shift Keying Modulation & Demodulation
OBJECTIVES:
1. Study of Line coding and Data Formats.
2. Study of Amplitude Shift Keying Modulation and Demodulation (ASK).
3. Study of Frequency Shift Keying Modulation and Demodulation (FSK).
4. Study of Phase Shift Keying Modulation and Demodulation (PSK).

MATERIALS / COMPONENTS & EQUIPMENT: DSO, Training Kit, and connecting patch chords.

THEORETICAL BACKGROUND:
Amplitude Shift Keying: Amplitude-shift keying (ASK) is a form of amplitude modulation that represents
digital data as variations in the amplitude of a carrier wave. In an ASK system, a symbol, representing one or
more bits, is sent by transmitting a fixed-amplitude carrier wave at a fixed frequency for a specific time
duration.
Logic 1 – Carrier signal is present
Logic 0 – Carrier signal is absent

Frequency Shift Keying: In Frequency Shift Keying, the frequency of sinusoidal carrier is shifted between
two discrete values. One of these frequencies represents a binary 1 and other value represents binary 0. There
is no change in amplitude of carrier signal. Frequency shift keying (FSK) is the most common form of digital
modulation in the high-frequency radio spectrum, and has important applications in telephone circuits. Binary
FSK (usually referred to simply as FSK) is a modulation scheme typically used to send digital information
between digital equipment such as tele-printers and computers.

Phase-shift keying: Phase-shift keying (PSK) is a digital modulation process which conveys data by changing
(modulating) the phase of a constant frequency reference signal (the carrier wave). The modulation is
accomplished by varying the sine and cosine inputs at a precise time. For example, when encoding bits, the
phase shift could be 0 degree for encoding a "0," and 180 degrees for encoding a "1," or the phase shift could
be –90 degrees for "0" and +90 degrees for a "1," thus making the representations for "0" and "1" a total of
180 degrees apart.

Line Coding:
Line coding is the process of converting digital data to digital signals. By this technique we convert a sequence
of bits to a digital signal. At the sender side digital data are encoded into a digital signal and at the receiver
side the digital data are recreated by decoding the digital signal.

Different Data Formatting techniques:

(a) Non return to zero- level (NRZ-L):

Representation: +5V for data bit 1 and 0V for data bit 0.
Bandwidth: Low.
DC Level: High DC component.

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Timing Information: No timing information (For long stream of 1s and 0s)
In this scheme, all the signal levels are either above or below the axis.

Fig. 1 NRZ data format

(b) Non return to zero- level (NRZ-M):
Representation: Level transition for bit 1 and unchanged level for bit 0.
Bandwidth: Low bandwidth.
DC Level: High DC component.
Timing Information: No timing information (For long stream of 0s)

Fig. 2 NRZ-M data format

(c) Return to zero (RZ):
Representation: 0V for bit 0 and for bit 1, for half bit duration +5V and the rest of the bit duration is
represented as 0V.
Bandwidth: Twice as that required for the NRZ.
DC Level: High DC component.
Timing Information: No timing information (For long stream of 0s)

Fig. 3 RZ data format

(d) Biphase (Manchester):
Representation: For bit 1, +5V for first half bit time and 0V during the second half and for bit 0, 0V for first
half bit time and +5V during the second half.
Bandwidth: Twice as that required for the NRZ.
DC Level: No DC component.
Timing Information: Good clock recovery

Fig. 4 Biphase/ Manchester data format

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(e) Biphase (Mark):
Representation: For any bit either 1 or 0, first half bit duration +5V or 0V and invert of first half during next
half bit duration. Bit 0 Bit Pattern remains the same. Bit 1 Phase Reversal.
Bandwidth: Twice as that required for the NRZ.
DC Level: No DC component.
Timing Information: Good clock recovery.

Fig. 5 Biphase (Mark) data format

(f) Return to Bias (RB):
Representation: During the first half a period, positive level for bit 1 and a negative level for bit 0 and during
the second half bit time, both returns to the bias level.
Bandwidth: Twice as that required for the NRZ.
DC Level: The DC component depends on the string of 1’s and 0’s.
Timing Information: Good clock recovery (Self clocking system).

Fig. 6 Return to Bias data format

(g) Alternate Mark Inversion (AMI):
Representation: Like RB encoding, the AMI always returns to the bias level during second half of the bit time
interval and during the first half the transmitted level can be a positive, a negative or bias level, as for a bit 0
bias level and for a bit 1 either a positive level or negative level, the level being chose opposite to what it was
used to represent the previous bit 1.
Bandwidth: Twice as that required for the NRZ.
DC Level: No DC component.
Timing Information: No timing information (For long sequence of 0’s).

Fig. 7 Alternate Mark Inversion data format

Exercise:

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1. Study of Data Formats:
PROCEDURE:
1) Connect CLOCK O/P from clock source to CLOCK I/P of Data source.
2) Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘Clock In’ and observe the waveforms. The output at ‘Data
In’ is repeating sequence of bits generated by Parallel to serial Converter.
3) Observe and verify all data formatting techniques. Save your graphs.

2. Study of ASK

Fig. 8 Connection Diagram/Block Diagram of ASK

PROCEDURE:
1) Make the connection as shown in figure. Note carrier frequency.
2) Observe Data I/P and ASK O/P. Examine ASK signal corresponding to “ON” and “OFF” time period of data.
3) Now, detect the ASK signal using the ASK demodulator and observe the given graphs.

OBSERVATION:
TABLE ASK
Sr. No. Time period of Data Output Voltage of ASK Detected Data
TON TOFF V0 at TON V0 at TOFF TON TOFF
1
2
3

Fig.9 Expected Waveform of ASK generation and detection

Graphs to be observed:
1: Data I/P Vs ASK modulator o/p

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2: ASK Vs Diode Detector O/P
3: Diode detector O/P Vs LPF O/P
4: Data I/P Vs Data O/P

3. Study of PSK

Fig. 10 Connection Diagram/Block Diagram of PSK

For PSK signal demodulation the square loop detector circuit is used. The signal squarer multiplies the input
signal by itself. The output of this block is a signal of having twice the frequency to that of the input carrier
frequency. As the frequency of the output doubled, the 0° & 180° phase changes are reflecting as 0° & 360°
phase changes. Since phase change of 360° is same as 0° phase change, it can be said that the signal squarer
simply removes the phase transitions from the original PSK waveform. The PLL block locks to the frequency
of the signal square output & produces a clean square wave output of same frequency. To derive the square
wave of same frequency as the incoming PSK signal, the PLL output is divided by two.
phase adjust circuit allows the phase of the digital signal to be adjusted with respect to the input PSK signal.
When the output is high the switch closes & the original PSK signal is switched through the detector. When
the output of phases adjust block is low, the switch opens & the output of detector output falls to 0 Volts. The
demodulator output contains positive half cycles when the PSK input has one phase & only negative half cycles
when the PSK input has another phase.

PROCEDURE:
1. Make the connection as shown in figure. Note carrier frequency.
2. Observe Data I/P and Bipolar data using DSO. Examine unipolar and bipolar data.
3. Observe the Data I/P together with PSK O/P and examine the phase difference corresponding to the
transitions of pulses from 0 to 1 and 1 to 0.
4. Observe O/P of the signal squarer block and examine & record its frequency.
5. Observe O/P of the PLL block and examine & record its frequency.
6. Observe O/P of divide by 2 counter block and examine and record its frequency.
7. Observe the O/P of phase adjust block having positive and negative half cycles.

OBSERVATION:
TABLE PSK
Time period of Data Freq. of squarer Freq. of divide by 2 counter Detected Data
Sr. No. TON TOFF fsq fcounter TON TOFF

1
2
3
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Fig.11 Expected Waveform of PSK generation and detection

Graphs to be observed:
1: Data I/P Vs Bipolar Data
2: Data I/P Vs PSK
3: PLL O/P Vs Divide by 2 O/P
4: PSK Demodulator O/P Vs LPF O/P
5: Data I/P Vs Data O/P

4. Study of FSK

Fig. 12 Connection Diagram/Block Diagram of FSK

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PROCEDURE:
1. Make the connection as shown in figure. Note higher & lower carrier frequencies.
2. Observe Data I/P and Inverted data using DSO.
3. Observe the Data I/P together with FSK O/P and measure fhigher & fLower frequencies corresponding to TON
and TOFF time period of Data.
4. Now, detect the FSK using the FSK demodulator and observe the given graphs.

OBSERVATION:
TABLE FSK
Time period of Data FSK frequency Detected Data
Sr. No. TON TOFF fhigher at TON fLower at TOFF TON TOFF

1
2
3

Fig.13 Expected Waveform of FSK generation and detection

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Graphs to be observed:
1) Data I/P Vs Inverted Data
2) ASK 1 Vs ASK 2
3) Data I/P Vs FSK
4) PLL O/P Vs FSK
5) LPF O/P Vs Comparator O/P
6) Comparator O/P Vs Data I/P

Results:

Conclusion:

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