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ST2 2017
ST2 2017
ST2 2017
Rekenaaringenieurswese Engineering
Semestertoets 2 : Invul en e-Merk Semester Test 2: Fill-in and e-Grading
Afdeling A: Studie-eenhede 5 - 7 Part A: Study units 5 - 7
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Analoog Elektronika ENE310 Analogue Electronics ENE310
9 Mei 2017 9 May 2017
Punte / Marks
Totaal Afd. A:
V/Q1 V/Q2 V/Q3 V/Q4
/11 /10 /12 /0 Total Part A: /33
Totaal ELO 1:
Total ELO 1: /10
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
Veronderstel die opvolgende Bode-plot is van [11] Suppose the following Bode plot is of the loop
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die luswins, L, vir 'n terugvoerversterker. Die gain, L, for a feedback amplifier. The solid
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soliede lyne gee die oorspronklike oordrag, lines give the original transfer, while the dotted
terwyl die stippellyne die oordrag is nadat lines are for the transfer after stability
stabiliteitskompensasie uitgevoer is. compensation had been performed.
Vir die oorspronklike oordrag (soliede lyne): 1.1 For the original transfer (solid lines):
a. Indien die wins van die opelus vorentoe- (4) a. If the gain of the open-loop feedforward
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voer-versterker 70 dB is, bepaal die amplifier is 70 dB, determine the feedback
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terugvoernetwerkwins β grafies. Toon β network gain, β, graphically. Indicate β
aan met 'n # op u Bode-plot. (ELO1) with a # on your Bode plot. (ELO1)
b. Skat die fase-marge, PM, grafies, en merk b. Graphically estimate the phase margin,
die tersaaklike frekwensie met 'n X op u PM, and mark the pertinent frequency with
Bode-plot. an X on your Bode plot.
c. Skat die wins-marge, GM, grafies en c. Graphically estimate the gain margin,
merk die tersaaklike frekwensie met 'n O GM, and mark the pertinent frequency with
op u Bode-plot. an O on your Bode plot.
d. Is die versterker stabiel? Gebruik “J” vir d. Is the amplifier stable? Use “Y” for Yes,
Ja, “N” vir Nee. “N” for No.
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 2
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
Vir die kompenseerde oordrag (stippellyne): 1.2 For the compensated transfer (dotted lines):
a. Bepaal die dominante poolfrekwensie, fp’, (5) a. Graphically determine the dominant pole
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van die kompenseerde versterker grafies. frequency, fp’, of the compensated
Merk fp’ met ‘n . amplifier. Mark fp’ with an .
b. Bepaal die transisiefrekwensie, ft, van die b. Graphically determine the transition
kompenseerde versterker grafies, en merk frequency, ft, of the compensated amplifier,
ft met ‘n ^. and mark ft with a ^.
c. Wat is die fase-marge, PM’, van die c. What is the phase margin, PM’, of the
kompenseerde versterker? Dui PM’ aan compensated amplifier? Indicate PM’
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 3
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
met ‘n *. with a *.
d. Indien ‘n geslote-lus wins van Avf = 20 dB d. If a closed-loop gain of Avf = 20 dB is
vereis word vir die kompenseerde demanded for the compensated amplifier,
versterker, bepaal grafies wat die geslote- determine graphically what the closed-
lus bandwydte sal wees. Merk die loop bandwidth will be. Mark the closed-
geslote-lus bandwydte, BW, met ‘n ∆ op loop bandwidth, BW, with a ∆ on your
u Bode-diagram.
Bode diagram.
e. Gestel die geslote-lus versterker (d) lewer e. Suppose the closed-loop amplifier of (d)
‘n piekuitsetamplitude van vLp = 5 V,
delivers a peak output voltage amplitude of
spesifiseer die benodigde volgtempo, SR,
van die versterker. vLp = 5 V, specify the required slew rate,
SR, for the amplifier.
Vir die kompenseerde oordrag (stippellyne): 1.3 For the compensated transfer (dotted lines):
Aanvaar die dominante poolfrekwensie, fp’, (2) Assume the dominant pole frequency, fp’, of the
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van die kompenseerde versterker word compensated amplifier is associated with the
geassosieer met die inset van die versterker. input of the amplifier. For an input resistance
Vir ‘n insetweerstand Ri = 2.2 k, bepaal die of 2.2 k, determine the input capacitance, Ci,
insetkapasitansie, Ci wat fp’ sal lewer. that would produce fp’.
VRAAG 2 QUESTION 2
10
Lineêre OV-bane Linear OpAmp circuits
Beskou die volgende omsetterbrugversterker: [10] Consider the following transducer bridge
S-E/U 6 amplifier:
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 4
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
For δ≪1:
𝑅2⁄
𝑣𝑂 ≈ 𝑅 ∙ 𝑉𝑅𝐸𝐹 𝛿
𝑅 𝑅
1 + 1⁄𝑅 + 1⁄𝑅
2
Franco
VREF = 3 V ; R = 200 Ω ; R1 = ? Ω ; R2 = 33 kΩ
RTD: R0 = 200 Ω @ 25 °C ; αR = 500 mΩ / °C ; Pdp = 10 mW
Laat die omsetter in die brug ‘n platinum Let the transducer in the bridge be a platinum
weerstand-temperatuur-detektor (WTD) wees: resistance temperature detector (RTD):
verwysingswaarde R0 = 200 Ω by 25 C reference value at 25 C of R0 = 250 Ω
αR = 500 mΩ/C temperatuurkoëffisiënt. temperature coefficient αR = 500 mΩ/C
Beperk self-verhitting deur te verseker dat To limit self-heating, the power
die drywingsdissipasie in die WTD nie dissipation in the RTD may not exceed
PRTD = 10 mW oorskry nie. PRTD = 10 mW.
a. Ontwerp vir die onbekende parameter R1 in 2.1 a. Design for the unknown parameter R1 in
die stroombaan. Gee die antwoord as die (5) the circuit. Give the answer as the closest
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naaste 1 % standaard weerstandwaarde. 1 % standard resistance value.
b. Gee die waarde van drywingsdissipasie in b. Give the value of power dissipation in the
die WTD van u ontwerp. RTD for your design.
c. Gestel daar is 5% toleransie op al die brug- c. Suppose there is a 5% tolerance on all the
weerstandwaardes. Spesifiseer die bridge resistance values. Specify the
maksimum drywin wat die die VREF-bron maximum power that the VREF source must
moet kan lewer. (ELO1) be able to deliver. (ELO1)
Bereken die sensitiwiteit, S, rondom 25 °C (dus 2.2 Calculate the sensitivity, S, around 25 °C (i.e.
met δ << 1) vir u ontwerp. (2) with δ << 1) for your design.
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Evalueer tot welke mate die versterkertrap die 2.3 Evaluate to what extent the amplifier stage
brug belas, en lewer kommentaar oor die (3) loads the bridge, and comment on the
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praktiese toepaslikheid van die stroombaan. U practical applicability of the circuit. You may
mag aanvaar dat die OV ideal is. (ELO1) assume an ideal opamp. (ELO1)
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 5
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
VRAAG 3 QUESTION 3
12
Nie-lineêre OV-bane Non-linear OpAmp circuits
Beskou die volgende Schmitt-sneller: [6] Consider the following Schmitt trigger:
S-E/U 6
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 6
Departement Elektriese, Elektroniese en Rekenaaringenieurswese Department of Electrical, Electronic and Computer Engineering
Analoog Elektronika ENE310 – Hereksamen Deel A 2016 Analogue Electronics ENE310 – Supplementary Part A 2016
Kopiereg voorbehou Copyright reserved
Beskou die volgende presisie vol- [6] Consider the following precision full-wave
golfgelykrigter (FWR): S-E/U 6,7 rectifier(FWR):
ENE310 Semester Test 2 - Part A / Semestertoets 2 - Deel A © 2017, UP EECE, Trudi Joubert 7
Departement Elektriese, Elektroniese Department of Electrical, Electronic
en Rekenaaringenieurswese and Computer Engineering
Toetsinligting:
Test information:
Maksimum punte: 20 Volpunte: 20
Maximum marks: Full marks:
Duur van vraestel: 90 minute Oopboek / toeboek: Oop
Duration of paper: 90 minutes Open / closed book: Open
Totale aantal bladsye (hierdie blad ingesluit): Punt:
Total number of pages (including this page): 3 Mark:
BELANGRIK- IMPORTANT
1. Die toets & eksaminerings regulasies van die Universiteit van Pretoria is van toepassing.
The test & examination regulations of the University of Pretoria apply.
2. Vrae moet in onuitveebare ink geskryf word. Antwoorde in potlood sal nie gemerk word nie!
Questions must be answered in indelible ink. Answers in pencil will not be marked!
3. Antwoord al die vrae en skryf die antwoorde vir gedeelte A en B in die apparte voorsiende antwoord boeke.
Answer all the questions and write the answers for part A and B in the separate supplied answer books.
4. Dui alle bewerkings waar van toepassing aan. Geen punte sal gegee word vir korrekte antwoorde wat nie gestaaf word met bewerkings/denkwyse nie.
Show all calculations where applicable. No marks will be given for correct answers without calculations/reasoning to support them.
5. Gebruik duidelike en geregverdigde ingenieursbenaderings (en/of aannames) waar van toepassing. Alle aannames moet gestaaf word.
Use clearly justified & educated engineering approximations (and/or stated assumptions) where/as appropriate. All assumptions must be justified.
6. Gee duidelik die definisie vir die berekening van die finale resultaat indien enige verskil in notasie (van die voorgeskrewe handboek) gebruik word
(evaluasie sal daarvolgens geskied).
Where there’s a notation difference (to the prescribed textbook), specify your definition in computing the final result (evaluation will be done in
accordance).
7. Die elektroniese evaluasie regulasies van die Departement Elektries, Elektronies en Rekenaaringenieurswese is van toepassing.
The electronic evaluation regulations of the Department of Electrical, Electronic and Computer Engineering apply.
V/Q B1 / 10
V/Q B2 / 10
Afdeling B / Part B
Beskou die laaglaatfilter stroombaandiagram Consider the first order low pass filter
met verstelbare weerstande hieronder. Ontwerp circuit diagram with potentiometers given
‘n filter met ‘n konstante afsnyfrekwensie van 6 below. Design a filter that will exhibit a
kHz en ‘n verstelbare spanningswins tussen 10 fixed cut off frequency of 6 kHz and an
- 30 dB. Slegs 10 kΩ verstelbare weerstande is adjustable voltage gain between 10 - 30 dB.
beskikbaar. (Wenk: Jy hoef nie van beide Only 10 kΩ potentiometers are available.
verstelbare weerstande gebruik te maak nie. (Hint: You do not have to use both
Indien jy een onaktief wil maak, kan beide die potentiometers. If you want to neglect the
minimum en maksimum waardes as 0 Ω gekies effect of one, choose both the minimum and
word.) maximum values as 0 Ω.)
ENE310 Semester Test 2 - Part B / Semestertoets 2 Deel B © 2017, UP EECE, Johan Schoeman 2
Vraag B2 [10] Question B2
Tweede orde filter ontwerp {SU9.2-9.6} / ELO1 Second order filter design {SU9.2-9.6} / ELO1
Ontwerp ‘n tweede orde bandlaatfilter wat ‘n Design a second order bandpass filter that
totale bandwydte van 4 kHz gesentreerd rond- will pass a total bandwidth of 4 kHz centred
om 40 kHz sal deurlaat vir ‘n IR versendtoe- around 40 kHz for an IR transmitter
passing deur van ‘n veelvuldige terugvoer application by using a multiple-feedback
topologie gebruik te maak. ‘n Maksimum topology. A maximum voltage gain
spanningswinsgrootte van 40 dB word toegelaat magnitude of 40 dB is allowed to prevent
om te verseker dat die uitset nie versadig nie. output saturation. Determine the required
Bepaal die vereiste kwaliteits-faktor van die quality factor of the filter section and the
filtergedeelte en die komponent-waardes om die component values to realise this design.
ontwerp te realiseer.
ENE310 Semester Test 2 - Part B / Semestertoets 2 Deel B © 2017, UP EECE, Johan Schoeman 3