Design and Verification of RV32I RISC-V

Processor with 2-way Associative Cache

V R Athira
G Nishanthi Dr. V Arun
Anna University Regional Campus
Anna University Regional Campus Anna University Regional Campus
Anna University
Anna University Anna University
Madurai,India
Madurai,India Madurai,India
nairaathira843@gmail.com
nishak27518@gmail.com nairaathira843@gmail.com

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 Abstract—RISC-V is an open-source Instruction Set
Architecture (ISA) based on the principle of Reduced
Instruction Set Computer (RISC). In this paper, a 32-bit
pipelined RISC-V ISA is designed. The design is implemented
in such a way that at every clock cycle a new instruction is
started and each stage finishes its execution within one clock
cycle. The pipeline hazards like structural, data and control
hazards are removed. Furthermore, the Universal Verification
Methodology (UVM) is used to build the verification platform
to verify the synthesized RTL code, then by using functional
coverage it is verified that all the DUT features have been
verified and have measured the quality of verification. The
logic function of the processor is verified by implementing it in
the Xilinx Spartan 6 FPGA. The synthesized RTL code is
reliable and fully verified and the performance parameters are
also optimized.
Keywords—RISC-V, RV32I, Verilog, System Verilog, EDA
I. INTRODUCTION
Due to the use of CISC (Complex Instruction Set
Computing), the majority of CPU realizations, up to the
1980s, became increasingly complex. As CISC directives
were followed. Because pipeling is complicated to
implement and it takes multiple clock cycles to complete a
single instruction, which slows down speed and memory
access. The first computer using a Reduced Instruction Set
Computer (RISC) architecture was developed by IBM
researcher John Cocke and his colleagues in the early 1980s.
Subsequently, in May 2010, as a part of the Parallel
Computing Laboratory (Par Lab) at UC Berkeley, where
Prof. David Patterson served as Director, Prof. Krste
Asanovi and graduate students Yunsup Lee and Andrew
Waterman began developing the RISC-V instruction set. A
new instruction set architecture (ISA) called RISC-V was
created to aid in the study and development of computer
architecture[1]. The core concept of RISC V is that an
instruction is executed once every clock cycle, and that the
memory is constant in size, making it simple to decode the
instruction. The BASE and EXTENSION modules make up
the RISC V architecture. Any implanter can choose which
functions to include in a CPU design because to this. One
BASE module and zero or more EXTENSION modules are
provided for every RISC V implementation. The 32-bit basic
integer instruction set is referred to as RV32I. M stands for
multiplication and division, F for floating-point instructions,
D for double-point precision instructions, and A for atomic
instructions. These are the standard RISC-V extensions. In
addition, RV32G is a general-purpose 32-bit instruction set
that includes all instructions from the M, F, D, and A
extensions. There also exist the 64-bit and 128-bit variants of
these instruction sets. This paper is focused on RV32I base
module.
The 32-bit RISC V ISA processor in this study is created
using the Verilog programming language, primarily in five
pipelined stages: instruction fetching, decoding, execution,
memory access, and writing back. Every stage is built so that
a new instruction should begin every clock cycle and that
each stage's execution must be completed in one clock cycle.
To execute functional verification and gather coverage, a
reusable verification platform is created using UVM
Methodology.
II. RISC-V ISA DESIGN
A. Instruction formats
There are seven different forms of RISC-V instructions
formats. They are
U-type: It is utilised for instructions that make use of a rd
destination register and an immediate operand of 20 bits.
J-type: The jal instruction has an instantaneous value that
specifies the jump target address, and is encoded using the J-
type instruction format. It is comparable to the U-type, but
the immediate operand's bits are arranged differently.
R-type: The R-type instructions are used for operations
that cause the contents of source registers rs1 and rs2 to be
transferred to the destination register rd.
I-type: Instructions with a signed 12-bit immediate
operand with a range of [2048..2047], a rd register, and an
rs1 register are encoded using the I-type instruction format.
S-type: Instructions with a signed 12-bit immediate
operand with a range of [2048..2047], an rs1 register, and an
rs2 register are encoded using the S-type instruction format.
B-type: When a branch instruction needs an even
immediate value, the B-type instruction format is used to
specify the branch target address as an offset from the
address of the current instruction.
B. Pipeline Stage
The five steps that make up the pipelined implementation
of RISC V are: Instruction Fetch (IF), Instruction Decoding
(ID), Execution (EXE), Memory Access (MEM), and Write
Back (WB). The following stages are described:
Instruction Fetch (IF):   An instruction is retrieved from
memory at this point. The address of the instruction that
needs to be fetched from the instruction memory is stored in
the program ounter (PC), often known as the PC register.
The computer increases PC to PC + 4 after retrieving the
command. However, the destination address will be the
updated value of PC for the Branch/Jump instruction. Since
the new value is stored in NPC, PC is not updated at this
point for Branch/Jump instructions.
Instruction Decode (ID): Two tasks are completed at this
stage. Opcode is used to decode the instruction that was
fetched from the instruction memory. The register is fetched
after the indexes are provided as the register memory's
address. Register prefetching and instruction decoding are
carried out concurrently. The immediate data is sign
extended in a similar manner. The target address for the
Branch/Jump instruction is simultaneously determined
during register fetching.
Execute (EXE) : The computation process occurs during
this stage. This stage consists of two 2*1 MUX, an ALU
and a comparator. For Branch/Jump instruction, the MUX_1
produces NPC as output and feds to the ALU, otherwise it
gives, register A as output and feds to the ALU. For
immediate instruction, the MUX_2 selects imm (immediate
value) as the output and feds to the ALU, Otherwise it
produces register B as output. The MUX output is fed to the
ALU, the ALU computes and produces ALUOut.

Memory Access (MEM): At this point, any data that needs

to be accessed from memory is done so. This stage is used
by the LOAD, STORE, and Branch instructions. Depending
on how the branch condition turns out, the PC is updated.

Write Back (WB): During this stage, the result is written

back to the register file. The result may either come from the
ALU or the memory system (via. a LOAD).

C. Pipeline Hazards
There are several circumstances in the pipeline that prevent
the following instruction in the stream from running during
the specified clock cycles. This is regarded as a hazard [5].
There are three categories into which the hazards are
divided.

Structural Hazard: When two pipelined instructions

attempt to use the same hardware resource while being at
separate stages of the pipeline. They cannot access a single
copy of a hardware resource at once; one must wait.
Instruction memory and Data memory are the two memories
employed in this paper. This hazard is removed by using
Havard Architecture.
Data Hazard: Because of instruction dependence, this
hazard exists. Data hazards can be eliminated by forwarding
data or inserting a stall cycle, respectively.

Control Hazard: Control hazard arise due to branch

instruction. The branch is taken at Execute (EXE) stage, so
already entered instruction at Instruction Fetch (IF),
Instruction Decode (ID) are discarded. In this paper,
TAKEN_BRANCH register is set after the decision to take
a branch is known. It is required to disable instructions that
have already entered the pipeline from making any state
change.

FIG. 1 .5-STAGE PIPELINE SCHEMATIC RESULT

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