404 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO.

2, FEBRUARY 2022

A 25 Gb/s Wireline Receiver With Feedforward and

Feedback Equalizers at Analog Front-End
Jincheol Sim, Graduate Student Member, IEEE, Yeonho Lee , Member, IEEE,
Hyunsu Park, Graduate Student Member, IEEE, Yoonjae Choi , Graduate Student Member, IEEE,
Jonghyuck Choi , Graduate Student Member, IEEE, and Chulwoo Kim , Senior Member, IEEE

Abstract—An important issue in wireline receivers (RX) is min-

imizing the area and power consumption while overcoming the
channel attenuation with an equalizer. The greater the compen-
sation for channel loss at the analog front end (AFE) of the
RX, the lower the number of decision feedback equalizer (DFE)
taps. Power dissipation and area can be reduced by reducing
the number of DFE taps. This brief presents a technology that
compensates for the channel loss with the proposed AFE based
on a two-stage continuous-time linear equalizer (CTLE), low
and high bandwidth amplifiers, and a gain controller. It suffi-
ciently reduces the DC gain and increases the peak gain of the
AFE by using a feedforward equalizer (FFEQ) and feedback
equalizer (FBEQ). These equalizers result in an increase in the
difference between the peak and DC gains and the gain differ-
ence at the fundamental frequency (f0 ) and 2nd subharmonic Fig. 1. Top architecture of RX.
frequency (f1/2 ). The IC is fabricated in a 28 nm CMOS pro-
cess, and the proposed architecture yields a BER less than 10−12 additional area and power consumption, five or more taps are
at 25.8 dB channel attenuation. At 25 Gb/s, the area and power used in the DFE to overcome the channel attenuation [3]–[8].
efficiency of the proposed AFE are 1.19 pJ/bit and 0.01 mm2 , If the analog front-end (AFE) that includes the CTLE suf-
respectively. ficiently compensates for the inter-symbol interference (ISI),
the number of DFE taps can be reduced. However, in a single-
Index Terms—High-speed link, channel attenuation, receivers,
analog equalizer. stage CTLE, the difference between the peaking and DC gains
is limited. A boundary occurs where the DC gain of the single-
stage CTLE is lowered, because the DC gain of the CTLE
is inversely proportional to the degeneration resistance [1].
I. I NTRODUCTION Therefore, the gain difference at the fundamental frequency
HE DATA bandwidth required in high-speed interfaces
T has significantly increased over the years mainly due to
the increasing data traffic. The channel attenuation of these
(f0 ) and the 2nd subharmonic frequency (f1/2 ) also has limi-
tations. Instead of a single-stage CTLE, multiple stages of the
CTLE help improve the equalization ability. However, this is
interfaces is a bottleneck for data transmission. The chan- accompanied by an increase in both the area and the power
nel attenuation worsens with the increase in serial data rate. dissipation [12]–[14]. Therefore, a AFE of low cost and high
Therefore, equalization techniques are important to decrease performance that reduces the number of DFE taps is required.
the bit error rate (BER). A CTLE [1] and a DFE [2] are com- We propose a technique that increases the difference between
monly used in the receiver (RX). When the channel attenuation the peaking and DC gains and the gain difference at f0 and
increases at the target data rate, the number of CTLEs and/or f1/2 by using a feedforward equalizer (FFEQ) and a feedback
DFE taps should be increased. As the desired bandwidth equalizer (FBEQ) at the AFE.
increases, the limited capability of a single-stage CTLE results The rest of this brief is organized as follows. Section II
in a large proportion of equalization in the DFE. Even with explains the architecture of the RX with the proposed
AFE. Section III presents an analysis of the proposed AFE
Manuscript received June 7, 2021; accepted June 26, 2021. Date of with FFEQ and FBEQ. The measurement results are explained
publication July 1, 2021; date of current version January 31, 2022. This in Section IV. Finally, Section V concludes this brief.
work was supported by Future Interconnect Technology Cluster Program
of Samsung Electronics. This brief was recommended by Associate Editor
C. Condo. (Corresponding author: Chulwoo Kim.) II. S TRUCTURE OF THE R ECEIVER
Jincheol Sim, Yeonho Lee, Yoonjae Choi, Jonghyuck Choi, and
Chulwoo Kim are with the Department of Electrical Engineering, The top architecture of the proposed RX is shown in Fig. 1.
Korea University, Seoul 02841, South Korea (e-mail: ckim@korea.ac.kr). The RX consists of three blocks: the AFE, 1-tap DFE, and
Hyunsu Park is with the Department of Semiconductor System Engineering, clock I/O. The AFE consists of CTLEs, high bandwidth ampli-
Korea University, Seoul 02841, South Korea. fier (HBWA), low bandwidth amplifier (LBWA), and a gain
This article has supplementary material provided by the
authors and color versions of one or more figures available at
controller (GCONT )s. The CTLE in [1] is adopted, a modi-
https://doi.org/10.1109/TCSII.2021.3093913. fied Cherry-Hooper amplifier in [9] is used for the HBWA,
Digital Object Identifier 10.1109/TCSII.2021.3093913 and a common source differential amplifier is used for the
1549-7747 
c 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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SIM et al.: 25 Gb/s WIRELINE RECEIVER WITH FEEDFORWARD AND FEEDBACK EQUALIZERS AT ANALOG FRONT-END
Fig. 2. Schematics of (a) CTLE, (b) HBWA, and (c) LBWA.
Fig. 3. Block diagram of proposed FFEQ and FBEQ.
LBWA, as shown in Fig. 2. The bandwidths of the CTLE and
HBWA are greater than f0 , and that of the LBWA is lower
than f0 . Two phase clocks (CKODD , CKEVEN ) are required for
sampling at the slicer because the 1-tap DFE uses a half-rate
structure. To change the sampling phases of the CKODD and
CKEVEN , a digitally controlled delay line (DCDL) is used.
The resolution of the DCDL is 3 ps. The duty cycle correc-
tor (DCC) generates CKODD and CKEVEN with a clock duty
cycle of 50 % for input clocks with a duty cycle between 35 %
and 65 %.
The FFEQ and FBEQ have similar structures. In Fig. 3, the
outputs of the GCONT s are connected to the outputs of the
CTLEs. In the FFEQ and FBEQ, the inputs of LBWA1 and
LBWA2 are DIN and DOUT_AFE, respectively. Furthermore,
DIN and SUBFB are connected to the inputs of CTLE1 and
CTLE2 , respectively. A GCONT consists of two pairs of GCONT
X1 arrays, and GCONT X1 has two switches connected to both
ends of the inverter, and these switches are controlled by dig-
ital bits. The arrays of GCONT are grouped by 5-bit (or 4-bit)
binary weights. Therefore, the output amplitudes of the GCONT
are determined by NFF and NFB . In this prototype RX, the NFF
and NFB of the proposed AFE are manually controlled using
the internal I2 C.
III. A NALYSIS OF THE AFE
A. Frequency Response
In Fig. 2(a), the NMOS connected in parallel with the
degenerated resistor (RS ) determines the DC gain of the
CTLE depending on the gate voltage (VCTRL ). When the
VCTRL changes from VDD to VSS, the AFE with two-
stage CTLEs has a peaking and DC gain difference of
up to 6.5 dB at 12.5 GHz, as shown in Fig. 4. The DC
gain of the AFE is limited after the NMOS is turned off
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405
Fig. 4. Frequency response of AFE according to VCTRL (NFF = 0 and
NFB = 0).
Fig. 5. (a) Frequency response and (b) zero place according to NFF .
owing to the low VCTRL . Although DC and peaking gains
of the CTLE are limited, the FFEQ and FBEQ help gener-
ate high peaking and low DC gains. The transfer function
of the proposed AFE can be expressed by the following
equation:
DOUT_AFE (s) [HC1,2 (s) − NFF GCONT HL1 (s)]HH (s)
2
= (1)
DIN (s) 1+NFB GCONT HL2 (s)HC2 (s)HH (s)
where HC (s), HH (s), and HL (s) are the transfer functions of
the CTLE, HBWA, and LBWA, respectively. In (1), FFEQ and
FBEQ affect the numerator and denominator, respectively. The
frequency responses of the AFE, according to NFF and NFB ,
can be achieved by substituting the transfer function of each
circuit into (1). When the NFB and VCTRL are zero, and NFF
increases, the DC gain of the AFE decreases regardless of
the CTLE boundary, and the phase of the Bode plot exhibits
a peak, as shown in Fig. 5(a). As NFF increases, the gain of
the two-stage CTLEs is subtracted from NFF · GCONT · HL1 (s)|
and the 1st zero moves to a lower frequency. Fig. 5(b) shows
the locations of the zeros according to the NFF . The FFEQ
affects the 1st and right half plane (RHP) zeros. Fortunately,
RHP zero does not affect AFE at f0 because the RHP zero is
only located at a frequency above 1013 Hz, even if the NFF
increases.
Conversely, Fig. 6(a) shows the frequency response when
the NFF and VCTRL are zeros and the NFB increases. The
FBEQ changes the peaking and DC gains. The DC gain of
the AFE is decreased by loop gain, and the peaking gain is
increased due to complex poles. The change in the NFB affects
two complex quadratic equations, as shown in the following
equation:

DOUT_AFE (s)  K1 ω2n1 K2 ω2n2
 ≈
DIN (s) NFB (s2 +2ζ1 ωn1 +ω2n1 ) (s2 +2ζ2 ωn2 +ω2n2 )
(2)
406 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO. 2, FEBRUARY 2022
Fig. 6. (a) Frequency response and (b) damping factor according to NFB.
Fig. 7. Transient response of (a) ideal differential input, (b) RX input,
and (c) AFE outputs according to NFF and (d) NFB .
where K, ζ, and ωn are the DC gain, damping factor, and
natural frequency, respectively. As the proposed AFE is a high-
order system, it is difficult to calculate (2) manually. Therefore,
(2) can be solved using the modeling of the proposed AFE in
MATLAB. As NFB increases, ζ1 decreases, and ζ2 is con-
stantly greater than 0.9, as shown in Fig. 6(b). Because the
proposed AFE operates in a similar manner to the 2nd order
system, the peaking gain of the AFE can be changed by NFB .
However, when the NFB is larger than a certain bit, ζ1 has
a negative value. Therefore, the NFB was set to 4-bit to ensure
stability of the AFE. Thus, it is possible to control the differ-
ence between the peaking and DC gains by NFF and NFB . In
addition, because the slope of the proposed AFE is sharper,
the gain difference at f0 and f1/2 is further increased.
B. Transient Response
To simplify the transient response, it is shown in
Fig. 7(a) that a differential 1-unit interval (UI) pulse width
with 9 UI delay (VIN P and VIN N) is used. When the VIN
P and VIN N pass through −20 dB or more insertion loss,
DIN P and DIN N are transmitted to the RX, as shown in
Fig. 7(b). The DIN P and DIN N do not have a crossing
point in the data transition because pre and post cursors occur
due to the channel characteristic. Although the two-stages
CTLEs are used to compensate for the channel attenuation
(NFF = NFB = VCTRL = 0), the slicer makes an error because
there are no crossing points in the DOUT_AFE P and DOUT_AFE
N. Figs. 7(c) and 7(d) show the outputs of the AFE according
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Fig. 8. Comparison of AFE outputs (a) without and (a) with FFEQ and
FBEQ.
to the NFF and NFB change, respectively. The NFF of FFEQ
controls the DC gain of the AFE. As the NFF increases, the
voltage gap between the differential signals is reduced while
maintaining the signal shapes. It is possible to have crossing
points in the data transition. Furthermore, the NFB of FBEQ
changes the voltage difference between differential signals and
sharpens the signal in data transitions. The sharpness of the
signal can be confirmed from Fig. 8. As shown in Fig. 8(a),
the channel attenuation is compensated using the two-stage
CTLEs alone because FFEQ and FBEQ are turned off. Owing
to the CTLEs, the main cursor is increased, as compared to
DIN N; however, it does not generate zero crossing points,
which results in an error in the slicer. By contrast, when FFEQ
and FBEQ are used simultaneously, the first post cursor can
be lowered significantly while generating zero crossing points,
as shown in Fig. 8(b). Therefore, a better BER performance
of the proposed AFE, as compared to the two-stage CTLEs,
is expected, given that the combination of NFF and NFB can
compensate for the data transition against the channel ISI.
C. Total Harmonic Distortion and Signal to Noise Ratio
Linearity is an important factor in the AFE because the
distortion lowers the BER performance. The linearity of
the proposed AFE is verified with total harmonic distor-
tion (THD), which is calculated using a fast Fourier trans-
form (FFT). Fig. 9(a) shows the normalized THD of the
proposed AFE according to NFF and NFB . Normalized THD
is obtained by dividing THD by the THD amplitude when the
NFF and NFB are zero. Even though the performance of the
THD degrades when the NFF becomes larger than a certain
bit, the NFF and NFB constantly perform better in this case
than when NFF and NFB are zero. In addition, the signal-to-
noise ratio (SNR) can be calculated as shown in Fig. 9(b). The
normalized SNR is obtained by dividing SNR by the SNR
amplitude when the NFF and NFB are zeros. The larger the
NFB , the better is the SNR. As the NFF increases, the SNR
decreases because the signal amplitude becomes smaller and
smaller, as shown in Fig. 9(c). However, as shown in Fig. 9(d),
the noise power remains unchanged, regardless of NFF and
NFB . Therefore, it is verified that the contribution of noise
amplification due to FFEQ and FBEQ is not remarkable.
IV. M EASUREMENT R ESULTS
The proposed RX was fabricated in a 28 nm CMOS pro-
cess. The die micrographs in Fig. 10 show the proposed AFE
(RX1 ) and RX (RX2 ) with the AFE, clock I/O, and 1-tap
DFE. The areas of the RX1 and RX2 are 0.01 and 0.04 mm2 ,
respectively. The channel responses of Channels A and B are
SIM et al.: 25 Gb/s WIRELINE RECEIVER WITH FEEDFORWARD AND FEEDBACK EQUALIZERS AT ANALOG FRONT-END
Fig. 9. Normalized (a) THD, (b) SNR, (c) signal power, and (d) noise power
of the proposed AFE.
Fig. 10. Die micrographs of the proposed (a) AFE and (b) RX.
Fig. 11. (a) Measured channel attenuation of Channel A and B, and (b) eye
diagrams of input data and sampling clock.
−16.1 and −25.8 dB at 12.5 GHz, respectively, as shown in
Fig. 11(a). Channels A and B exclude package losses. The
data and sampling clock are received from a pattern gener-
ator. Fig. 11(b) shows the eye diagrams of the input data
and sampling clock. For the PRBS-31 and at 25 Gb/s, the
input data 0.73 UI in the open eye diagram. Furthermore, total
jitter (TJ) and random jitter (RJ) of 9.5 ps and 495 ps, respec-
tively, were also observed. The two-phase sampling clock has
a TJ of 4.5 ps and an RJ of 315 fs at 12.5 GHz.
Fig. 12 shows the eye diagrams for the AFE (RX1 ) out-
put according to NFF and NFB . All the eye diagrams were
accumulated more than 10,000 times. The input patterns are
PRBS-7 and 31, and an output driver, including an inductor,
is used to compensate for the parasitic capacitance from the
output pad to the oscilloscope. When NFF and NFB are turned
off, the eye-opening of the AFE is closed [Fig. 12(a)]. When
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407
Fig. 12. Eye diagrams when the FFEQ and FBEQ are (a) turned off
and (b) turned on for PRBS-7; PRBS-31 on (c) Channel A and (d) Channel B.
Fig. 13. Bathtub curves according to (a) Channel A and (b) Channel B.
NFF and NFB are turned on, an eye-opening of 110 mV and
a 0.48 UI are measured, as shown in Fig. 12(b). In addition,
even if the pattern changes from PRBS-7 to PRBS-31, it has
0.28 UI and 72 mV eye-opening [Fig. 12(c)]. When switching
from Channel A to B while maintaining the data pattern as
PRBS-31, The eye diagram in Fig. 12(d) was measured by
controlling NFF and NFB , which were manually changed from
6 to 8 and from 8 to 14, respectively. Therefore, the equal-
ization of the proposed AFE is 2.98 times better than that of
the two stage CTLEs at 25 Gb/s, because the proposed FFEQ
and FBEQ can control the peaking and DC gains.
Measurements of the proposed RX2 are performed using
Channel A and B. Fig. 13 shows the bathtub curves with
respect to the channels for PRBS-31. As shown in Fig. 13(a),
when the proposed AFE is adopted, the BER is better than
10−12 . However, the BER is over 10−2 when the 1-tap DFE
is used instead of the FFEQ and FBEQ. The two-stage CTLEs
and 1-tap DFE are not sufficient to compensate for Channel
A. To achieve a BER of 10−12 using the two stage CTLEs,
2-tap or more DFE taps would be required. Simultaneously
using 1-tap DFE, FFEQ, and FBEQ results in a wider 10−12
BER interval, ranging from 0.075 UI to 0.15 UI, as com-
pared to than when using the proposed AFE alone. Even in
the case of Channel B, similar curves are achieved, as shown
in Fig. 13(b). However, as Channel B involves greater atten-
uation than Channel A at 12.5 GHz, it is difficult to obtain
a BER of 10−12 or less using the proposed AFE alone. By
contrast, the simultaneous use of the proposed AFE and 1-tap
DFE can more than 0.07 UI with a BER of less than 10−12 .
Therefore, FFEQ and FBEQ reduce the equalization burden
408 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 69, NO. 2, FEBRUARY 2022
TABLE I
P ERFORMANCE C OMPARISON
Fig. 14. (a) Eye diagrams of the RX2 output and (b) power breakdown.
of the DFE by sufficiently compensating for the channel loss
in the AFE.
Fig. 14(a) shows the recovered data for PRBS-31 from the
differential NRZ. As the proposed RX uses a half-rate struc-
ture, the 25 Gb/s NRZ data are recovered to 12.5 Gb/s full-rate
data. The power breakdown of the proposed RX is presented
in Fig. 14(b). The total power consumption is 70.4 mW at
25 Gb/s. FFEQ and FBEQ account for approximately 10.9 %
of the total power dissipation; this is similar to the two-stage
CTLEs (9.2 %) and 1-tap DFE (11 %). Table I summarizes
the performance of the proposed RX and presents a com-
parison of this work with previous work. Compared to [10]
and [11], even if an inductor is not used, the proposed AFE
can sufficiently overcome a similar channel loss with a low
FOM. The FOM of the AFE was the lowest in [13], but the
feed-forward equalizer (FFE) at the transmitter (TX) reduces
the burden of compensation at the AFE of the RX; this, in
turn, lowers the power consumption of the AFE. Instead, the
proposed RX can reduce the power dissipation of the 1-tap
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DFE, thereby minimizing the total power consumption of the
AFE and DFE.
V. C ONCLUSION
This brief presented a 25 Gb/s wireline receiver configured
to an AFE with FFEQ and FEBQ, clock I/O, and a 1-tap
DFE. The proposed AFE controls the DC gain of the AFE
regardless of the CTLE boundary by using NFF and NFB .
Furthermore, FBEQ increases the peaking gain of the AFE
because the damping factor (ζ1 ) is changed by NFB , similar to
the 2nd order system. As a result, the FFEQ and FBEQ assist
the CTLE in improving equalization capability and reducing
the burden of the DFE to compensate for ISI.
ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education
Center (IDEC), South Korea.
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