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SL1 - Aula 04 e Aula 05 - Slides 05-06
SL1 - Aula 04 e Aula 05 - Slides 05-06
Docentes:
Prof. Pedro Sousa, pas@fct.unl.pt
Sistemas Lógicos 1 pim@fct.unl.pt
Prof. João Paulo Pimentão,
Departamento de Engenharia Electrotécnica e Computadores
Other logical operators
• NAND
• NOR
• XOR (Exclusive OR)
• XNOR
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Universal Gates
NAND gates are sometimes called universal gates
because they can be used to produce the other basic
Boolean functions.
A A A AB
B
Inverter AND gate
A A
A+B A+B
B B
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Universal Gates
NOR gates are also universal gates and can form all of
the basic gates.
A A A A+ B
B
Inverter OR gate
A A
AB AB
B B
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
A
C X= AC + AB
A
B
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Examples
• Implement using NANDs:
– A.B + C + D.A
– A+B + C.A + D
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Examples
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Overview
• What are Canonical Forms?
• Minterms and Maxterms
• Index Representation of Minterms and
Maxterms
• Sum-of-Minterm (SOM) Representations
• Product-of-Maxterm (POM) Representations
• Karnaugh Maps
• Representation of Complements of Functions
• Conversions between Representations
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Canonical Forms
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Minterms
• Minterms are AND terms with every variable
present in either true or complemented form.
• Given that each binary variable may appear normal
(e.g., x) or complemented (e.g.,x ), there are 2n
minterms for n variables.
• Example: Two variables (X and Y) produce
2 x 2 = 4 combinations:
• (both normal)
• (X normal, Y complemented)
• (X complemented, Y normal)
• (both complemented)
• Thus there are four minterms of two variables.
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Maxterms
• Maxterms are OR terms with every variable in true or
complemented form.
• Given that each binary variable may appear normal
(e.g., x) or complemented (e.g., x), there are 2n
maxterms for n variables.
• Example: Two variables (Y and X) produce
2 x 2 = 4 combinations:
• (both normal)
• (x complemented, y normal)
• (x normal, y complemented)
• (both complemented)
• Thus there are four Maxterms of two variables.
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Maxterms and Minterms
• Examples: Two variable minterms
and maxterms. Y,X
Index Minterm Maxterm
0 (00)
1 (01)
2 (10)
3 (11)
• The index above is important for
describing which variables in the terms
are true and which are complemented.
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Standard Order
• Minterms and maxterms are designated with a subscript
• The subscript is a number, corresponding to a binary
pattern
• The bits in the pattern represent the complemented or
normal state of each variable listed in a standard order.
• All variables will be present in a minterm or maxterm and
will be listed in the same order
• Example: For variables c, b, a (this is the weight order):
– Maxterms: (c + b + a), (c + b + a)
– Terms: (b + a + c) and (b + a + c) are NOT in standard
order.
– Minterms: c b a, c b a, c b a
– Terms: c a, c b, and (c + b) do NOT contain all
variables
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Purpose of the Index
• The index for the minterm or maxterm, expressed as
a binary number, is used to determine whether the
variable is shown in the true form or complemented
form.
• For minterms:
– “1” means the variable is “Not Complemented” and
– “0” means the variable is “Complemented”.
• For Maxterms:
– “0” means the variable is “Not Complemented” and
– “1” means the variable is “Complemented”.
• e.g. 13 = 1101 for DCBA means
• as minterm m13 and
• as Maxterm M13
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Index Examples – Four Variables
Index Binary Minterm Maxterm
i Pattern mi Mi
0 0000 a b c d
1 0001 a b c d ?
3 0011 ? a+b+c+d
5 0101 a b c d a + b + c + d
7 0111 ? a+b+c+d
10 1010 a b c d a + b + c + d
13 1101 a b c d ?
15 1111 a+b+c+d
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Minterm and Maxterm Relationship
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Function Tables for Both
• minterms of Maxterms of
2 variables 2 variables
xy m0 m1 m2 m3 x y M0 M1 M2 M3
00 1 0 0 0 00 0 1 1 1
01 0 1 0 0 01 1 0 1 1
10 0 0 1 0 10 1 1 0 1
11 0 0 0 1 11 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
165432
70+
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Minterm Function Example
• F(A, B, C, D, E) = ????
Can you guess the expression ?
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Maxterms
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Maxterm Function Example
• Example: Implement F1 in maxterms:
F1 (x,y,z)= M0 · M2 · M3 · M5 · M6
F1 = (x + y + z) · + y + z)· + y + z )
· x + y + z )·(xx + y + (x
z)
( i M ⋅ guess
x( y z you
Can M2⋅ M ⋅ M5?
⋅M =
0 0 0 0 00 ⋅ 1 ⋅ 31 ⋅ 1 ⋅ 1 =
F1
0(Expression
0 1 1 1 ⋅ 1 ⋅ 1 ⋅F1 1⋅
6
1 =
0
010 2 1 ⋅ 0 ⋅ 1⋅ 1 ⋅ 1 =
1
0 1 1 3 and
1 ⋅ 1 ⋅ 0⋅ 1 ⋅ 1 =
0
1 0Truth ⋅ 1 ⋅ 1⋅ 1 ⋅
0 4 1 Table) 1 =
0
101 5 1 ⋅ 1 ⋅ 1⋅ 0 ⋅ 1 =
1
110 6 1 ⋅ 1 ⋅ 1⋅ 1 ⋅ 0 =
0
111 7 1 ⋅ 1 ⋅ 1⋅ 1 ⋅ 1 =
0
Sistemas Lógicos 1 1
Departamento de Engenharia Electrotécnica e Computadores
⋅76543210i
F1 (x,y,z)= (x+y+z)(x+y+z)(x+y+z)(x+y+z)(x+y+z)
xyz M0 M2 M3 M5 M6 = F1
000 0 1 1 1 1 =0
001 1 1 1 1 1 =1
010 1 0 1 1 1 =0
011 1 1 0 1 1 =0
100 1 1 1 1 1 =1
101 1 1 1 0 1 =0
110 1 1 1 1 0 =0
111 1 1 1 1 1 =1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Maxterm Function Example
• F( D , C, B, A ) = M 2⋅ M 8 ⋅ M 11 ⋅ M 14
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth table and Function
D C B A F
0 0 0 0
0 0 0 1 “Tirar Pelos uns”
0 0 1 0 F=
0 0 1 1
D’C’B’A’+D’C’B’A+D’C’BA’+D’C’BA+
0 1 0 0
D’CB’A’+D’CB’A+D’CBA’+D’CBA+
0 1 0 1
0 1 1 0 DC’B’A’+DC’B’A+DC’BA’+DC’BA+
0 1 1 1 DCB’A’+DCB’A+DCBA’+DCBA
1 0 0 0 =1
1 0 0 1
1 0 1 0 “Tirar Pelos zeros”
1 0 1 1 Y=
1 1 0 0 (D+C+B+A)(D+C+B+A’)(D+C+B’+A)(D+C+B’+A’)
1 1 0 1 (D+C’+B+A)(D+C’+B+A’)(D+C’+B’+A)(D+C’+B’+A’)
1 1 1 0 (D’+C+B+A)(D’+C+B+A’)(D’+C+B’+A)(D’+C+B’+A’)
1 1 1 1 (D’+C’+B+A)(D’+C’+B+A’)(D’+C’+B’+A)(D’+C’+B’+A’)
=0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth table and Function
D C B A F
0 0 0 0 1
0 0 0 1 1 “Tirar Pelos uns”
0 0 1 0 1 F=
0 0 1 1 1
D’C’B’A’+D’C’B’A+D’C’BA’+D’C’BA+
0 1 0 0 0
D’CB’A’+D’CB’A+D’CBA’+D’CBA+
0 1 0 1 0
0 1 1 0 0 DC’B’A’+DC’B’A+DC’BA’+DC’BA+
0 1 1 1 0 DCB’A’+DCB’A+DCBA’+DCBA
1 0 0 0 0 =D’C’ (B’A’+B’A+BA’+BA)
1 0 0 1 0 =D’C’
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth table and Function
D C B A F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
“Tirar Pelos zeros”
0 1 0 1 0 F=
0 1 1 0 0 (D+C+B+A)(D+C+B+A’)(D+C+B’+A)(D+C+B’+A’)
0 1 1 1 0 (D+C’+B+A)(D+C’+B+A’)(D+C’+B’+A)(D+C’+B’+A’)
1 0 0 0 1 (D’+C+B+A)(D’+C+B+A’)(D’+C+B’+A)(D’+C+B’+A’)
1 0 0 1 1 (D’+C’+B+A)(D’+C’+B+A’)(D’+C’+B’+A)(D’+C’+B’+A’)=
1 0 1 0 1 =(D+C’)
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
A F A 0 1
0 1 1 0
1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
B A F A\B 0 1
0 0 1 0 00 10
0 1 0 1 01 11
1 0 0
1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
C B A F
0 0 0 BA\C 0 1
0 0 1 00 000 100
0 1 0
01 001 101
0 1 1
1 0 0 011 111
11
1 0 1
1 1 0 10 010 110
1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
C
D
m D C B A F BA\DC 00 01 11 10
0 0 0 0 0
1 0 0 0 1 00 0000 0100 1100 1000
2 0 0 1 0
3 0 0 1 1 01 0001 0101 1101 1001
4 0 1 0 0 Binário
A
5 0 1 0 1 11 0011 0111 1111 1011
6 0 1 1 0 B
7 0 1 1 1 10 0010 0110 1110 1010
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0 BA\DC 00 01 11 10
11 1 0 1 1
00 0 4 12 8
12 1 1 0 0
13 1 1 0 1 01 1 5 13 9
14 1 1 1 0 Decimal
15 1 1 1 1 11 3 7 15 11
10 2 6 14 10
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
m D C B A F
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 0 15 0 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 F=D’C’B’
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
DCBA
F=D’C’
6 0 1 1 0 0
01 1 1 0 5 0 13 0 9
7 0 1 1 1 0 A
8 1 0 0 0 0 11 1 3 0 7 0 15 0 11
9 1 0 0 1 0 B
10 1 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
m D C B A F
0 0 0 0 0 0 C
D
1 0 0 0 1 0
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 0 4 12 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 5 13 9
A
7 0 1 1 1 0
11 3 7 15 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 2 6 14 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
m D C B A F
C
0 0 0 0 0 0
D
1 0 0 0 1 0
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 0 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 0 1 0 5 0 13 0 9
A
7 0 1 1 1 0 11 0 3 0 7 1 15 1 11
8 1 0 0 0 0 B
9 1 0 0 1 0 10 0 2 0 6 1 14 1 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
F=DB
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
m D C B A F
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 0 4 12 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 5 13 9
A
7 0 1 1 1 0
11 3 7 15 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 2 6 14 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
F=BD+D’C’B’
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
C
D
BA\DC 00 01 11 10
00 1 0 0 4 0 12 1 8
01 0 1 0 5 0 13 0 9
A
11 0 3 0 7 0 15 0 11
B
10 0 2 0 6 0 14 0 10
F=BD+D’C’B’
Can you guess the expression ?
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
C
D
BA\DC 00 01 11 10
00 1 0 0 4 0 12 1 8
01 0 1 0 5 0 13 0 9
A
11 0 3 0 7 0 15 0 11
B
10 0 2 0 6 0 14 0 10
F=C’B’A’
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
DCBA
C
D
BA\DC 00 01 11 10
00 1 0 0 4 0 12 1 8
01 0 1 0 5 0 13 0 9
A
11 0 3 0 7 0 15 0 11
B
10 1 2 0 6 0 14 1 10
F=C’A’
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 0 15 0 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 0 15 0 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 0 15 0 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 F=C’.D’. B’
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 1
BA\DC 00 01 11 10
3 0 0 1 1 1
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 1 3 0 7 0 15 0 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 1 2 0 6 0 14 0 10
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 F=C’.D’
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 0 C
D
1 0 0 0 1 0
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 0 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 0 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 1 15 1 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 1 14 1 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 0 C
D
1 0 0 0 1 0
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 0 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 0 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 1 15 1 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 1 14 1 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0 F= B.D
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 1 15 1 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 1 14 1 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Truth Tables and Karnaugh Maps
Using zeros
m D C B A F DCBA
0 0 0 0 0 1 C
D
1 0 0 0 1 1
2 0 0 1 0 0
BA\DC 00 01 11 10
3 0 0 1 1 0
4 0 1 0 0 0 00 1 0 0 4 0 12 0 8
5 0 1 0 1 0
6 0 1 1 0 0 01 1 1 0 5 0 13 0 9
A
7 0 1 1 1 0
11 0 3 0 7 1 15 1 11
8 1 0 0 0 0
B
9 1 0 0 1 0 10 0 2 0 6 1 14 1 10
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0 F=(D+B’)(D+C’)(D’+B)
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Sistemas Lógicos 1
Departamento de Engenharia Electrotécnica e Computadores
Exercises
F1(D,C,B,A)= ∑(0,1,4,5,10,11,14,15)
F2(D,C,B,A)= 𝚷(0,1,8,9,10,11)