Operational Amplifier circuits

Sina Vafi
College of Engineering, IT and Environment
 The Two stage CMOS OP-AMP
First stage:
• Differential Q1-Q2 , current mirror load Q3-Q4
• Converts differential to single-ended form
• Provides a reasonable CMRR
• It is biased by current source Q5

Second stage:
• Common-source amplifier (by Q6),
current source load Q7
• Biased by by Q8, Q5 and Q7
• The current mirror is fed by Iref
• It typically provides a gain of 50V/V to
80 V/V.
• It takes part in the process of frequency
compensating the op-amp (through
Capacitance Cc)

Q5 and Q8: Mirror-current.

•It supplies differential pair Q1-Q2
CC: It enhances Miller effect to provide a dominant pole Sedra,6th edition,ISBN:9780199738519

CC also acts as a negative feedback and

creates more stability for the amplifier.
 Input offset voltage of OP-AMP

•Two input terminals are grounded.

•If the input stage is perfectly matched: the voltage appearing at the drain of Q4 will
be equal to the voltage at the drain of Q3, i.e. (-VSS+VGS4).
•This voltage is fed to the gate of Q6.
•VD4=VD3= -VSS+VGS4
•VDS4=VGS4 and VDS4=VGS6 Then VGS4=VGS6

(W / L)6
I6  ( I / 2)
(W / L)4

•No offset voltage at the output: I6 should be equal to I7.

(W / L)7
Q5 and Q7 form a current source I7  I
(W / L)5

In order to have I6=I7:

( W / L) 6 ( W / L) 7
2
( W / L) 4 ( W / L) 5
 Input Common-Mode Range of the Op-AMP
• In common-mode, inputs of the differential amplifiers are tied together
Assume inputs are sourced by VICM.
Lowest value of VICM:
• Large enough to keep Q1 and Q2 in saturation.
Q1 : PMOS → VSD1 ≥VSG1-|Vtp| OR VD1 ≤ VG1+|Vtp| (*)

Voltage at the drain of Q1 (VD1) : -VSS+VGS3=-VSS+Vtn+VOV3 We have VG1=VICM (**)

From (*) and (**) → VICM ≥ -VSS+Vtn+VOV3-|Vtp| (1)

Highest value of VICM:

• Low enough to keep Q5 in saturation.
• Operation of Q5 in saturation : VSD5 ≥ |VOV5| or VD5 ≤ VDD-|VOV5| (VS5=VDD) (◊)
We have VD5=VSG1+VICM (◊◊)

From (◊) and (◊◊): VICM ≤ VDD -|VOV5|- VSG1 OR VICM ≤ VDD -|VOV5|- |Vtp|-|VOV1| (2)

Note:
• Overdrive voltages are important design parameters.
• From (1) and (2): Overdrive voltages (|VOV3| and |VOV5| are subtracted from dc
power supply). This reduces the input common-mode range.
• Lower VOV provides greater range for VICM.
 Output Swing of the Op-AMP

• It is limited at the lower end by the condition that maintains Q6 in saturation

• It is limited at the upper end by the condition that maintains Q7 in saturation

Q7 (PMOS): VSD7 ≥ VSG7-|Vtp| or VSD7 ≤|VOV7| , VS7=VDD , VD7=vO → vO ≤ VDD-|VOV7|

Q6 (NMOS): VDS6 ≥ VOV6 VD6=vO , VS6=-VSS → vO ≥ -VSS+VOV6

-VSS+VOV6 ≤ vO ≤ VDD- |VOV7|

Note:
• In order to achieve a wide range for the output voltage swing, VOVs should be low as
possible.
• fT is proportional to VOV6.This means, greater VOV provides greater fT.

An important requirement of an op-amp:

• It should be possible for Its output to be connected back to its negative input
terminal so that a unity-gain amplifier is obtained.

Possibility to have a unity-gain amplifier:

• Substantial overlap between the range of vO and VICM.
 Voltage gain of OP-AMP
• Apply small-signal model of the amplifier
• Each stage is modelled as a transconductance amplifier
• The input resistance is infinite
Transconductance of the first stage: Gm1=gm1=gm2
• Q1 and Q2 are operated at equal bias current and equal overdrive voltage
22
= =
| |
Output resistance of the first stage: R1=ro2||ro4 , = =
/ /

A1=-Gm1R1=-gm1(ro2||ro4) or =

Transconductance of the second stage: = =

Sedra,6th edition,ISBN:9780199738519
 Voltage gain of OP-AMP (cont.)
| |
Output resistance of the second stage: R2=ro6||ro7 , = =

A2=-Gm2R2=-gm6(ro6||ro7) or =

In order to have a higher gain from A2:

• Q6 has to operated at a low overdrive voltage (Vov)
• Channel lengths (L) of Q6 and Q7 should be made longer.
Note:
Higher Vov and L reduce amplifier bandwidth.

The overall DC gain: Av=A1A2

Av=Gm1R1Gm2R2 or Av=gm1(ro2||ro4) gm6(ro6|| ro7)

Conclusion:
AV is in range of (gmro)2. The maximum value of Av would be in the range of 500 V/V
To 5000 V/V.

Output resistance of op-amp:

It is the output resistance of the second stage. That is, Ro=ro6||ro7.
 Frequency response of OP-AMP:

Sedra,6th edition,ISBN:9780199738519

C1=Cgd+Cdb4+Cgd2+Cdb2+Cgs6
C2=Cdb6+Cdb7+Cgd7+CL
Gm1: transconductance of the first stage (Gm1=gm1=gm2)
Gm2: transconductance or the second stage
R1: Output resistance of the first stage (ro2||ro4)
CL: is the capacitor load and usually is larger than other capacitors. Thus C2>>C1.
Cgd6 is in parallel with CL. Since CL>>Cgd6: CL+Cgd6≈CL
KCL at node D2:
vi2
G m 1 v id   sC 1 Vi 2  sC C ( Vi 2  Vo )  0
R1
 Frequency response of OP-AMP (cont.):
KCL at node D6:
vo
Gm2vi2   sC2Vo  sCC (Vo  Vi2 )  0
R2
Vo G m1 (G m 2  sC C ) R 1R 2

Vid 1  s[C1R 1  C 2 R 2  C C (G m 2 R 1R 2  R 1  R 2 )]  s 2 [C1C 2  C C (C1  C 2 )]R 1R 2
G m2
Zero: sZ  Z 
CC

1 1
Poles: P1  P1 
R 1 C1  CC (1  G m 2 R 2 ) R 1CC G m 2 R 2

G m 2CC G m2
P 2  P 2 
C1C 2  CC (C1  C 2 ) C2

•DC gain: (Gm1R1Gm2R2)

G m1
•P1 is a dominant pole: → ωt= (Gm1R1Gm2R2)ωP1 or t 
CC
 Frequency response of OP-AMP (cont.):

• In order to achieve a uniform -20 dB/decade gain roll-off to 0 dB:

• ft must be lower than fP2 and fZ . This means:
(Gm1/Cc) < (Gm2/C2) and Gm1 <Gm2

Sedra,6th edition,ISBN:9780199738519
 Slew Rate (SR) of OP-AMP
• Consider the unity-gain follower: VI is a step function voltage
(1V applied at the input)
• The output will not change in zero time (it takes time to follow
changes of the input voltage).
• If the inserted input signal demands an output faster
than Slew rate, the op-amp will not follow that response.
• Immediately after the input is applied, the entire
value of the step will appear as a differential signal
between the two input terminals.
• Slew rate (SR) =dvo/dt
Sedra,6th edition,ISBN:9780199738519

The first stage:

• If Q2 is turn off, Q1 will conduct the entire current I.
• Q4 will sink a current that will be pulled from CC.
The second stage:
• Can be modelled as an integrator (due to capacitance
Cc).
• vo(t)= I t/Cc
• Slew rate will be SR=I/CC
• We have Gm1=gm1=I/VOV and ωt=Gm1/CC.
• SR=2 πft VOV or SR=VOV ωt. Sedra,6th edition,ISBN:9780199738519
 Slew Rate (SR) of OP-AMP (cont.)

Why did we choose Q1 and Q2 as P-MOSFET?

1. Higher slow rate is obtained by operating Q1 and Q2 at a larger VOV.

For a fixed bias current I, a larger VOV is obtained if Q1 and Q2 are p-channel devices

2. It allows the second stage to be designed as n-channel device.

Note:
• n-channel devices have greater transconductance than corresponding p-channel
devices.

#$
• A higher value of Gm2 , higher second pole frequency and higher ωt ( !" = %
)
is concluded.

Disadvantage of such this design (using P-MOS in the first stage)

Lower Gm1 is formed at the first stage → a lower dc gain.
 Folded-cascode CMOS OP AMP

Sedra,6th edition,ISBN:9780199738519
 Folded-cascode CMOS OP AMP (Cont.)
Q1 and Q2:
• Input differential pair
• They are common-source amplifier
• The input differential pair is biased by a constant-current source I
• Darin currents of Q1 and Q2: I/2

Q3 and Q4:
• Cascode transistors
• Gates of these transistors are connected to a constant voltage (VBIAS1)
• The bias current for Q3 and Q4: IB-I/2.
• If IB=I, drain currents of Q3 and Q4 will be I/2 .

For differential input signals:

• Each of transistor pairs Q1-Q3 and Q2-Q4 act as a folded-cascode amplifier
• Cascode current mirror: provides a high output resistance.

Capacitance CL:
Denotes total capacitance at the output.
 Input Common-Mode range of
folded cascode amplifier
• Input terminals are connected together and fed by voltage VICM .
Maximum value of VICM:
• It is limited based on the condition that maintains Q1 and Q2 in saturation mode.
VICM ≤ Vtn+ (VD)Q1,Q2

• (VD)Q1,Q2 is determined based on VBIAS1.

• VBIAS1 should be set to a value so as (VD)Q1,Q2 ≥ VDD- |VOV9| (or |VOV10|)
Assume
Q9 and Q10 are operated at the edge of saturation. Hence,
(VICM)max= VDD-|VOV9|+Vtn (VSD9= |VOV9|)

Criteria for VBIAS2 value:

• To provide the required value of IB .
• Q9 and Q10 should operate at small value of |VOV| (≈ 0.2 V).
Minimum value of VICM :
• Q11 should remain in saturation mode
(VICM)min= -VSS+(VOV)11+(VOV)1+Vtn
(VICM)max is in range of VDD
Note:
(VICM)min is not a small value as it is greater than Vtn.
• The value of VBIAS3 should be set so as to provide the required value of I
• Q11 should operate at a low overdrive voltage
Maximum value of vO:
• Should maintain Q10 and Q4 in saturation.
• Q10 operates in saturation when VSD ≥ |VOV|.
• Maximum possible swing of vO means maximum value of VICM
• Select the value of VBIAS1 so that Q10 operates at the edge of saturation:
VSD10 ≥ |VOV10| or VDD-VS4 >|VOV10|,
We write VG4+VDD-VS4 >= VG4+ |VOV10|. VG4=VBIAS1. Hence, VBIAS1=VDD-|VOV10|-VSG4.
• Q4 operates in saturation (VG4-VD4≥ -|Vt4|)

(vO)max=VDD-|VOV10|-|VOV4|

At the gate of Q6:

VG6=-VSS+VGS7+VGS5 or VG6= - VSS+VOV7+VOV5+2Vtn

Minimum value of vO:

• Q6 is at the edge of saturation(VGD ≤ Vt)
(vO)min=-VSS+VOV7+VOV5+Vtn

This (vO)min is a high voltage.

 Increasing the output voltage Range: The
wide-Swing Current Mirror

From the analysis of two-stage amplifier:

• Ideally, we would like to have (Vo)min=-VSS+ 2VOV
• Cascode mirror reduces the voltage swing by Vt volts

For the current mirror (with VSS=0 V):

• Voltage at gate Q3: 2Vt+2VOV

The minimum voltage permitted at the output :

• Q3 remains in saturation. Hence
VGD3 ≤ Vt3 OR VD3 ≥ VG3-Vt3

VD3 ≥ Vt3+2VOV3
VS3=VD1 and VDS3 ≥ VOV
or VD1 ≤ Vt+VOV

The maximum voltage at drain of Q3 ((vD3)max or ((vO)max):

(vO)max=VDD-2|VOV| (Q3 remains in saturation if VD3 ≥ 2VOV)
• In order to have (Vo)min=-VSS+ 2VOV:
1. Voltage at gate of Q3 should be set to Vt+2VOV
2. VD3 ≥ 2VOV Sedra,6th edition,ISBN:9780199738519
 Increasing the output voltage Range: The
wide-Swing Current Mirror (cont.)
How to do it (to have VD3=2VOV and VG3=Vt+2VOV) ?
• Gate of Q3 is connected to a bias voltage with the amount of VBIAS=Vt+2VOV
• Voltage at drain of Q2:
• VBIAS=VGS4+VDG2+VGS2 or VBIAS=VGS4+VD2 .
• Let VGS4 =VGS . Then, VD2= VOV. .
• Similarly, voltage at drain of Q1: VOV (Q1: edge of saturation)
• Voltage at drain of Q3: 2VOV (Q3 remains in saturation).

Note:
• Gate and drain of Q2 are not connected together
• Instead, gate of Q2 is being connected to drain of Q4.

VD4 =Vt+VOV (Q4 is in saturation)

Sedra,6th edition,ISBN:9780199738519
 Voltage gain of folded cascode amplifier
• As a product of short circuit transconductance (Gm) and output resistance (Ro)
'

Short circuit transconductance (Gm): Gm=gm1=gm2 or Gm=

Output resistance: Ro=Ro4||Ro6
Ro4: Output resistance of cascode amplifier. Ro4≈ (gm4ro4)(ro2||ro10)
Ro6: Output resistance of cascode mirror, Ro6 ≈ gm6 ro6 ro8

Av= Gm Ro → Av=gm1{[gm4 ro4(ro2||ro10)] || (gm6 ro6 ro8)}

Conclusion: The amplifier has a high output resistance.

What we know from OP-AMPS: Good OP AMPS have low output resistance.

How to provide a low Ro?

Connect the output terminal of the circuit to the negative input terminal.
Feedback type: Series-Shunt

* *
( ) = ≈ = or Rof=1/gm1
+, +, #$

gm1 is in order of 1mA/V. Hence Rof will be in range of KΩ.

It is much lower than Ro but still is not low enough to drive low-valued resistive loads.
 Frequency Response of
folded cascode amplifier
• Based on analysis conducted for cascode amplifier
• Two poles are at very high frequencies
• Dominant pole due to CL (if CL is not large)

- #$ *
• Refer to Figure 12.11: =
./ 0%1 *

Dominant pole: fP=

2%1 *

#$
Unity-gain frequency: ft=GmRofP=
2%1

Note: CL should be selected so as the given ft provides the required phase margin

If CL is increased:
• ft decreases and frequency of the second pole also decreases
• Phase margin is increased and bandwidth is reduced.
• Increase in CL can be compensated by increase in Cc such that a lower
value of ft and required phase margin is obtained.
 Slew Rate of folded cascode amplifier

• Slewing occurs when a large differential input is applied

• Assume large Vid is applied such that Q1 is off and Q2 conducts the entire current I

Current at Q3: IB-I

Current at Q4: I
Current mirror: IB-I (through Q5 and Q7)
Output current in the drain of Q6: IB-I
Current flows into CL: I4-I6=IB-(IB-I)=I

Conclusion:
Output vo will be a ramp with a slope of I/CL. Hence, SR=I/CL

Note: This condition is valid for IB>I .

Typically, IB is set 10% to 20% greater than I

An alternative expression of SR (for the proposed two-stage amplifier):

SR=2π ft VOV1
Rail-to-rail cascode amplifier

Sedra,6th edition,ISBN:9780199738519
 Rail-to-rail cascode amplifier (cont.)
A drawback of the proposed two-stage amplifier:
• Low input common-range ((VICM)min is not very low ).
Solution:
• Put an NMOS and a PMOS differential pair in parallel
• It exceeds the power supply voltage in positive and negative directions
• Two positive input terminals are connected together
• Two negative input terminals are connected together
• Q5 and Q6 are the cascode transistors for the Q1-Q2
• Q7 and Q8 are the cascode transistors for the Q3-Q4

Let Vid be the differential input signal

• Current at Drains of Q6 and Q8: Gm(Vid/2). Gm=gm1=gm2=gm3=gm4
• Total current at output nodes: Gm Vid

Let Ro be the output resistance between each of the two nodes and ground:
• Vo=2GmRoVid
• The voltage gain: Av= 2GmRo
Note:
• For a limited range of VICM, both differential pairs operate
• On the remainder of the input common-mode range (out of range of VICM),
only one differential pair operates.
• In this case, gain is dropped to half of 2 Gm Ro (AV=GmRo).