CMOS parallel camera with VGA

Introduction Camera interface

resolution
• The camera interfacing code consists of two main modules.
• The input capture image and the camera configuration.
• The input capture code is responsible of transmitting the pixels
to the frame buffer. This module decodes the pixels coming
from the camera.
• Each pixel is packed into 2 consecutive bytes. The Input capture
modules converts this to RGB444. 
• multiple pixel image formats RGB565

Functional Block Diagram • The OV7670/OV7171 sensor has an

image array of 656 x 488 pixels for a
Image Sensor total of 320,128 pixels
Array • Of which 640 x 480 pixels are active
(307,200 pixels).
 Timing Generator Analog Signal Processor
• In general, the timing generator controls the following functions: • This block performs all analog image functions including:
• Array control and frame generation Automatic Gain Control (AGC)
Automatic White Balance (AWB)
• Internal timing signal generation and distribution
• Frame rate timing
• Automatic Exposure Control (AEC)
• External timing outputs (VSYNC, HREF/HSYNC, and PCLK)

A/D converter Test Pattern Generator

• After the Analog Processing block, Raw signal is fed to a 10-bit • The Test Pattern Generator features the following:
analog-to-digital (A/D) converter shared by GBR channels.
• This A/D converter operates at speeds up to 12 MHz and is 8-bar color bar pattern
fully synchronous to the pixel rate (actual conversion rate is Fade-to-gray color bar pattern
related to the frame rate). Shift "1" in output pin
Digital Signal Processor (DSP) Camera configuration
• Datasheet information
• This block controls the interpolation from Raw data to RGB and some • I2C-like SSCB interface is needed to communicate with the camera,
image quality control. configure it, and get image data
• Edge enhancement (a two-dimensional high pass filter) • The device control register list
• Color space converter (can change Raw data to RGB or YUV/YCbCr) .
• RGB matrix to eliminate color cross talk
• Hue and saturation control
• White/black pixel correction
• De-noise
• Lens shading correction
• Programmable gamma control
• Transfer 10-bit data to 8-bit

Horizontal Timing VGA Frame Timing

QVGA Frame Timing QQVGA Frame Timing

CIF Frame Timing RGB 565 Output Timing Diagram

555 Output Timing Diagram RGB 444 Output Timing Diagram

Timing

Displaying
the real-time
video/image
on a VGA
monitor
 VGA – Video Graphics Array
• Video display standard introduced in the late 1980’s
• Widely supported by PC graphics hardware
and monitors
• Used initially with the CRT (cathode ray tube)
monitors
• Later adopted for LCD monitors as well
ECE 448 – FPGA and ASIC Design with VHDL
Operation of a CRT monitor
ECE 448 – FPGA and ASIC Design with VHDL
VGA – Characteristic Features
• Resolution: 640x480
• Display: up to 256 colors (8 bits)
• Refresh Rate: 25Hz, 30Hz, 60Hz (frames / second)
• RGB: Red, Green and Blue analog signals
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CRT Monitor – Conceptual Diagram
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 CRT Monitor – Scanning Pattern CRT Monitor – Horizontal Scan

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VGA Controller – Simplified View

VGA Controller

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 Three-bit VGA Color Combinations

VGA Synchronization

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Horizontal Synchronization Four regions of hsync

• Display: 0..639, width = 640

• Right border (front porch): 640..655, width = 16
• Retrace (horizontal flyback): 656..751, width=96
• Left border (back porch): 752..799, width=48

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 Vertical Synchronization Four regions of vsync

• Display: 0..479, width = 480 lines

• Bottom border (front porch): 480..489, width = 10
• Retrace (vertical flyback): 490..491, width=2
• Top border (back porch): 491..524, width=33

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Pixel Rate

• p: the number of pixels in a horizontal scan line

p = 800 pixels/line
• l: the number of horizontal lines in a screen
l = 525 lines/screen Pixel Generation Circuit
• s: the number of screens per second (refresh rate)
s = 60 screens/second

Pixel Rate = p • l • s = 25 Mpixels/second

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 VGA Controller – Simplified View
ECE 448 – FPGA and ASIC Design with VHDL
Tile-Mapped Pixel Generation Circuit
• Tile = a group of pixels, e.g., 8x8 square of pixels
• The 640x480 pixel-oriented screen becomes
an 80x60 tile-oriented screen
• The tile can hold a limited number of patterns, e.g. 32
• For each tile we need to store the number
of a displayed pattern (in the range 0..31)
• Tile memory
80•60 tiles/screen • 5 bits/tile ≈ 24 kbits
Pattern memory
32 patterns • 64 bits/pattern = 2kbit
ECE 448 – FPGA and ASIC Design with VHDL
Bit-Mapped Pixel Generation Circuit
• Video memory is used to store data to be
displayed
on the screen
• Each pixel is represented by a memory word
holding its color
• Graphics processing circuit continuously updates
the screen by writing to the video memory,
which is then read by the Pixel Generation Circuit
• Memory needed
640•480 = 310 kbits for a monochrome display
640•480•3 = 930 kbits for an 8-color display
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Example of a Tile Pattern
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Object-Mapped Scheme

• RGB signals are generated on the fly based

on the values of x and y coordinates
(pixel_x, pixel_y)
• Applicable to a limited number of simple objects
Graphic Generation
• No memory needed with an Object Mapped
Scheme

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Object-Mapped Pixel Generation Still Screen of the Pong Game

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 Generation of the Wall Stripe Generation of the Bar (Paddle)

32 ≤ x ≤ 600 ≤ x ≤ 603
35 204 ≤ y ≤ 275

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Generation of the Square Ball Selection and Multiplexing Circuit

580 ≤ x ≤ 587
238 ≤ y ≤ 245

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