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19 February 2020 1441 ‫ جمادى الثانية‬25

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Analog IC Design

Lecture 04
MOSFET Large Signal Model

Dr. Hesham A. Omran

Integrated Circuits Lab (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Outline
❑ Why is the Transistor Different?
❑ MOSFET Structure
❑ MOSFET Operation
▪ Depletion
▪ Inversion and Channel Formation
▪ Linear and Triode Region
▪ Saturation (Pinch-off) Region
❑ MOSFET IV Characteristics and Large Signal Model
❑ Channel Length Modulation
❑ Body Effect
❑ Short channel effects

04: MOSFET DC 2
 Why is the Transistor Different?
❑ We are used to two-terminal devices
▪ Resistors, capacitors, inductors, diodes
❑ The transistor is a three-terminal device I = f(Vctrl)
▪ The voltage between two terminals controls the
current flowing in the third terminal

Transistor
▪ Voltage controlled current source (VCCS)
❑ This feature enabled a multitude of applications that
changed our life!
Vctrl
▪ Analog signal amplification and processing
▪ Digital logic and memory circuits

04: MOSFET DC 3
 VCCS as an Amplifier
❑ Voltage controlled current source (VCCS): 𝑣𝑖𝑛 controls 𝑖𝑜𝑢𝑡
𝑖𝑜𝑢𝑡
𝑇𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 = = 𝐺𝑚
𝑣𝑖𝑛
𝑣𝑖𝑛 = 𝑉𝑝 sin 𝜔𝑡
𝑣𝑜𝑢𝑡 = 𝐺𝑚 𝑣𝑖𝑛 × 𝑅𝑜𝑢𝑡 = 𝐺𝑚 𝑅𝑜𝑢𝑡 𝑣𝑖𝑛 = 𝐺𝑚 𝑅𝑜𝑢𝑡 𝑉𝑝 sin 𝜔𝑡
𝑣𝑜𝑢𝑡
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝐺𝑎𝑖𝑛 = 𝐴𝑣 = = 𝐺𝑚 𝑅𝑜𝑢𝑡
𝑣𝑖𝑛
(GmRout)Vp
Vp vin vout

iout=
Rin Rout
Gmvin

04: MOSFET DC 4
 MOSFET
❑ MOSFET: Metal-oxide-semiconductor field-effect transistor
▪ N-channel MOSFET: NMOS
▪ P-channel MOSFET: PMOS
▪ Complementary MOS (CMOS) technology: NMOS + PMOS
❑ A.k.a. insulated-gate FET or IGFET
❑ Simply, a VCCS
❑ The concept of MOSFET was patented in 1925
❑ But it was not successfully fabricated till 1960s
❑ CMOS technology became the dominant IC fabrication technology by the 1980s

04: MOSFET DC 5
 N-Channel MOSFET Structure
❑ MOSFET: Metal-oxide-semiconductor field-effect transistor
❑ Three-terminal device: Gate (G), Source (S), and Drain (D)
❑ Substrate/Bulk/Body (S/B) can be treated as a fourth terminal

G
B S D
G
p+ n+ n+
p-sub S D
04: MOSFET DC [Razavi, 2014] 6
 MOSFET Dimensions
❑ Channel length: 𝐿 ~ 10𝑛𝑚 − 10𝜇𝑚
❑ Channel width: 𝑊 ~ 50𝑛𝑚 − 100𝜇𝑚
❑ Oxide thickness: 𝑡𝑜𝑥 ~ 1𝑛𝑚 − 10𝑛𝑚
❑ Gate formed of metal or polysilicon

04: MOSFET DC [Razavi, 2017] 7

 Depletion
❑ The device acts as a capacitor: positive charge on the gate is mirrored by negative charge in
the substrate
❑ The positive charge on the gate repels the holes in the substrate
▪ Fixed negative ions are exposed (uncovered)
▪ A depletion region is created

VGS<VTH VGD<VTH
G
S D

n+ n+
p-sub

04: MOSFET DC 8
 Inversion and Channel Formation
❑ N-type channel region (inversion layer) formed at
𝑽𝑮𝑺 > 𝑽𝑻𝑯
𝑽𝑮𝑺 = 𝑽𝑻𝑯 + 𝑽𝒐𝒗
▪ Threshold voltage: 𝑉𝑇𝐻 ~ 0.3𝑉 − 1𝑉
▪ Overdrive voltage: 𝑉𝑜𝑣 ~ 0𝑉 − 0.5𝑉 (for analog circuits)
▪ Electrons are provided by the n+ source and drain regions

VGS>VTH VGD>VTH
G
S D

n+ n+
p-sub
04: MOSFET DC 9
 Charge in Channel
𝜖𝑜𝑥 𝐴 𝜖𝑜𝑥 𝑊𝐿
𝐶𝑔𝑎𝑡𝑒 = = = 𝐶𝑜𝑥 𝑊𝐿
𝑑 𝑡𝑜𝑥
❑ For 𝑆𝑖𝑂2
𝐹
𝜖𝑜𝑥 = 𝜖𝑟 𝜖𝑜 = 𝟑. 𝟗 × 8.854 × 10−12
𝑚
𝜖𝑜𝑥 𝑓𝐹
❑ Example: if 𝑡𝑜𝑥 = 4𝑛𝑚 → 𝐶𝑜𝑥 = ≈ 8.6 2
𝑡𝑜𝑥 𝜇𝑚

𝑄 = 𝐶𝑉 = 𝐶𝑜𝑥 𝑊𝐿 ⋅ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝐶𝑜𝑥 𝑊𝐿 ⋅ 𝑉𝑜𝑣

04: MOSFET DC 10
 Linear Region (Deep Triode)
❑ Small 𝑉𝐷𝑆 : We assume the channel is uniform
❑ MOSFET acts as a voltage controlled resistor (VCR)
▪ Vertical field (𝑉𝐺𝑆 ) controls the channel depth (resistance value)
▪ Lateral field (𝑉𝐷𝑆 ) controls the carrier acceleration (drift current)

VGS>VTH VGD>VTH
G
S D

n+ n+
p-sub

Small VDS

04: MOSFET DC 11
 Linear Region (Deep Triode)
𝑄 = 𝐶𝑉 = 𝐶𝑜𝑥 𝑊𝐿 ⋅ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝐶𝑜𝑥 𝑊𝐿 ⋅ 𝑉𝑜𝑣
𝑉𝐷𝑆
𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝐹𝑖𝑒𝑙𝑑 = 𝐸 =
𝐿
𝑉𝐷𝑆
𝐶𝑎𝑟𝑟𝑖𝑒𝑟 𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 = 𝑣 = 𝜇𝑛 𝐸 = 𝜇𝑛
𝐿
𝑄 𝐿
𝐷𝑟𝑎𝑖𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡 = 𝐼𝐷 = = 𝐶𝑜𝑥 𝑊 ⋅ 𝑉𝑜𝑣 = 𝐶𝑜𝑥 𝑊 ⋅ 𝑣 ⋅ 𝑉𝑜𝑣
𝑡 𝑡
𝑊 𝑉𝐷𝑆
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 ⋅ 𝑉𝐷𝑆 =
𝐿 𝑅𝐷𝑆
1 1 1 1
𝑅𝐷𝑆 = = = =
𝑊 𝑊
𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 𝑘𝑛′ 𝑉𝑜𝑣 𝑘𝑛 𝑉𝑜𝑣 𝛽𝑛 𝑉𝑜𝑣
𝐿 𝐿
𝑊
𝐴𝑠𝑝𝑒𝑐𝑡 𝑅𝑎𝑡𝑖𝑜 =
𝐿

04: MOSFET DC 12
 Linear Region (Deep Triode)
𝑊 𝑉𝐷𝑆
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 ⋅ 𝑉𝐷𝑆 =
𝐿 𝑅𝐷𝑆

1 1 1 1
𝑅𝐷𝑆 = = = =
𝑊 𝑊
𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 𝑘𝑛′ 𝑉𝑜𝑣 𝑘𝑛 𝑉𝑜𝑣 𝛽𝑛 𝑉𝑜𝑣
𝐿 𝐿

𝑊
𝐴𝑠𝑝𝑒𝑐𝑡 𝑅𝑎𝑡𝑖𝑜 =
𝐿

VGS

S D

04: MOSFET DC 13
 Linear Region (Deep Triode)
❑ MOSFET acts as a voltage controlled resistor (VCR)
1 1 1 1 1
𝑅𝐷𝑆 = = = = =
𝐺𝐷𝑆 𝜇 𝐶 𝑊 ′ 𝑊 𝑘𝑛 𝑉𝑜𝑣 𝛽𝑛 𝑉𝑜𝑣
𝑛 𝑜𝑥 𝐿 ⋅ 𝑉𝑜𝑣 𝑘 𝑉
𝑛 𝐿 𝑜𝑣

❑ Linear characteristics

04: MOSFET DC [Sedra/Smith, 2015] 14

 Triode Region
❑ 𝑉𝐷𝑆 increases: The channel becomes tapered
❑ Voltage at source side: 𝑉𝐺𝑆 − 0 = 𝑉𝐺𝑆 = 𝑉𝑇𝐻 + 𝑉𝑜𝑣
▪ If 𝑉𝐺𝑆 > 𝑉𝑇𝐻 or 𝑉𝑜𝑣 > 0: The channel exists at source
❑ Voltage at drain side: 𝑉𝐺𝑆 − 𝑉𝐷𝑆 = 𝑉𝐺𝐷 = 𝑉𝑇𝐻 + 𝑉𝑜𝑣 − 𝑉𝐷𝑆
▪ If 𝑉𝐺𝐷 > 𝑉𝑇𝐻 or 𝑉𝐷𝑆 < 𝑉𝑜𝑣 : The channel exists at drain

VGS>VTH VGD>VTH
G
S D

n+ n+
p-sub

VDS<Vov

04: MOSFET DC 15
 Triode Region
❑ 𝑉𝐷𝑆 increases: The channel becomes tapered
❑ Voltage at source side: 𝑉𝐺𝑆 − 0 = 𝑉𝐺𝑆 = 𝑉𝑇𝐻 + 𝑉𝑜𝑣
▪ If 𝑉𝐺𝑆 > 𝑉𝑇𝐻 or 𝑉𝑜𝑣 > 0: The channel exists at source
❑ Voltage at drain side: 𝑉𝐺𝑆 − 𝑉𝐷𝑆 = 𝑉𝐺𝐷 = 𝑉𝑇𝐻 + 𝑉𝑜𝑣 − 𝑉𝐷𝑆
▪ If 𝑉𝐺𝐷 > 𝑉𝑇𝐻 or 𝑉𝐷𝑆 < 𝑉𝑜𝑣 : The channel exists at drain
❑ Average overdrive voltage:
𝑉𝑜𝑣 + 𝑉𝑜𝑣 − 𝑉𝐷𝑆 𝑉𝐷𝑆
𝑉𝑜𝑣 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 = = 𝑉𝑜𝑣 −
2 2
❑ Replace 𝑉𝑜𝑣 with 𝑉𝑜𝑣 𝑎𝑣𝑒𝑟𝑎𝑔𝑒
2
𝑊 𝑉𝐷𝑆 𝑊 𝑉𝐷𝑆
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 − ⋅ 𝑉𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 𝑉𝐷𝑆 −
𝐿 2 𝐿 2

04: MOSFET DC 16
 Triode Region
❑ Inverted parabola
2
𝑊 𝑉𝐷𝑆
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 𝑉𝐷𝑆 −
𝐿 2

04: MOSFET DC [Sedra/Smith, 2015] 17

 Pinch-Off (Saturation)
❑ 𝑉𝐺𝐷 = 𝑉𝐺𝑆 − 𝑉𝐷𝑆 ≤ 𝑉𝑇𝐻 → 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝑉𝑜𝑣
▪ No channel at drain side
▪ 𝑉𝐷𝑆 has no more control on the shape and charge of the channel
𝑉𝑜𝑣 +0 𝑉𝑜𝑣
❑ Average overdrive voltage: 𝑉𝑜𝑣 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 = = ≠ 𝑓 𝑉𝐷𝑆
2 2
❑ Voltage across channel is constant = 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 𝑉𝑜𝑣 ≠ 𝑓 𝑉𝐷𝑆
▪ Extra 𝑉𝐷𝑆 falls on the small region between channel and drain

VGS>VTH VGD<VTH
G
S D

n+ n+
p-sub

04: MOSFET DC
VDS>Vov 18
 Pinch-Off (Saturation)
❑ Replace 𝑉𝑜𝑣 with 𝑉𝑜𝑣 𝑎𝑣𝑒𝑟𝑎𝑔𝑒and 𝑉𝐷𝑆 with 𝑉𝑜𝑣
𝑊 𝑉𝑜𝑣 𝜇𝑛 𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ ⋅ 𝑉𝑜𝑣 = ⋅ 𝑉𝑜𝑣 ≠ 𝑓 𝑉𝐷𝑆
𝐿 2 2 𝐿
❑ Current remains constant (saturates) → VCCS

04: MOSFET DC [Sedra/Smith, 2015] 19

 Pinch-Off (Saturation)
❑ The channel is pinched off if the difference between the gate and drain voltages is not
sufficient to create an inversion layer
𝑉𝐺𝐷 ≤ 𝑉𝑇𝐻 𝑂𝑅 𝑉𝐷𝑆 ≥ 𝑉𝑜𝑣
❑ Square-law (long channel MOS)
𝜇𝑛 𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = ⋅ 𝑉𝑜𝑣
2 𝐿

VGS>VTH VGD<VTH
G
B S D

p+ n+ n+
p-sub

VDS>Vov
04: MOSFET DC 20
 IV Characteristics
𝜇𝑛 𝐶𝑜𝑥 𝑊 2 𝜇𝑛 𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = ⋅ 𝑉𝑜𝑣 = ⋅ 𝑉𝐺𝑆 − 𝑉𝑇𝐻
2 𝐿 2 𝐿

04: MOSFET DC [Sedra/Smith, 2015] 21

 Regions of Operation Summary
OFF
ON
(Subthreshold)
𝑉𝐺𝑆 > 𝑉𝑇𝐻
𝑉𝐺𝑆 < 𝑉𝑇𝐻

Triode Pinch-Off
(Saturation)
𝑉𝐷𝑆 < 𝑉𝑜𝑣
𝑉𝐷𝑆 ≥ 𝑉𝑜𝑣
Or
Or
𝑉𝐺𝐷 > 𝑉𝑇𝐻
𝑉𝐺𝐷 ≤ 𝑉𝑇𝐻

𝑊 2
𝑉𝐷𝑆 𝜇𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = 𝜇𝐶𝑜𝑥 𝑉 𝑉 − 𝐼𝐷 = 𝑉
𝐿 𝑜𝑣 𝐷𝑆 2 2 𝐿 𝑜𝑣

04: MOSFET DC 22
 P-Channel MOSFET (PMOS)
❑ Electrons have higher mobility than holes (2 – 4 times)
❑ For same W/L and 𝑉𝑜𝑣 , NMOS current is 2 – 4 times higher than PMOS

|VGD|<|VTH| |VGS|>|VTH|
G VDD
D S B

p+ p+ n+
n-sub

|VDS|>Vov

04: MOSFET DC 23
 MOSFET Symbols
❑ S/D junction diodes must be reverse-biased under all conditions
▪ NMOS bulk connected to most negative potential (ground)
▪ PMOS bulk connected to most positive potential (VDD)

NMOS

PMOS

04: MOSFET DC [Sedra/Smith, 2015] 24

 Large Signal Model in Saturation
❑ Ideal VCCS: no dependence on 𝑉𝐷𝑆
𝜇𝑛 𝐶𝑜𝑥 𝑊 2 𝜇𝑛 𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = ⋅ 𝑉𝑜𝑣 = ⋅ 𝑉𝐺𝑆 − 𝑉𝑇𝐻
2 𝐿 2 𝐿

G D

VGS ID

04: MOSFET DC 25
 Large Signal Model with Finite Output Res
❑ The transistor is a VCCS
❑ The VCCS is not ideal: There is some dependence on 𝑉𝐷𝑆
𝑉𝐷𝑆 𝑉𝐷𝑆 /𝐼𝐷𝑆
𝐼𝐷 = 𝐼𝐷𝑆 + = 𝐼𝐷𝑆 1 +
𝑟𝑜 𝑟𝑜
𝜇𝐶𝑜𝑥 𝑊 2
𝐼𝐷𝑆 = 𝑉𝑜𝑣
2 𝐿

ID
G D

VGS IDS ro VDS

04: MOSFET DC 26
 Channel Length Modulation (CLM)
❑ The VCCS is not ideal: There is some dependence on 𝑉𝐷𝑆
Δ𝑉𝐷𝑆 1 1 𝑉𝐴 1
𝑟𝑜 = = = = =
Δ𝐼𝐷 𝜕𝐼𝐷 /𝜕𝑉𝐷𝑆 𝑔𝑑𝑠 𝐼𝐷𝑆 𝜆𝐼𝐷𝑆
𝑉𝐴 : Early voltage (𝑉𝐴 ∝ 𝐿) ↔ 𝜆: Channel length modulation coefficient (𝜆 ∝ 1/𝐿)
𝑉𝐷𝑆 𝑉𝐷𝑆 /𝐼𝐷𝑆 𝜇𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = 𝐼𝐷𝑆 + = 𝐼𝐷𝑆 1 + = 𝑉 1 + 𝜆𝑉𝐷𝑆
𝑟𝑜 𝑟𝑜 2 𝐿 𝑜𝑣

04: MOSFET DC [Sedra/Smith, 2015] 27

 Channel Length Modulation (CLM)
❑ 𝐿𝑒𝑓𝑓 decreases with 𝑉𝐷𝑆 → Shorter L gives more current
❑ 𝑉𝐴 : Early voltage (𝑉𝐴 ∝ 𝐿)
❑ 𝜆: Channel length modulation coefficient (𝜆 ∝ 1/𝐿)
𝜇𝐶𝑜𝑥 𝑊 2 𝑉𝐴 1
𝐼𝐷 = 𝑉 1 + 𝜆𝑉𝐷𝑆 𝑟𝑜 = =
2 𝐿 𝑜𝑣 𝐼𝐷𝑆 𝜆𝐼𝐷𝑆
❑ 𝑉𝐴 increases with 𝑉𝐷𝑆 : higher 𝑟𝑜 as we go deeper into saturation

VGS>VTH VGD<VTH
G
S D

n+ n+
Leff
p-sub
VDS>Vov
04: MOSFET DC 28
 Regions of Operation Summary
OFF
ON
(Subthreshold)
𝑉𝐺𝑆 > 𝑉𝑇𝐻
𝑉𝐺𝑆 < 𝑉𝑇𝐻

Triode Pinch-Off
(Saturation)
𝑉𝐷𝑆 < 𝑉𝑜𝑣
𝑉𝐷𝑆 ≥ 𝑉𝑜𝑣
Or
Or
𝑉𝐺𝐷 > 𝑉𝑇𝐻
𝑉𝐺𝐷 ≤ 𝑉𝑇𝐻

𝑊 2
𝑉𝐷𝑆 𝜇𝐶𝑜𝑥 𝑊 2
𝐼𝐷 = 𝜇𝐶𝑜𝑥 𝑉 𝑉 − 𝐼𝐷 = 𝑉 1 + 𝜆𝑉𝐷𝑆
𝐿 𝑜𝑣 𝐷𝑆 2 2 𝐿 𝑜𝑣

04: MOSFET DC 29
 Body Effect
❑ 𝑉𝑆𝐵 affects the charge required to invert the channel
▪ Increasing 𝑉𝑆 or decreasing 𝑉𝐵 increases 𝑉𝑇𝐻
𝑉𝑇𝐻 = 𝑉𝑇𝐻0 + 𝛾 2Φ𝐹 + 𝑉𝑆𝐵 − 2Φ𝐹
▪ Φ𝐹 = surface potential at threshold
• Depends on doping level and intrinsic carrier concentration 𝑛𝑖
▪ 𝛾 = body effect coefficient
• Depends on 𝐶𝑜𝑥 and doping
VGS>VTH VGD<VTH
VSB G
B S D

p+ n+ n+
p-sub

VDS>Vov
04: MOSFET DC 30
 CMOS
❑ CMOS = NMOS + PMOS on the same substrate
❑ S/D junction diodes must remain reverse-biased
▪ NMOS bulk connected to most negative potential (ground)
▪ PMOS bulk connected to most positive potential (VDD)

VGS>VTH VGD<VTH |VGD|<|VTH| |VGS|>|VTH|

G G VDD
B S D D S B

p+ n+ n+ p+ p+ n+

VDS>Vov |VDS|>Vov n-well

p-sub

04: MOSFET DC 31
 CMOS
❑ CMOS = NMOS + PMOS on the same substrate
❑ All NFETs share the same substrate
▪ If source is floating then will have body effect
❑ Each PFET can have an independent n-well
▪ Connect body to floating source to avoid body effect
❑ NFET can be placed in a “private” well in twin/triple-well technologies

VGS>VTH VGD<VTH |VGD|<|VTH| |VGS|>|VTH|

G G VDD
B S D D S B

p+ n+ n+ p+ p+ n+

VDS>Vov |VDS|>Vov n-well

p-sub

04: MOSFET DC 32
 CMOS Technology Scaling: Moore’s Law
❑ Min feature size 𝐿𝑚𝑖𝑛 shrinking 30% (≈ 1/ 2) every 2-3 years
▪ Transistor area (and cost) are reduced by a factor of 2
❑ Device scaling brings new challenges in circuit design

04: MOSFET DC [Weste and Harris, 2010] 33

 Short Channel Effects: Velocity Saturation
❑ For deep-submicron MOSFET with short channel length (𝐿 < 0.25𝜇𝑚) the lateral electric
field is very high
𝑉𝐷𝑆
𝐸=
𝐿
❑ @ 𝐸 = 𝐸𝑐𝑟 𝑉𝐷𝑆 = 𝑉𝐷𝑆𝑠𝑎𝑡 the velocity of the carriers saturates
𝑉𝐷𝑆𝑠𝑎𝑡
𝑣𝑠𝑎𝑡 = 𝜇𝐸𝑐𝑟 = 𝜇 ≈ 107 𝑐𝑚/𝑠
𝐿

04: MOSFET DC [Sedra/Smith, 2015] 34

 Velocity Saturation: IV Characteristics
❑ Long channel: Triode region
𝑊 𝑉𝐷𝑆
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 − ⋅ 𝑉𝐷𝑆
𝐿 2
❑ Velocity sat happens before pinch-off if 𝑉𝐷𝑆𝑠𝑎𝑡 < 𝑉𝑜𝑣
𝑉𝐷𝑆 𝑉𝐷𝑆𝑠𝑎𝑡
▪ Replace 𝑉𝐷𝑆 with 𝑉𝐷𝑆𝑠𝑎𝑡 and 𝑣 = 𝜇𝑛 with 𝑣𝑠𝑎𝑡 = 𝜇𝑛
𝐿 𝐿
𝑊 𝑉𝐷𝑆𝑠𝑎𝑡 𝑉𝐷𝑆𝑠𝑎𝑡
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 ⋅ 𝑉𝑜𝑣 − ⋅ 𝑉𝐷𝑆𝑠𝑎𝑡 = 𝐶𝑜𝑥 𝑊𝑣𝑠𝑎𝑡 ⋅ 𝑉𝑜𝑣 −
𝐿 2 2
▪ Including channel length modulation effect (the physical reason is different, but the
effect on 𝐼𝐷 is the same)
𝑉𝐷𝑆𝑠𝑎𝑡
𝐼𝐷 = 𝐶𝑜𝑥 𝑊𝑣𝑠𝑎𝑡 ⋅ 𝑉𝑜𝑣 − 1 + 𝜆𝑉𝐷𝑆
2
▪ (1) Current independent of 𝐿 and (2) linear dependence on 𝑉𝑜𝑣
04: MOSFET DC 35
 Velocity Saturation: IV Characteristics
❑ Velocity sat happens before pinch-off if 𝑉𝐷𝑆𝑠𝑎𝑡 < 𝑉𝑜𝑣
𝑉𝐷𝑆𝑠𝑎𝑡
𝐼𝐷 = 𝐶𝑜𝑥 𝑊𝑣𝑠𝑎𝑡 ⋅ 𝑉𝑜𝑣 − 1 + 𝜆𝑉𝐷𝑆
2

04: MOSFET DC [Sedra/Smith, 2015] 36

 Velocity Saturation: IV Characteristics
❑ Velocity sat happens before pinch-off if 𝑉𝐷𝑆𝑠𝑎𝑡 < 𝑉𝑜𝑣
𝑉𝐷𝑆𝑠𝑎𝑡
𝐼𝐷 = 𝐶𝑜𝑥 𝑊𝑣𝑠𝑎𝑡 ⋅ 𝑉𝑜𝑣 − 1 + 𝜆𝑉𝐷𝑆
2

04: MOSFET DC [Sedra/Smith, 2015] 37

 Velocity Saturation: IV Characteristics
❑ Velocity sat happens before pinch-off if 𝑉𝐷𝑆𝑠𝑎𝑡 < 𝑉𝑜𝑣
𝑉𝐷𝑆𝑠𝑎𝑡
𝐼𝐷 = 𝐶𝑜𝑥 𝑊𝑣𝑠𝑎𝑡 ⋅ 𝑉𝑜𝑣 − 1 + 𝜆𝑉𝐷𝑆
2

04: MOSFET DC [Sedra/Smith, 2015] 38

 Short Channel Effects: Mobility Degradation
❑ Vertical electric field: 𝐸𝑣𝑒𝑟𝑡 = 𝑉𝐺𝑆 /𝑡𝑜𝑥
▪ Attracts carriers into channel
▪ Long channel: 𝑄𝑐ℎ𝑎𝑛𝑛𝑒𝑙 ∝ 𝐸𝑣𝑒𝑟𝑡
❑ At high vertical field strengths (𝑉𝐺𝑆 /𝑡𝑜𝑥 )
▪ The carriers scatter off the oxide interface more often
▪ Scattering slows carrier progress
▪ Leads to less current than expected at high 𝑉𝐺𝑆
❑ Mobility degradation can be modeled by replacing 𝜇 with a smaller 𝜇𝑒𝑓𝑓 that is a function
of 𝑉𝐺𝑆

04: MOSFET DC 39
 Short Channel Effects: DIBL
❑ DIBL: Drain-Induced Barrier Lowering
❑ Electric field from drain affects threshold voltage
▪ More pronounced in short channel devices
′
𝑉𝑇𝐻 = 𝑉𝑇𝐻 − 𝜂𝑉𝐷𝑆
▪ 𝜂: DIBL coefficient ~ 100𝑚𝑉/𝑉
❑ High drain voltage causes current to increase (similar to channel length modulation)
❑ Gate is losing control over the channel

04: MOSFET DC [Tsu‐Jae King Liu, Berkeley, 2012] 40

 Short-Channel MOSFET I-V Ccs
❑ 65 nm IBM process, VDD = 1.0 V

04: MOSFET DC [Weste & Harris, 2010] 41

 Why Do We Still Learn Square-Law?
❑ For digital and RF, use min 𝐿
▪ You care most about speed and power
❑ For analog, we use relatively long 𝐿
▪ We care about matching, gain, and low-frequency noise
❑ For digital 𝑉𝑜𝑣 is large = 𝑉𝐷𝐷 – 𝑉𝑇𝐻
▪ Short channel effects (e.g., velocity sat.) are more pronounced
❑ For analog 𝑉𝑜𝑣 is relatively low
▪ Short channel effects (e.g., velocity sat.) are less pronounced
❑ Simple model provides a great deal of intuition that is necessary in analog design
▪ We must simulate the circuit to get more accurate results

04: MOSFET DC 42
 Is the Square-Law Still Valid?
❑ Valid “relatively” if
▪ Relatively long channel length
▪ Strong inversion, but not too strong (e.g., 𝑉𝑜𝑣 ≈ 100 − 300𝑚𝑉)
• For small and negative 𝑉𝑜𝑣 : moderate and weak inversion (subthreshold operation)
– ID-VGS relation gradually becomes exponential
• For large 𝑉𝑜𝑣 : velocity saturation happens before pinch-off
– ID-VGS relation becomes linear
❑ If the above conditions are not valid
▪ Use design charts or look-up tables, e.g., gm/ID design methodology (to be explained
later)
❑ Actually, better to use gm/ID methodology even if the above conditions are valid!

04: MOSFET DC 43
 FinFET
❑ Planar CMOS cannot be scaled below 20nm due to excess leakage current and severe short
channel effects
❑ FinFET: gate has better control on the channel
▪ Intel’s version is called trigate FET
▪ Generally: multigate transistor
❑ In the future: Gate-all-around

04: MOSFET DC [Weste & Harris, 2010] 44

 Thank you!

04: MOSFET DC 45
 References
❑ A. Sedra and K. Smith, “Microelectronic Circuits,” Oxford University Press, 7th ed., 2015.
❑ B. Razavi, “Fundamentals of Microelectronics,” Wiley, 2nd ed., 2014.
❑ B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2nd ed., 2017.
❑ N. Weste and D. Harris, “CMOS VLSI Design,” Pearson, 4th ed., 2010.

04: MOSFET DC 46