2 49 PDF

INDEX
(1) Assignment 1 :-
(a) Introduction to VHDL
(2) Assignment 2 :-
(a) AND gate
(b) OR gate
(c) NOT gate
(d) NAND gate
(e) NOR gate
(f) XOR gate
(3) Assignment 3 :-
(a) Half Adder
(b) Full Adder
(4) Assignment 4 :-
(a) Half Subtractor
(b) Full Subtractor
(5) Assignment 5 :-
(a) 2x4 Decoder
(b) 4x1 Multiplexer (MUX)
(6) Assignment 6 :-
(a) 4-bit Binary Adder
(7) Assignment 7 :-
(a) 4-bit Composite Unit
(8) Assignment 8 :-
(a) 4-bit Arithmetic Logic Unit (ALU)
(9) Assignment 9 :-
(a) D Flip Flop
(10) Assignment 10 :-
(a) 4-bit Register
INTRODUCTION TO VHDL
VHDL is a programming language that has been designed and optimized for describing the
behaviour of digital circuits and systems.
VHDL has many features appropriate for describing the behaviour of electronic components
ranging from simple logic gates to complete microprocessors and custom chips. Features of
VHDL allow electrical aspects of circuit behaviour to be precisely described. The resulting
VHDL simulation models can then be used as building blocks in larger circuits for the
purpose of simulation.
Just as high-level programming languages allow complex design concepts to be expressed

as computer programs, VHDL allows the behaviour of complex electronic circuits to be
captured into a design system for automatic circuit synthesis or for system simulation.
VHDL provides features allowing concurrent events to be described. This is important
because the hardware being described using VHDL is inherently concurrent in its operation.
One of the most important aspects of VHDL is its ability to capture the performance
specification for a circuit, in a form commonly referred to as a test bench. Test benches are
VHDL descriptions of circuit stimulus and corresponding expected outputs that verify the
behaviour of a circuit over time. Test benches should be an integral part of any VHDL
project, and should be created in parallel with other descriptions of the circuit.
AND GATE
The AND gate is a basic digital logic gate that implements AND operation between two or
more binary bits.
Logic diagram Truth table
A B C
0 0 0
0 1 0
1 0 0
1 1 1
Code
testbench.vhd design.vhd
-- AND gate testbench -- Basic AND gate

library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
entity testbench is entity and_gate is

-- empty port(
end testbench; a: in std_logic;
b: in std_logic;
architecture test_arch of testbench is c: out std_logic);
end and_gate;
component and_gate is
port( architecture and_gate_arch of and_gate is
a: in std_logic; begin
b: in std_logic; process(a,b) is
c: out std_logic); begin
end component; c <= a and b;
end process;
signal a_in, b_in, c_out: std_logic; end and_gate_arch;
begin
DUT: and_gate port map(a_in, b_in, c_out);
process is
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(c_out='0') report "Fail 0/0" severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';
assert(false) report "Test done" severity note;

wait;
end process;
end test_arch;
OUTPUT:
OR GATE
The OR gate is a basic digital logic gate that implements OR operation between two or more
binary bits.
A B C
0 0 0
0 1 1
1 0 1
1 1 1
Code
-- OR gate testbench -- Basic OR gate

entity testbench is entity or_gate is

-- empty port(
b: in std_logic;
end or_gate;
component or_gate is
port( architecture or_gate_arch of or_gate is
end component; c <= a or b;
end process;
signal a_in, b_in, c_out: std_logic; end or_gate_arch;
begin
DUT: or_gate port map(a_in, b_in, c_out);
process is
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
NOT GATE
The NOT gate is a basic digital logic gate that implements NOT operation or complement
operation on a single binary bit.
A B
0 1
1 0
Code
-- NOT gate testbench -- Basic NOT gate

entity testbench is entity not_gate is

-- empty port(
b: out std_logic);
architecture test_arch of testbench is end not_gate;
component not_gate is architecture not_gate_arch of not_gate is

port( begin
a: in std_logic; process(a) is
b: out std_logic); begin
end component; b <= not a;
end process;
signal a_in, b_out: std_logic; end not_gate_arch;
begin
DUT: not_gate port map(a_in, b_out);
process is
begin
a_in <= '0';
wait for 1 ns;
assert(b_out='1') report "Fail 0" severity error;
a_in <= '1';

wait for 1 ns;
assert(b_out='0') report "Fail 1" severity error;
a_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
NAND GATE
The NAND gate is a basic digital logic gate that implements NAND operation or NOT AND
operation between two or more binary bits.
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Code
-- NAND gate testbench -- Basic NAND gate

entity testbench is entity nand_gate is

-- empty port(
b: in std_logic;
end nand_gate;
component nand_gate is
port( architecture nand_gate_arch of nand_gate is
end component; c <= a nand b;
end process;
signal a_in, b_in, c_out: std_logic; end nand_gate_arch;
begin
DUT: nand_gate port map(a_in, b_in, c_out);
process is
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
NOR GATE
The NOR gate is a basic digital logic gate that implements NOR operation or NOT OR
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Code
-- NOR gate testbench -- Basic NOR gate

entity testbench is entity nor_gate is

-- empty port(
b: in std_logic;
end nor_gate;
component nor_gate is
port( architecture nor_gate_arch of nor_gate is
end component; c <= a nor b;
end process;
signal a_in, b_in, c_out: std_logic; end nor_gate_arch;
begin
DUT: nor_gate port map(a_in, b_in, c_out);
process is
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
XOR GATE
The XOR gate is a basic digital logic gate that implements XOR operation or Exclusive OR
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Code
-- XOR gate testbench -- Basic XOR gate

entity testbench is entity xor_gate is

-- empty port(
b: in std_logic;
end xor_gate;
component xor_gate is
port( architecture xor_gate_arch of xor_gate is
end component; c <= a xor b;
end process;
signal a_in, b_in, c_out: std_logic; end xor_gate_arch;
begin
DUT: xor_gate port map(a_in, b_in, c_out);
process is
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
HALF ADDER
The half adder is a digital logic circuit which performs addition of two binary bits and
produces a sum and a carry.
A B Sum Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logical expression
B = A XOR B Cout = AB = A AND B
Code
-- Testbench for half adder -- Simple half adder design

entity testbench is entity half_adder is

-- empty port(
b: in std_logic;
architecture test_arch of testbench is sum: out std_logic;
cout: out std_logic);
component half_adder is end half_adder;
port(
a: in std_logic; architecture half_adder_arch of half_adder is
b: in std_logic; begin
sum: out std_logic; process(a, b) is
cout: out std_logic); begin
end component; sum <= a xor b;
cout <= a and b;
signal a_in, b_in, s_out, c_out: std_logic; end process;
end half_adder_arch;
begin
DUT: half_adder port map(a_in, b_in, s_out, c_out);
process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(s_out='0') report "Fail 0/0" severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
a_in <= '1';

b_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';
assert false report "Test done." severity note;

wait;
end process;
end test_arch;
OUTPUT:
FULL ADDER
The full adder is a digital logic circuit which performs addition of three binary bits and
produces a sum and a carry.
A B Cin Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logical expression
Sum =
B) + C(A
=A B C = BC + AC + AB
= A XOR B XOR C = AB + AC + BC
= (A AND B) OR (A AND C) OR (B AND C)
Code
-- Testbench for full adder -- Simple full adder design

entity testbench is entity full_adder is

-- empty port(
b: in std_logic;
architecture test_arch of testbench is cin: in std_logic;
sum: out std_logic;
component full_adder is cout: out std_logic);
port( end full_adder;
a: in std_logic;
b: in std_logic; architecture full_adder_arch of full_adder is
cin: in std_logic; begin
sum: out std_logic; process(a, b, cin) is
cout: out std_logic); begin
end component; sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and
signal a_in, b_in, c_in, s_out, c_out: std_logic; cin);
end process;
begin end full_adder_arch;
DUT: full_adder port map(a_in, b_in, c_in, s_out,

c_out);
process
begin
a_in <= '0';
b_in <= '0';
c_in <= '0';
wait for 1 ns;
assert(s_out='0') report "Fail 0/0/0" severity error;
assert(c_out='0') report "Fail 0/0/0" severity error;
a_in <= '0';

b_in <= '0';
c_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
c_in <= '0';
wait for 1 ns;
a_in <= '0';

b_in <= '1';
c_in <= '1';
wait for 1 ns;
a_in <= '1';

b_in <= '0';
c_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '0';
c_in <= '1';
wait for 1 ns;
a_in <= '1';
b_in <= '1';
c_in <= '0';
wait for 1 ns;
a_in <= '1';

b_in <= '1';
c_in <= '1';
wait for 1 ns;
a_in <= '0';

b_in <= '0';
c_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
HALF SUBTRACTOR
The half subtractor is a digital logic circuit which performs subtraction of two binary bits
and produces a difference and a borrow.
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Logical expression
B = A XOR B
Code
-- Testbench for half subtractor -- Simple half subtractor design

entity testbench is entity half_subtractor is

-- empty port(
b: in std_logic;
architecture test_arch of testbench is diff: out std_logic;
borrow: out std_logic);
component half_subtractor is end half_subtractor;
port(
a: in std_logic; architecture half_subtractor_arch of
b: in std_logic; half_subtractor is
diff: out std_logic; begin
borrow: out std_logic); process(a, b) is
end component; begin
diff <= a xor b;
signal a_in, b_in, diff_out, borrow_out: std_logic; borrow <= (not a) and b;
end process;
begin end half_subtractor_arch;
DUT: half_subtractor port map(a_in, b_in, diff_out,

borrow_out);
process
begin
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(diff_out='0') report "Fail 0/0" severity error;
assert(borrow_out='0') report "Fail 0/0" severity
error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '0';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '1';
wait for 1 ns;
error;
a_in <= '0';

b_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
FULL SUBTRACTOR
The full subtractor is a digital logic circuit which performs subtraction of three binary bits
and produces a difference and a borrow.
A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logical expression
ABC
B) + C(A
=A B C
= A XOR B XOR C
= ((NOT A) AND B) OR ((NOT A) AND C)
OR (B AND C)
Code
-- Testbench for full subtractor -- Simple full subtractor design

entity testbench is entity full_subtractor is

-- empty port(
b: in std_logic;
architecture test_arch of testbench is c: in std_logic;
diff: out std_logic;
component full_subtractor is borrow: out std_logic);
port( end full_subtractor;
a: in std_logic;
b: in std_logic; architecture full_subtractor_arch of
c: in std_logic; full_subtractor is
diff: out std_logic; begin
borrow: out std_logic); process(a, b, c) is
diff <= a xor b xor c;
signal a_in, b_in, c_in, diff_out, borrow_out: std_logic; borrow <= ((not a) and b) or ((not a)
and c) or (b and c);
begin end process;
end full_subtractor_arch;
DUT: full_subtractor port map(a_in, b_in, c_in, diff_out,
borrow_out);
process
begin
a_in <= '0';
b_in <= '0';
c_in <= '0';
wait for 1 ns;
assert(diff_out='0') report "Fail 0/0/0" severity error;
assert(borrow_out='0') report "Fail 0/0/0" severity
error;
a_in <= '0';

b_in <= '0';
c_in <= '1';
wait for 1 ns;
error;
a_in <= '0';

b_in <= '1';
c_in <= '0';
wait for 1 ns;
error;
a_in <= '0';

b_in <= '1';
c_in <= '1';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '0';
c_in <= '0';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '0';
c_in <= '1';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '1';
c_in <= '0';
wait for 1 ns;
error;
a_in <= '1';

b_in <= '1';
c_in <= '1';
wait for 1 ns;
error;
a_in <= '0';

b_in <= '0';
c_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
DECODER (2 x 4)
A decoder is a combinational logic circuit with n inputs and 2n outputs. A single output line
is turned on based on the given input. A 2x4 decoder decodes 2 inputs into one of the 4
output lines.
s0 s1 d0 d1 d2 d3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Logical expression
d3 = (s0)(s1) = s0 AND s1
Code
-- Testbench for 2x4 decoder -- Simple 2x4 decoder design

entity testbench is entity decoder is

-- empty port(
end testbench; s0: in std_logic;
s1: in std_logic;
architecture test_arch of testbench is d0: out std_logic;
d1: out std_logic;
component decoder is d2: out std_logic;
port( d3: out std_logic);
s0: in std_logic; end decoder;
s1: in std_logic;
d0: out std_logic; architecture decoder_arch of decoder is
d1: out std_logic; begin
d2: out std_logic; process(s0, s1) is
d3: out std_logic); begin
end component; d0 <= (not s0) and (not s1);
d1 <= (not s0) and s1;
signal s0_in, s1_in, d0_out, d1_out, d2_out, d3_out: d2 <= s0 and (not s1);
std_logic; d3 <= s0 and s1;
end process;
begin end decoder_arch;
DUT: decoder port map(s0_in, s1_in, d0_out,
d1_out, d2_out, d3_out);
process
begin
s0_in <= '0';
s1_in <= '0';
wait for 1 ns;
assert(d0_out='1') report "Fail 0/0" severity error;
s0_in <= '0';

s1_in <= '1';
wait for 1 ns;
s0_in <= '1';

s1_in <= '0';
wait for 1 ns;
s0_in <= '1';

s1_in <= '1';
wait for 1 ns;
s0_in <= '0';

s1_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
MULTIPLEXER (4 x 1)
A multiplexer is a combinational logic circuit with n select inputs, 2n data inputs and 1 data
output. A single data input is selected based on the select inputs and is passed to the data
output. A 4x1 multiplexer selects one of the 4 data inputs and passes it to the 1 data output
according to the 2 select lines.
s0 s1 output
0 0 i0
0 1 i1
1 0 i2
1 1 i3
Logical expression
output =
= ((NOT s0) AND (NOT s1) AND i0) OR ((NOT s0) AND s1 AND i1) OR
(s0 AND (NOT s1) AND i2) OR (s0 AND s1 AND i3)
Code
-- Testbench for 4x1 mux -- Simple 4x1 mux design

entity testbench is entity mux4to1 is

-- empty port(
end testbench; s0: in std_logic;
s1: in std_logic;
architecture test_arch of testbench is i0: in std_logic;
i1: in std_logic;
component mux4to1 is i2: in std_logic;
port( i3: in std_logic;
s0: in std_logic; output: out std_logic);
s1: in std_logic; end mux4to1;
i0: in std_logic;
i1: in std_logic; architecture mux_arch of mux4to1 is
i2: in std_logic; begin
i3: in std_logic; process(s0, s1, i0, i1, i2, i3) is
output: out std_logic); begin
end component; output <= ((not s0) and (not s1) and i0) or
((not s0) and s1 and i1) or (s0 and (not s1) and
signal s0_in, s1_in, i0_in, i1_in, i2_in, i3_in, i2) or (s0 and s1 and i3);
output_out: std_logic; end process;
end mux_arch;
begin
DUT: mux4to1 port map(s0_in, s1_in, i0_in, i1_in,

i2_in, i3_in, output_out);
process
begin
s0_in <= '0';

s1_in <= '0';
i0_in <= '0';
i1_in <= '1';
i2_in <= '1';
i3_in <= '1';
wait for 1 ns;
assert(output_out='0') report "Fail 0/0" severity
error;
i0_in <= '1';
i1_in <= '0';
i2_in <= '0';
i3_in <= '0';
wait for 1 ns;
error;
s0_in <= '0';

s1_in <= '1';
i0_in <= '1';
i1_in <= '0';
i2_in <= '1';
i3_in <= '1';
wait for 1 ns;
error;
i0_in <= '0';
i1_in <= '1';
i2_in <= '0';
i3_in <= '0';
wait for 1 ns;
error;
s0_in <= '1';

s1_in <= '0';
i0_in <= '1';
i1_in <= '1';
i2_in <= '0';
i3_in <= '1';
wait for 1 ns;
error;
i0_in <= '0';
i1_in <= '0';
i2_in <= '1';
i3_in <= '0';
wait for 1 ns;
error;
s0_in <= '1';

s1_in <= '1';
i0_in <= '1';
i1_in <= '1';
i2_in <= '1';
i3_in <= '0';
wait for 1 ns;
error;
i0_in <= '0';
i1_in <= '0';
i2_in <= '0';
i3_in <= '1';
wait for 1 ns;
error;
s0_in <= '0';

s1_in <= '0';
i0_in <= '0';
i1_in <= '0';
i2_in <= '0';
i3_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
4-BIT BINARY ADDER
A 4-bit binary adder is an adder which performs addition of 2 4-bit binary numbers and
produces a 4-bit sum and 1-bit carry.
Logic diagram
Block diagram
Code
-- Testbench for 4-bit adder -- Design for 4-bit adder


--empty port(
b: in std_logic;
sum: out std_logic;
component adder_4_bit is cout: out std_logic);
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0); architecture full_adder_arch of full_adder is
sum: out std_logic_vector(3 downto 0); begin
carry: out std_logic); process(a, b, cin) is
sum <= a xor b xor cin;
signal a_vector, b_vector, sum_vector: cout <= (a and b) or (a and cin) or (b and cin);
std_logic_vector(3 downto 0); end process;
signal cout: std_logic; end full_adder_arch;
begin ----------------------------------------------------------------
DUT: adder_4_bit port map(a_vector, b_vector,
sum_vector, cout); library IEEE;
use IEEE.std_logic_1164.all;
process
begin entity adder_4_bit is
port(
a_vector <= "1001"; a: in std_logic_vector(3 downto 0);
b_vector <= "0110"; b: in std_logic_vector(3 downto 0);
wait for 1 ns; sum: out std_logic_vector(3 downto 0);
assert(sum_vector="1111") report "Fail" carry: out std_logic);
severity error; end adder_4_bit;
assert(cout='0') report "Fail" severity error;
architecture adder_4_bit_arch of adder_4_bit is
a_vector <= "0000";
b_vector <= "0000"; component full_adder is
assert false report "Test done" severity note; port(
wait; a: in std_logic;
end process; b: in std_logic;
end test_arch; cin: in std_logic;
sum: out std_logic;
cout: out std_logic);
end component;
signal ctemp: std_logic_vector(2 downto 0);
begin
fa0: full_adder port map(a(0), b(0), '0', sum(0),

ctemp(0));
fa1: full_adder port map(a(1), b(1), ctemp(0),
sum(1), ctemp(1));
sum(2), ctemp(2));
sum(3), carry);
end adder_4_bit_arch;
OUTPUT:
4-BIT COMPOSITE UNIT
A 4-bit composite unit is a digital logic circuit which performs either addition or subtraction
of 2 4-bit binary numbers depending on a particular input and produces a 4-bit sum or
difference and 1-bit carry or borrow.
Logic diagram
Block diagram Truth table
M OUTPUT
0 A+B
1 A-B
Code
-- Testbench for 4-bit composite unit -- Design for 4-bit composite unit

--empty port(
b: in std_logic;
sum: out std_logic;
component composite_addsub_4_bit is cout: out std_logic);
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0); architecture full_adder_arch of full_adder is
m: in std_logic; begin
sum: out std_logic_vector(3 downto 0); process(a, b, cin) is
carry: out std_logic); begin
end component; sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
signal a_vector, b_vector, sum_vector: end process;
std_logic_vector(3 downto 0); end full_adder_arch;
signal m_in, cout: std_logic;
----------------------------------------------------------------
begin
DUT: composite_addsub_4_bit port library IEEE;
map(a_vector, b_vector, m_in, sum_vector, cout); use IEEE.std_logic_1164.all;
process entity composite_addsub_4_bit is

begin port(
m_in <= '0'; a: in std_logic_vector(3 downto 0);
a_vector <= "1001"; b: in std_logic_vector(3 downto 0);
b_vector <= "0110"; m: in std_logic;
wait for 1 ns; sum: out std_logic_vector(3 downto 0);
assert(sum_vector="1111") report "Fail" carry: out std_logic);
severity error; end composite_addsub_4_bit;
assert(cout='0') report "Fail" severity error;
architecture composite_4_bit_arch of
m_in <= '1'; composite_addsub_4_bit is
a_vector <= "1001";
b_vector <= "0011"; component full_adder is
wait for 1 ns; port(
assert(sum_vector="0110") report "Fail" a: in std_logic;
severity error; b: in std_logic;
assert(cout='1') report "Fail" severity error; cin: in std_logic;
sum: out std_logic;
m_in <= '0'; cout: out std_logic);
a_vector <= "0000"; end component;
b_vector <= "0000";
assert false report "Test done" severity note; signal ctemp: std_logic_vector(2 downto 0);
wait;
end process; begin
end test_arch; fa0: full_adder port map(a(0), (b(0) xor m), m,
sum(0), ctemp(0));
fa1: full_adder port map(a(1), (b(1) xor m),
ctemp(0), sum(1), ctemp(1));
ctemp(1), sum(2), ctemp(2));
ctemp(2), sum(3), carry);
end composite_4_bit_arch;
OUTPUT:
4-BIT ARITHMETIC LOGIC UNIT (ALU)
A 4-bit ALU is a digital logic circuit which performs different types of arithmetic operations
between either 1 or 2 4-bit binary numbers depending on particular select inputs and
produces a 4-bit sum output and 1-bit carry output. The following ALU is designed to
perform five different operations. They are :-
(a) Addition (ADD) (b) Subtraction (SUB) (c) Increment (INC)
(d) Decrement (DEC) (e) Transfer (TRS)
Logic diagram
Block diagram
Truth table
select0 select1 c_in Operation name Operation Operation
code result
0 0 0 Addition ADD A+B
0 0 1 Addition with carry ADC A+B+1
0 1 0 Subtraction with carry SUC
0 1 1 Subtraction SUB A B
1 0 0 Transfer TRS A
1 0 1 Increment INC A+1
1 1 0 Decrement DEC A 1
1 1 1 Transfer TRS A
Code
--Testbench for 4-bit ALU -- 4-bit ALU design with addition(ADD),

library IEEE; subtraction(SUB), increment(INC),
use IEEE.std_logic_1164.all; decrement(DEC), transfer(TRS) operations
entity testbench is --Design of 4x1 MUX

--empty library IEEE;
end testbench; use IEEE.std_logic_1164.all;
architecture test_arch of testbench is entity mux4to1 is

port(
component alu_4_bit is s0: in std_logic;
port( s1: in std_logic;
a: in std_logic_vector(3 downto 0); i0: in std_logic;
b: in std_logic_vector(3 downto 0); i1: in std_logic;
c_in: in std_logic; i2: in std_logic;
select0: in std_logic; i3: in std_logic;
select1: in std_logic; output: out std_logic);
sum: out std_logic_vector(3 downto 0); end mux4to1;
carry: out std_logic);
end component; architecture mux4to1_arch of mux4to1 is
begin
signal a_vector, b_vector, sum_vector: process(s0, s1, i0, i1, i2, i3) is
std_logic_vector(3 downto 0); begin
signal cin, cout, s0_in, s1_in: std_logic; output <= ((not s0) and (not s1) and i0) or
((not s0) and s1 and i1) or (s0 and (not s1) and i2)
begin or (s0 and s1 and i3);
DUT: alu_4_bit port map(a_vector, b_vector, cin, end process;
s0_in, s1_in, sum_vector, cout); end mux4to1_arch;
process --------------------------------------------------------------------
begin
--ADD --Design of full adder
s0_in <= '0'; library IEEE;
s1_in <= '0'; use IEEE.std_logic_1164.all;
cin <= '0';
a_vector <= "1001"; entity full_adder is
b_vector <= "0110"; port(
wait for 1 ns; a: in std_logic;
assert(sum_vector="1111") report "Fail ADD" b: in std_logic;
severity error; cin: in std_logic;
assert(cout='0') report "Fail ADD" severity sum: out std_logic;
error; cout: out std_logic);
end full_adder;
--SUB
s0_in <= '0'; architecture full_adder_arch of full_adder is
s1_in <= '1'; begin
cin <= '1'; process(a, b, cin) is
a_vector <= "1010"; begin
b_vector <= "0111"; sum <= a xor b xor cin;
wait for 1 ns; cout <= (a and b) or (a and cin) or (b and cin);
assert(sum_vector="0011") report "Fail SUB" end process;
severity error; end full_adder_arch;
assert(cout='1') report "Fail SUB" severity
error; --------------------------------------------------------------------
--TRS --Design of 4-bit ALU

s0_in <= '1'; library IEEE;
s1_in <= '0'; use IEEE.std_logic_1164.all;
cin <= '0';
a_vector <= "1011"; entity alu_4_bit is
wait for 1 ns; port(
assert(sum_vector="1011") report "Fail TRS" a: in std_logic_vector(3 downto 0);
severity error; b: in std_logic_vector(3 downto 0);
assert(cout='0') report "Fail TRS" severity c_in: in std_logic;
error; select0: in std_logic;
select1: in std_logic;
--INC sum: out std_logic_vector(3 downto 0);
s0_in <= '1'; carry: out std_logic);
s1_in <= '0'; end alu_4_bit;
cin <= '1';
a_vector <= "0101"; architecture alu_4bit_arch of alu_4_bit is
wait for 1 ns;
assert(sum_vector="0110") report "Fail INC" component mux4to1 is
severity error; port(
assert(cout='0') report "Fail INC" severity s0: in std_logic;
error; s1: in std_logic;
i0: in std_logic;
--DEC i1: in std_logic;
s0_in <= '1'; i2: in std_logic;
s1_in <= '1'; i3: in std_logic;
cin <= '0'; output: out std_logic);
a_vector <= "1001"; end component;
wait for 1 ns;
assert(sum_vector="1000") report "Fail DEC" component full_adder is
severity error; port(
assert(cout='1') report "Fail DEC" severity a: in std_logic;
error; b: in std_logic;
cin: in std_logic;
--TRS sum: out std_logic;
s0_in <= '1'; cout: out std_logic);
s1_in <= '1'; end component;
cin <= '1';
a_vector <= "0111"; signal temp_c: std_logic_vector(2 downto 0);
wait for 1 ns; signal temp_mux: std_logic_vector(3 downto 0);
assert(sum_vector="0111") report "Fail TRS"
severity error; begin
assert(cout='1') report "Fail TRS" severity
error; mux0: mux4to1 port map(select0, select1, b(0),
(not b(0)), '0', '1', temp_mux(0));
--Clear mux1: mux4to1 port map(select0, select1, b(1),
s0_in <= '0'; (not b(1)), '0', '1', temp_mux(1));
s1_in <= '0'; mux2: mux4to1 port map(select0, select1, b(2),
cin <= '0'; (not b(2)), '0', '1', temp_mux(2));
a_vector <= "0000"; mux3: mux4to1 port map(select0, select1, b(3),
b_vector <= "0000"; (not b(3)), '0', '1', temp_mux(3));
assert false report "Test done" severity note;
wait; fa0: full_adder port map(a(0), temp_mux(0),
end process; c_in, sum(0), temp_c(0));
end test_arch; fa1: full_adder port map(a(1), temp_mux(1),
temp_c(0), sum(1), temp_c(1));
fa2: full_adder port map(a(2), temp_mux(2),
temp_c(1), sum(2), temp_c(2));
fa3: full_adder port map(a(3), temp_mux(3),
temp_c(2), sum(3), carry);
end alu_4bit_arch;
OUTPUT:
D-FLIP FLOP
A D-Flip Flop or a Data Flip Flop is a sequential circuit which has one data input D and one
CLK inputs and the previous outputs.

Logic diagram
Block diagram Truth table

CLK Q(t) D Q(t+1)
0 0 x 0
0 1 x 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Code
-- Testbench for D flip flop -- D flip flop design

entity testbench is entity d_flipflop is

-- empty port(
end testbench; d: in std_logic;
clk: in std_logic;
architecture test_arch of testbench is q: out std_logic;
qc: out std_logic);
component d_flipflop is end d_flipflop;
port(
d: in std_logic; architecture d_flipflop_arch of d_flipflop is
clk: in std_logic; begin
q: out std_logic; process(d, clk) is
qc: out std_logic); begin
end component; if(clk='1')
then
signal d_in, clk_in, q_out, qc_out: std_logic; q <= d;
qc <= not d;
begin end if;
end process;
DUT: d_flipflop port map(d_in, clk_in, q_out, end d_flipflop_arch;
qc_out);
process
begin
clk_in <= '1';
d_in <= '0';
wait for 1 ns;
assert(q_out='0') report "Fail 1/0" severity
error;
assert(qc_out='1') report "Fail 1/0" severity
error;
clk_in <= '1';

d_in <= '1';
wait for 1 ns;
error;
error;
clk_in <= '0';

d_in <= '0';
wait for 1 ns;
error;
error;
clk_in <= '0';

d_in <= '1';
wait for 1 ns;
error;
error;
-- Clear inputs
d_in <= '0';
clk_in <= '0';

wait;
end process;
end test_arch;
OUTPUT:
4-BIT REGISTER
A 4-bit register is a sequential circuit made of 4 individual D-flip flops. It has a 1-bit clock
input CLK and a 4-bit data input D and produces two 4-
the clock input is 1, the value at the data input is stored into the flip flops for future use.
Logic diagram
Truth table
CLK Q(t+1)
0 Q(t)
1 D
Code
-- Testbench for 4 bit register -- 4 bit register design

library IEEE;
use IEEE.std_logic_1164.all; -- D flip flop design
library IEEE;
entity testbench is use IEEE.std_logic_1164.all;
-- empty
end testbench; entity d_flipflop is
port(
architecture test_arch of testbench is d: in std_logic;
clk: in std_logic;
component register_4_bit is q: out std_logic;
port( qc: out std_logic);
d_in: in std_logic_vector(3 downto 0); end d_flipflop;
clk_in: in std_logic;
q_out: out std_logic_vector(3 downto 0); architecture d_flipflop_arch of d_flipflop is
qc_out: out std_logic_vector(3 downto 0)); begin
end component; process(d, clk) is
begin
signal d, q, qc: std_logic_vector(3 downto 0); if(clk='1')
signal clk: std_logic; then
q <= d;
begin qc <= not d;
end if;
DUT: register_4_bit port map(d, clk, q, qc); end process;
end d_flipflop_arch;
process
begin --------------------------------------------------------------------
clk <= '1';
d <= "1101"; library IEEE;
wait for 1 ns; use IEEE.std_logic_1164.all;
assert(q="1101") report "Fail 1" severity error;
assert(qc="0010") report "Fail 1" severity entity register_4_bit is
error; port(
d_in: in std_logic_vector(3 downto 0);
clk <= '0'; clk_in: in std_logic;
d <= "1001"; q_out: out std_logic_vector(3 downto 0);
wait for 1 ns; qc_out: out std_logic_vector(3 downto 0));
assert(q="1101") report "Fail 0" severity error; end register_4_bit;
assert(qc="0010") report "Fail 0" severity
error; architecture register_arch of register_4_bit is
-- Clear inputs component d_flipflop is

d <= "0000"; port(
clk <= '0'; d: in std_logic;
clk: in std_logic;
assert false report "Test done." severity note; q: out std_logic;
wait; qc: out std_logic);
end process; end component;
end test_arch;
begin
df0: d_flipflop port map(d_in(0), clk_in,

q_out(0), qc_out(0));
end register_arch;
OUTPUT:

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INDEX

Just as high-level programming languages allow complex design concepts to be expressed

-- AND gate testbench -- Basic AND gate

entity testbench is entity and_gate is

a_in <= '0';

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- OR gate testbench -- Basic OR gate

entity testbench is entity or_gate is

a_in <= '0';

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- NOT gate testbench -- Basic NOT gate

entity testbench is entity not_gate is

component not_gate is architecture not_gate_arch of not_gate is

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- NAND gate testbench -- Basic NAND gate

entity testbench is entity nand_gate is

a_in <= '0';

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- NOR gate testbench -- Basic NOR gate

entity testbench is entity nor_gate is

a_in <= '0';

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- XOR gate testbench -- Basic XOR gate

entity testbench is entity xor_gate is

a_in <= '0';

a_in <= '1';

a_in <= '0';

assert(false) report "Test done" severity note;

-- Testbench for half adder -- Simple half adder design

entity testbench is entity half_adder is

DUT: half_adder port map(a_in, b_in, s_out, c_out);

a_in <= '0';

a_in <= '1';

a_in <= '1';

a_in <= '0';

assert false report "Test done." severity note;

A B Cin Sum Cout

-- Testbench for full adder -- Simple full adder design

entity testbench is entity full_adder is

DUT: full_adder port map(a_in, b_in, c_in, s_out,

a_in <= '0';

a_in <= '0';

a_in <= '0';

a_in <= '1';

a_in <= '1';

a_in <= '1';

a_in <= '0';