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CPET7L PracticalExam Batch1
CPET7L PracticalExam Batch1
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Verilog Codes
The logic of a module can be described in anyone (or a combination) of the following modeling styles:
Summary:
• Gate-level modeling using instantiations of predefined and user-defined primitive gates. It is
very intuitive to a designer with a basic knowledge of digital logic circuit
• Dataflow modeling using continuous assignment statements with the keyword assign.
• Behavioral modeling using procedural assignment statements with the keyword always.
MSB LSB
2^ 7 2^6 2^5 2^4 2^3 2^2 2^1 2^0
128 64 32 16 8 4 2 1
Example:
11111111 = 8 bits
255= 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1
for Decimal
Computation:
= 256 -1
= 255 11111111
The individual bits are specified within square brackets, so D [2] specifies bit 2 of D. It is also possible to address parts
(contiguous bits) of vectors.
Example:
module definition
module and4 (x, y, z);
input [3:0] x, y;
output [3:0] z;
assign z = x | y;
end module
module TestBench;
reg W, X, Y, Z;
wire a;
initial begin
$display ("W X Y Z a ");
W =1'b0; X =1'b0; Y =1'b0; Z =1'b0;
#15 $finish;
end
Practical Midterm Exam Question:
Here is the following step to solve the given combinational logic design:
1. Specification, you must know the following specification in a circuit. Assume the inputs are W,
X, Y and Z. where:
• Variable W is the most significant bit (MSB)
• Variable Z is the least significant bit (LSB)
WXYZ = 4 variables
2 ^ 4 = 16 rows / lines
2. Formulation – you need to convert the specifications into a variety of forms. The form is to
construct a Truth table. The table below shows the conversion of binary number to decimal
number.
Table 1: Truth Table for BCD
K=mapping
m0 m1 m2 m3
m4 m5 m7 m6
m 12 m 13 m 15 m14
m8 m9 m 11 m10
Add
files
Requirements:
• Circuit Diagram as shown on figure 2 and figure 3.
• Verilog program either dataflow or behavioral Modeling
styles
• Documentation with figure and description
Circuit Diagram:
Boolean Expression and K- mapping:
Output a:
Output b:
Output c:
Output d:
Output e:
Output f:
Output g:
Dataflow: