Features ‘+ High-performance, Low-power AVR® 6-bit Microcontroller + Advancud RISC Architecture 143 Powerful wisth ction -Wioss ingle Clock Cycle Exect tion 32x _ General Purpose Working Registers + reripheral Control Registers + eilly Static Dperation ~ Up to 16 MIPS Throughput ut 16 MH. Ty = incchip 2-cycle Multipli + High Enaurance Non-volatile Memory segments = 128K Bytes of In-system Self-programmable Flash program memory ~ 4K wytes EEPROM ~ 4K Bytes Internal SRAM = Write/Erase cycles: 10,000 Flash/100,000 EEPROM = Lata retention: 0 years at 85°C/100 years at 25°C) = Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Reac-While-Write Operation ~ Up to 6- Bytes Optional External Memory Space = Programming eck ior Software Seourity = SPI Interface for In-System Programming + STAG (IEEE std. 1149.1 Compliant) Interface ~ Boundary-scan Capal lties According to the JTAG Standard ~ Extensive On-chip Debug Support — Programming of Flash, EEPROM, Fuses and Lock Bits through the JAG Interface + Peripheral Features 8-bit AVR Microcontroller with 128K Bytes In-System Programmable Flash “Two eit Timer-Counters wth Separate Prescalers and Compare Modes ATmega128A = Two Expanded 16-bit TimerrCounters with Separate Prescaler, Compare Mode and Capture Mode ~ Real Time Counter with Separate Oscillator = Two 6-bit PWM Channels Summary = 6 PWM Channels with Programmable Resolution from 2 to 16 Bits = Output Compare Modulator = s-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable iain at 1x, 10x, or 200x = Byte-oriented Two-wire Serial Interface = Dual Programmable Serial USARTs ~ Master/Slave SPI Serial Interface = Programmable Watchdog Timer with On-chip Oscillator = On-chip Analog Comparator Special microcontroller Features ~ Power-on Reset and Programmable Brown-out Detection = Intemal Calibrated RC Oscillator = External and Internal Interrupt Sources ~ Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby ~ Software Selectable Clock Frequency = ATmagat03 Compatibility Mode Selected by a Fuse = Global Pull-up Disable VO and Packages ~ 53 Programmable VO Lines ~ 64-lead TOFP and 64-pad QFN/MLF + Operating Voltages = 2.7- 8.8V for ATmegat28A Speed Grades = 0-16 MHz for ATmegat28A, Rey. e15108-AVR-6700 Amel,<1. ATS 32128 A Pin Configurations Figure 1-1. Pinout ATmegat28A 1 PFO yDCo, 1 PFS vaDOs/T 8) exo szhvec 6 few 62D AREF 60/1 PFI DC, S05 PF2 0C2, 58 [1 PFS yaDC3) 571 PF4 \ADCAITOK) 55} PFS \ADC8/T_O) 54 PF? aDC7/T_9 811 PAO (ADO) 50 PAt (ADI) wf Pa2 (AD2) o64pavec 61 PENG XDAI(PD) PEO | (PxDo!PDO) PEI C} (XCKO/AINO) PE2 C| (003./AIN?) PES: (OC3BANT4) PE4 C] (2C3C1NTS) PES C} (TINTS) PES 'C, 8NT!) PE? C| (68) PEO} 10 su) PBI 11 (Most) Pe2 C] 12 (MSO) PBSC} 13 v0) PBA] 1+ (001A) PBC} (0018) Pee C} 48D Pas (AD3, 47 DPAA (AD4, 46D Pas (AD5, FipGi(AD) Hpco(wr) oe RESET Cl 2c veeclz: enodez wae Xai es Poo | 2s poi C6 poz z7 Pos Cz. Pos] z9 Posc31 (2) P78, ck1) PDS] 3¢ c (CPt TELC Ped] to TCLC Pos] 19 (SCL NTO) \SDAN 1 (czocre) PB? C17 (X01 Nig) (XDI, N73) Note: The Pinou: igu e applies ty butt TOFP and MLF package. Tie bo torr: pad under he QFNMLF package should be soldered to grou. 2. Overview The ATmega128A is a low-power CMOS &-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega1ZBA achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. AIMEL 2 ‘15108-AVR-0700<1. ATS 32128 A 2.1 Block Diagram Figure 2-1. Block Diagram Hh ‘15108-AVR-0700 AIMEL<1. ATS 32128 A The AVR core combines a rich instruction set with 32 general purpose working registers. All the 82 registers are directly connected to the Arithmetic .ogic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture Is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATmegat28A provides the following features: 128K bytes of In-System Programmable Flash with Flead-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general pur- Pose I/O lines, 32 general purpose working registers, Real Time Counter (RTO), four flexible Timer/Counters with compare modes and PWM, 2 USARTS, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the Dn-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue funetion- ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all ther chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn- chronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all /]O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. ‘The device is manufactured using Atme!'s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circult emulators, and evaluation Kits. 2.2 ATmega103 and ATmega128A Compatibility ‘15108-AVR-0700 ‘The ATmega128A is a highly complex microcontroller where the number of V/O locations super- ssodes the 64 V/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmegat03, all /O locations present in ATmega103 have the same location in ‘ATmega128A. Most additional /O locations are added in an Extended /O space starting from $60 to SFF, (Le, in the ATmega103 internal RAM space; These locations can be reached by Using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and O JT instructions. The relocation ofthe internal RAM space may sii be a problem for ATmegat03 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended VO space are in use, so the intemal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed. AIMEL 4<1. ATS 32128 A The ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what the user should be aware of replacing the ATmega103 by an ATmegat28A, 2.2.1 ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new fea- tures in ATmega128 are not available in this compatibility mode, these features are listed below: * One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. * One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with three compare registers. + Two-wire serial interface is not supported. * Port C is output only. ++ Port G serves alternate functions only (not a general /O port) * Port F serves as digital input only in addition to analog input to the ADC. * Boot Loader capabilities is not supported. + Itis not possible to adjust the frequency of the internal calibrated RC Oscillator. * The External Memory Interface can not release any Address pins for general VO, neither configure different wait-states to different External Memory Address sections. * In addition, there are some other minor differences to make it more compatible to ATmega103: * Only EXTRF and PORF exists in MCUCSR. * Timed se_uence not required for Watchdog Time-out change. ‘+ External Interrupt pins 3 - 0 serve as level interrupt only. * USART has no FIFO buffer, so data overrun comes earlier. Unused 1/0 bits in ATmega103 should be written to 0 to ensure same operation in ATmega 128. 2.3 Pin Descriptions 2341 vec 23.2 GND Digital supply voltage. Ground. 2.3.3. Port A (PA7:PA0) ‘15108-AVR-0700 Port A is an bit bi-directional /O port with intemal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are extemally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running, Port A also serves the functions of various special features of the ATmegat28A as listed on Page 73. AIMEL 5<1. ATS 32128 A 23.4 Port B is an &bit bi-directional /O port with intemal pul-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running, Port B also serves the functions of various special features of the ATmegat28A as listed on page 74. 2.3.5 Port C (PC7:PCO) Port Cis an 8bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running, Port C also serves the functions of special features of the ATmega128A as listed on page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Note: The ATmega128A is by default shipped in ATmega103 compatiblity mode Thus, i the parts are ‘not programmed before they are put on the PCB, PORTC will be output durin first power up, and nti the ATme,ja103 compatilty mode is disabled. 2.3: Port D (PD7:PD0) Port D is an 8bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running, Port D also serves the functions of various special features of the ATmegat28A as listed on age 78. 2.3.7 Port E (PET:PEQ) Port E is an 8bit bi-directional /O port with intemal pul-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running, Port E also serves the functions of various special features of the ATmegat28A as listed on page 81 2.3.8 Port F (PF7:PFO) ‘15108-AVR-0700 Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional /O port, if the A/D Converter is not used. Port pins can provide intemal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the AIMEL 8<1. ATS 32128 A 2.3.9 2.3.10 23.11 23.12 2.3.13 2.3.14 23.15 TAG interface is enabled, the pull-up resistors on pins PF7(TD!), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. ‘The TDO pin is tr-stated unless TAP states that shift out data are entered, Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port Fis an input Port only. Port G (PG4:PG0) RESET XTALI XTAL2 avec AREF PEN ‘15108-AVR-0700 Port G is a 5-bit bi-directional /O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tr-stated when a reset condition becomes active, even if the clock is not running, Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running, In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PGO = 1, PGt = 1, and PG2 =0 asynchronously when a reset condition becomes active, even if the clock is not running, PG3 and PG4 are oscillator pins. Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in "System and Reset Characteristics" 01 page 324. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to Voc, even if the ADC is not used. If the ADC is used, it should be connected to Voc through a low-pass fiter. AREF is the analog reference pin for the A/D Converter. PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- {gramming mode. PEN has no function during normal operation. AIMEL 7<1. ATS 32128 A 3. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. ATmega128A/L rev. A-M characterization is found in the ATmega128A Appendix B. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. Amel, : s1510S-AVR-07!08<1. ATS 32128 A 5. Register Summary [_aacrece [Name a A ee) [eres | 5 5 5 = = = S 138) | vesste [=| unser |—ueai—[ ura | usar | ues | —oszio | vere = is uA. USARTTT Cope © se) | vesn. | acer | —vxcies | —vomer [mage —[ ix at | —ooseta [tos et 8 (so) tea m (soa unr 5 5 7 a = = (956, | fesnes [= = = (965, ucse0c [=| one Tro = (56 reser [= = = (89 reser [= = = (22) resins [= S = (1) [ewes [= = = (sso. | unneos [= 5 = ‘weri | Resenes | 5 a (see) | Resenes | s = (380) | Resse [= s = 1580) | ~Toorac | Foca | — Foca = a20)| “Teor | “consat_| oom wou tae) | Toorse | rence | — wes 0 (s69)__[ row s9__| ros. 18.) | ocrws (85, [oc (ssa ocr, (ss, orm is) cra ‘at is = ‘at (sre) | fesnes [= = = = = = = = (976) | peeves | = = = = = = = ‘s erase [= 5 wees | ocesa | ocess | roxs | oniese | enrte a ey ial eS = ics [corm | ccna | —tovs | cara | cre a (76) | Reseed [= Ss = = = = = = ay | “Toone | roca | —reore | —Focte a = = = = (s79)__| oom “Thea = Odd Compare Regie Cagh Bye (era, comon “ieee = Out Cops Rese C Lon (sin | Peers |= 5 a a = = 5 (s76- | Peers [= s S S = = = = (615, | Peers [= s eS S = = = = (sa ‘won| twat —|—twea | wera | —twsro | —twwe—| ew eS Tw a ‘sr Wom wb sealer Oi ete zs sr ‘wan [twas [was [wae [twas [wae | twa [wn [wae 2 (sr went [ ws | wes | rss | awe | ss = wre [woo a is er Tee Sra bs ata ger es is Ecc ‘eso Clon Rs “ i306) | ress 5 5 = = = = 5 360) | ca Sa | ea [sao [st | sn | a = (sec) | mca | — = es a = ‘aia —| — ns —[ = (306) | “reees[ 5 5 5 = = = = ‘ea ecea—| een, een | een | sean | sen | sore | cor | som = (869) | feared [= = = = < < = = (s65,|seucsn | sews | vs =| aes [asset | power | paeas [seu ro (ser) | reesnes [= = = = = = = = (865, | fesnes [= = = = = = = = (e) ona = = =| rosres | ronan | romres | sora | roman = ( one. 5 s Es poa1 | —ppan | pce | —ppat Da s =) NS 5 Ss = a e ‘15108-AVR-0700<1. ATS 32128 A 5. Register Summary (Continued) ‘asece | Name] BRT] BRS] BRS] ene) and] ena] ant Bro Pave Ce ee oe oor Dae a = = = = = = = ‘easy | sare 1 T x s v N z e wo ‘Se 6se) [en | ors [oa | oer | are [oon [oreo oa ora © 50.650) [ert Fr oa os a 3 2 1 Po 6 S06 ‘ow [soe | soe | aos | xo | axons | pone | xonei | a = 6.55) | pawez [= = = = z z aurea rn suesa) [oon [een | ere [eee [sea [ sos [ oso 40 ar 2059 | ese ar ra rm Ne rl m7 ol into we S30350) ‘gen [rer | tes | wes [ae [wrest | ao we 0185) | asx [ocx | roe | “nee | “paix | ocx —roxr | “onan [rosso Te ‘58,580 | ten | oor | toe 11 ocria | ocr | tows | — ocr Tow 110, wa. 1e2 Sis | weuca | sme | sawio | su ‘su uz | se Nee aoe sstiss | wevese | ro. A - cme | wore | ome [extn | poe se 207 ‘su | recno [Foo | wawen | cover [como | —wewor | esa | esot 50 ma sais | rewro “ena ma ‘ss | oon Tita Cup Congr ‘08 sso;ss | Assn 5 = 5 a aso | Texcos | —ocntus [Ten ‘08 sera7__| —Tecnia | cowiat | couraa | cower | counso | comet | comico | wows | — wou ‘see gue) [toons | enor ess a ‘wows | —wemse [este | esti 0 20 640) [Town “TinCan ~via Regs ih je 20 640) | Toure Teper ~ Car Regt Lowe ‘segas) [oct Tsar Out Congr Roger igh Be soxgan) | ocmta. “Teese — Ops Cong Reger A Low 2) | ocsum Ties — Out Congr Rapti Be ssa | ocr “Teper — Oud Conger 8 Low 271949 | rn TeorCourr mo Cpr ROR HONE 2640) | rome To — pu POT ge Low Bt 5160) | yoore | rece [wanes [cower | cone | women | cme [ost oe seesen | Towra “enon ca soe | oon “pose Ose Carpar aga ie 2190 | ocon | wimecany | ocone | —ocos | ocone | coves | aco [acon | ocoa ze suse) | worea a = woos [woe | —wora [woes | — woro = ssa | — sion | Tow 5 = = “acu | — pu a TTT sie") | eer = 5 = a TEPnOu Aaa eg ‘= sieg9e) | ee, Ea Aas Rogar ow Be = $10 ga0) | espa EePacM bas Regie = sicse) [esc 5 5 5 A ene [cows [eave [een = sisgae| | ponta | romtay | pomras | pomras | pomtaa | rowtas | porta | Porras | Pomtaa = sixeat) [bora | pow | oo [poss [nose [nota | pox | owt roan = $1930 ra | eras | pwns | eas | rns | pus | pu | wat | pre = sia.gay | —Ponra [poner | ones | —poras | Ponraa | —ronrea | —ponrea | —romret | Ponto: = S780 ‘bons | 067 | ones | oes | nose | ~ poss | nose | ~ sr ‘80 =. 51698) ‘ne | —Pwer | mes —| Paes | rma | rea | ruse —| pret | Pris = '15;699 | Pont |ponror| pores | ~pontes | porte | ronres_|~romtez | Foatci | ~roares. @. siaisag | — pono [ocr | ons | — pocs | pea | — pecs | once | — ner 100 7 S108 anc —| por | wos —| Paes | —pmce—| pics | pnce | nc [Pica 21s2 | pont | poaroy | poroe | ponros | poatoa | rorros | romtnz | poator | postr, my st1isa | oon [poor | oops —|~ ons —|~ ooo | ~ 00a —|~ ooo | ~ anor ‘oo my 5105 pw [wor | woe | Pos | pee | pos | poe | nor | Pron oe ‘sraor) [soon ia Reger re ‘ne ge) | eran | err [woe 5 a a 5 5 wa +8 a sre |_—bono | —werm—| —crou| ceva | set Pr a soc 620) | uono. UcASTOV Os ogi 2 ‘06 5) | ucsset | pace [6s [woes [reo | bono [pee [aro [ro ok 62x) | —ucseoe | aves | tac) yorico | — axe —[ ano [uesen | ms | Te sen [vem AST oa a ago 7 suusay | acs | Ae] aewe [0 21 noe | ae [ass] no ZI san(s2)| aowux [rast | nso | —Anuas [ae | [| [a 26 15629 | ~aocsra | —aoen | —aosc— aber | — ane —| — ane | nos | anes | —aneso 2 ‘soog2y | ncn ec oa Rage ae soon | aen ‘ADC Os Reg Lom Be ‘sus2q | pore | power | pomves | pomres | ponres | powres | romres | rower [Pome = AIMEL 10 ‘15108-AVR-0700<1. ATS 32128 A 5. Register Summary (Continued) Tasrece | Nome m7 me = ea ms me mr ro ae ‘sag29 | pone | ~oner | ones | nes | ocx | ~ pos —| ne | one Boe = 50520 fone —[ ewer —| reo | —owues | —pnuca | pen [pus | pet | rico ssa [ene | ener | —pmee | ones [ems | —paea | pw [ wer [ero = Notes: 1. For compatbilty with future devices, reserved bits should be writen to zero if accessed. Reserved YO memory addresses. should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the VO register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions ‘work with registers $00 to $1F only. Amel, " ‘15108-AVR-0700<1. ATS 32128 A 6. Instruction Set Summary ace ZEN Ss ake Su rete Cary wo gui cee ZONA S861 ti Sut Cay Const a ap ie RIK-C ZoNvi sew ax Swat nme ton Won on = nah ZENS 280. ae Lae AN Rees bef Fe ZNv N00 a Len AND Pepe en Cn iio zuv on ane Let OF gts ihe zuv ‘on Bak Lape OF Reger ond Oct Rie zuv con a Re xe OF Reser sc Pa Zuv ‘ow ia Ons Comper Ries Ad ZoNy Neg iat Twos Comper se S00 A ZoNvi on ina Be) Reger Bie RIK, Znv oc ak ‘Osa ROD ec te znv cour Be ‘Osa rags is =A 9 ZHv So i ‘sa Riaeer Bee at a Bate Su Ur i = A ze MS Ba Re Mu Sod 0 = AL Ze MSE Bae Mut Sa wa Une 0 = AL Ze uh ae recon ugly Unagres rises <7 zc rite ae econ Mt Se pute mec! ze ane " aaah a PocPeoest rs ‘ase nsec arp Poez a Me x ‘rel np Pom at TAL, int Cato ronz at fr rat At Poe STACK i cma ae ‘Congr. Sip Ea (= ty POPS rs ide — fe ZNVOR ‘ne ‘ade Cong aed ZNvoH cr a Conroe wna ok Znvon ne Fb kp Fm Regs Cars REO PET POETS , oo ‘kp FB Reger Se ngs) Po Foro 30 Be np VO Regs CIS HPO Peso 8 on kp Tm ¥O Reger Set pI) PO PEP ra a rch Sane Fg Se H(SALGE)= nen Poe PERTT Ae a rc Sune Fog i (SAE) = nen PEHR ST neo i arc ea Hig Bene PETES ro it arch ene ca H(Z=0)pen Pe PERSE exo © ‘Sarch Sane area hen Poe PE fr i ‘ach Gro of Ea Se ‘ear it ‘Sach 56 Than 20, Spe on ik ‘atch Hat Cry Fag Se ‘erie * ‘Sach Ha Cy Fag Coa ane t ‘Barc Fg St are i Barc Fig Gest ene Pores | ‘15108-AVR-0700 AIMEL 12<1. ATS 32128 A 6. Instruction Set Summary (Continued) MO Bae Te we oe n MOM fe ony eg Wa eter Re t ot Bak La eae Baek + ro Pax oat art seo) 2 w axe sera Pane ree pee 2 w- es oad net and Prac ev 1 Ret) 2 06 Pa Lo ac wth pace RimCoa 2 w- az oad nel nd Pec 22-1 Abe Zh 2 e Baz oat eet th Deport Bie 2 ws. ae oss Dre fe SRAM Bee 2 et 1 ‘Sor ret ee 2 = ae Soe et aos ge XeXeE 2 st we Som nest ore 2 ST eRe ‘Som net an Poin (mYe Yet 2 ca Re ‘Som net are Yev-t. ee 2 ‘s1 ane ‘Soe nae wh Depart soem 2 sv zie ‘Sot niet PT @emzeet 2 sr 7 So ait an re Zez ge 2 0. Zea Soe et wih Oop Parra 2 SIs ee ‘Sor Diets SA os 2 war oat Pm vena Fo 2 cat maz teas Progen ra = ca Baz toss Pan Ueno ad Pane ereren 2 seu eros and Prog er ron (RPE 2 eeu Biz eres Land Prog Maney SP fen (UPL, PET = AUPE 2 Sa Sor Prgyan Mey @=AuRo Pasi oa Fh Region Sc sok 2 roe. bs ep gel tm Sock Bs SAGE 2 m7 2 Sa fg wor ae 2 mo Be ea Bini Reger wos) ere 2 ia Bs Logs tt ai Ra Ra = ZoNy n sr a Loge Sm FE Fn «fi Ba) 0 Z6NW + AOL Fe at Let Toph Ca Raia HACER ZGnW + nom. Be os in Te Cay CC RON en} C0) ZGKW + a it ‘Ameen Sa gt Fn = Fa ma ZGNW + ‘ona Be ‘Snap nebes sa Ra aE now + est . Fan et sno) Sco r ean no og Gee sea) 0 Sea) r esr ae at Se non agar TA 7 o a Pa tad Hon Tis Regt ab) na n = Sernegse Fag N . eu (Ges Nee Fg N n = setze0Fg z n ez (es 7 Fe z n 58 ltl erg H i ou http Di H i ‘15108-AVR-0700 AIMEL 13<1. ATS 32128 A 6. Instruction Set Summary (Continued) nemonies | Operands] Description ‘Operation Amel, " ‘15108-AVR-0700<1. ATS 32128 A 7. Ordering Information 7.1 ATmega128A ‘Speed (MHz) Power Supply ‘Ordering Code™ Package” Operation Range ‘Almogat2BA-1=AS aA Industrial 27-88V Tmegat20A-1=M3 eam (40°C to 85 C) Notes: 1 The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information ‘and minimum quantities, Phtree packaging complies to the “-uropean Directive for Restriction of Hazardous Substances (RoHS directve,. Also halide free and fully Green, Package Type 64:ead, 14 « 14 x 1.0 mm, Thin Profle Plastic Quad Flat Package (TOFP) 64:pad, 9x 9.x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/M_F) 4A, eau be avneves AIMEL, 8<1. ATS 32128 A 8. Packaging Information 81 64a MMA Annan pnt fe l= 8 ~awiipenipen = f = e - Soe 1 ke i 1 ' c ie? ' we i a tA COMMON DIMEN IONS (Un Uoa8 re=mm) Svmeou] WN | NOM | WAX | NOTE al 129 ar | ous 235 ne | vss | 100 | 105 | 1575 | 1609 | 1625 Dt_| 1590 | 1600 | 1440 | Nate? 7 [1575 | 1600 | 1625 This ; ak ¢ 6 coaforms 10 JELLL ‘elerence MS 026. Varia.or EB. Ld 43.90 | 1400 | 14.10 | Note 2 2. Dinar sons DY and 1 donot intde ma oto owable a few | - | os roti ie 25.048 gs. Diversions and Ea wai plastic bocy sice dimensions including ok mismatch. c O98 = 920 v. Loo crt ay i 0.10 mn mana [eas | — [ov ° oa0NP 10/8200 z2s oa Panay EE a=W NO. | REV. chard Parkway 2 G4A, 64foad, 14x 14 mm Body Sizo, 1.0 mm Body Thickness, ‘San Jose, CA 95131 | a8 mm Lead Pitch, Thin Profile Plastic Gad Flat Package (TOFP} em 8 AIMEL ‘15108-AVR-0700 16<1. ATS 32128 A 8.2 64M1 \ ated P10 ToP VIEW ma m fc ran cne SIDE View UyUUUUUETYD WW Ae coon ats, es eh, 5 2) gs sorrom view : — os | oa [oa x baes Die [8 Note 1--2DECS dard 0-220, (SAW Siou! ton) ig. 1, VMIMD. 2.Dimansion snd ora wo form ASME 14.5% 1994, WE GAN, 64-pad, 9x 9.x 1 * mm Body, Lead Pi.ch 0.50 mn 5.40 mm Exposed Pad, Micro Lead Frame Packaye (MF 2925 Orchard Parkway ‘San Jose. Ch, 9131 AIMEL ‘15108-AVR-0700<1. ATS 32128 A 9. Errata The revision letter in this section refers to the revision of the ATmega128A device. 9.1 ATmegai28A Rev. U + Nr: ng value f-r Version in the JTAG Device Identification Register First Analog Comparaior conversion may be #elayed Interrupts nay .e lost when writing the ti er regisiers in ine asnenronous iit or ‘Stabilicing ti ne needed when changing xDIY Register ‘Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conv_rsion may e delay_d I the device is powered by a slow rising Voo, the first Analog Comparator coaversion will taxe longer than expected on some devices. Problem FixiWorkaround “shen the device has been powered or reset, disable then enable the Analog Comparator before the first conversion. 2. Interrupts may b? lost when writing the tim or registers in tl.2 asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround ‘Always check that the asynchronous Timer/Counter register neither have the value OxFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Dutput Compare Register (2CRx). 3. Stabilizing time needed wren changing XDIV Register Aiter increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly Problem Fix / Workaround ‘The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change should be NOP instructions. To ensure this, follow this procedure: 1.Clear the | bitin the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute © NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly, ‘Assembly Code Example: cut global interrupt enable wor XDIV, temp; set new prescale value Noe nyo eration Noe 1 noo eatin Now fn: 0 ecati n Amel, 8 ‘15108-AVR-0700<1. ATS 32128 A NOP + no operation NOP + no operation NOP 1 no operation Noe no operation NOP no operation SEI set global interrupt enuble 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCA'. reg- ister, the device may execute some of the subsequent instructions incorrectly, Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata, 5. IDCODE masks data from TDI input ‘The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.. Problem Fix / Workaround ~ If ATmega128A is the only device in the scan chain, the problem is not visible. = Select the Device ID Register of the ATmega128A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega128A while reading the Device ID Registers of preceding devices of the boundary scan chain. ~ If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega128A must be the fist device in the chain. 6. Reading EEPROM by using ST or STS to set EERE request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg- ister triggers an unexpected EEPROM interrupt request. triggers unexpected interrupt Problem Fix / Workaround Always use OUT or SBI to set EERE in ECR. Amel, * ‘15108-AVR-0700<1. ATS 32128 A 10. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision, 10.4 10.2 10.4 Rev. 8151D - 07/09 Rev. 8151C — 05/09 Rev. 8151B — 03/09 Rev. 8151A- 08/08 ‘15108-AVR-0700 Updated “Errata” on page 376. Updated the last page with Atmel's new addres: » Updated “Errata” on page 376, Almega:28A Rev. U. Updated view of ~.ypical Characteristics” on page 237 view. sit tial updates, Initial revision. (Based cn the Atmega128:L datasheet 2467R-AVR 6:8) Changes done compared to the ATmega128\L datasheet 2457R-AVR-06'08: - Uzdated "Stack Pointer’ on page 13 description. “Powe Management and Sleep Modes" on page 46 is reorganized, + All Electrical chara:teristcs is moved to “E'ectica’ Characteristics" on page 221 - Jutput Low Voltage (Vo, and Reset Pull-up Resistor (Rpg) limits updated in “DC Characteristics’ on page 221 - Register descriptions are moved to sub sections at the end of each chapter. New graphs in “Typical Characteristics” on page 338. = New "Ordering Information” on page 373. Amel, ~AIMEL Headquarters, International ‘Atme! Corporation ‘Atme! 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Aunel doos not make any commisnent o update the information conaied herr. welase special provid ‘thermo, rime! products are Nt sub or and shall nol be used in. aulomolnve apploations: Amol prodvts are nat onde, auhorze, or warranted To Os [ss components appicationsintnded fo support or sustain fe (© 1009 Atmel Corporation. All righte reserved. Atmel®, Atmel logo and some nations thereor, AVR® and others are registered trademarks or ‘ademarks of Atmel Corporation oils subeldiaries. Other lerms and product names may be trademarks of others. ‘15108-AVR-0700