Hardware Documentation

CNN
FPGA
Implementation
Hardware
Documentation
A Logic Design
Project By:
Ahmed Abdulkader 1170472
Daniel Eskandar 1170524
Omar Essam 1162285
Omar Tarek 1170331
Ahmed Ezzat 1162033
CNN
FPGA
Implementation
This is a Hardware Documentation for the Logic Design Project aiming to implement
a convolutional neural network on an FPGA using Verilog. The project is designed
through different independent modules, each executed by a different team member.
The first part of the report is a general overview of the project and a guide to the
attached files, with general procedures of testing and execution outlined. Then the
individual reports prepared by each individual team member are attached, along
with additional appendices to satisfy all required project deliverables.
CONTENTS
Overview Reporting
Project Overview
Member Distribution
Testing Overview
Attachments Overview
General Team Comments
Individual Reporting
Part 1- Daniel Eskandar
Part 2- Ahmed Ezzat
Part 3- Omar Essam
Part 4- Ahmed Abdulkader
Part 5- Omar Tarek
Overview
Reporting
Section
This section is a summary and outline of the project

as a whole, providing a good outline as a starting
point, explaining several key points
Project Overview
Member Distribution
Testing Overview
Project Overview
The Project is an implementation of the leNet-5
CNN architecture. As such our team consists of
5 members each executing a different part of the
Network. The distribution is as follows:
Daniel Eskandar Part 1- Convolution
Ahmed Ezzat Part 2- Tanh Activation
Omar Essam Part 3- SoftMax Activation
Ahmed Abdulkader Part 4- Average Pooling
Omar Tarek Part 5- Integration
All modules are verfied to be functional and synthesizable. The testing

procedures and verification will be outlined over the next pages
explaining the attached folder layouts and additional information on
the test cases used. Disscussions and relevant comments would also
be attached to every special case handled.
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
The next few pages will cover a summary on the different parts and
their implementations.
Part 1 - Convolution
Done By: Daniel Eskandar
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
The network has 3 convolution layers, each with different filters, all of
Kernel Size 5x5. Details of implementation would be found at the
individual report by Daniel. Several architectures were attempted and
implemented by Daniel, in an attempt to reach a compromise between
Parrallelism, Speed and Utilization. The trade off here is more parrallelism
requires higher power and is more hardware extensive. Less parrallelism
causes a decrease in speed. This balance is very tricky in convolution due
to the huge sizes of Data required for this complicated function. A
compromise was reached and a comparison between architectures
is outlined in Daniel’s individual report.
Code Folder:
\Final Code Files\Part 1- Convolution
Testing Scripts:
\Testing Scripts\Convolution Python Codes
Excel Sheets:
Conv1Test and Conv2Test
Part 2 - TanH Activation
Done By: Ahmed Ezzat
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
The activation function selected between the layers and each another
is the Hyperbolic Tangent Function. More details on structure and testing
are attached in the individual report prepared by Ahmed Ezzat. The
function deals with a large number of inputs, same issue as convolution.
During the convolution part of the integration, the TanH function is of
size 16, and at the fully connected parts it’s at size 32. The convergance
condition and the limiting range of 16 bit half precision floating point
numbers, and also the fact that this is implemented using the taylor
approximation of the function, make this a bottleneck of accuracy.
The accuracy is within the accepted range though.
Code Folder:
\Final Code Files\Part 2- TanH activation
Testing Scripts:
\Testing Scripts\Tanh testing Codes
Part 3 - SoftMax Activation
Done By: Omar Essam
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
The last layer in the leNet-5 architecture is a SoftMax activation layer.

This special activation layer takes the 10 produced values and through
a series of calculations produces the final classification of our neural
network. The series of calculations mentioned, is an approximation
of a function involving division of exponents. Implementations of
hardware division of several floating point numbers in Verliog is
exceptionally difficult, which led Omar Essam to develop multiple
architectures, and choosing the best compromise. Difference between
the architectures and the merits of each are discussed in detail in Omar
Essam’s individual report.
Code Folder:
\Final Code Files\Part 3- SoftMax activation
Testing Scripts:
\Testing Scripts\SoftMax Python Codes
Part 4 - Average Pooling
Done By: Ahmed Abdulkader
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
The network has 2 average pooling layers. These decrease the size of
the output data from the first 2 convolution layers. While fairly easy to
implement, they suffer from the same Data Size issue found in
convolution layers (part 1). These issues cause synthesis and utilization
problems, leading us to use compromises that may slow down the
process but improve hardware utilization significantly. The other
drawback of the large data size, is the inability of producing proper
post synthesis timing simulations. This is an issue that was agreed on
with faculty staff and we reached a compromise of simulating the
smallest processing element of each matrix.
Code Folder:
\Final Code Files\Part 4- Average Pooling
Testing Scripts:
\Testing Scripts\Average Pooling Python Codes
Excel Sheets:
AvgPool1Test and AvgPool2Test
Part 5 - Integrating Network
Done By: Omar Tarek
TanH
SoftMax
TanH
TanH
TanH
OUTPUT
avgPool avgPool
conv
conv
conv
FClayer
FClayer
INPUT
Arguably the hardest, least synthesizable and largest part of this project
is making sure that the network integrates properly. To make this happen
collabaration between the member responsible for integration, Omar
Tarek, and the rest of the team was essential. To also make the testing
easier, testing on the convolution units and the average pool units was
done consecutively with one input number image and plugging the
output data of the previous layer into the next layer. More on this could
be found on the testing section of the group report. Due to the sheer size
of this network synthesis was not attempted due to hardware limits.
More details are in the individual report.
Code Folder:
\Final Code Files\Part 5- Integration
Testing Scripts:
\Testing Scripts\ANN testing code +previously mentioned
Excel Sheets:
Testing Overview
Testing is done through the following procedure:
1) A code of similar function is run on an external script written in
a different software design language (Python and C++)
2) The corresponding testbench is run on ModelSim and Data
Results are extracted
3) Both Sets of data are compared against one another, with
random samples taken for conversion to check if results are
correct
4) If errors are found, the code is corrected and we start over
Special testing procedure for Convolution and AvgPool:

For average pooling and convolution the same procedure is
carried out, however it is done consecutively. The results of each
prior stage are passed on as inputs of the next. This method
ensures that all values are accumulated into a single data set
that if correct by the end would mean the whole process was
probably correctly functioning.
All test scripts used are attached in the \Testing Scripts\ folder. In order to save
time and effort the data sets used to verify the function are attached on a separate
excel spreadsheet. This has data extracted from the test codes and the actual codes
stacked against one another as a proof of function. This is only for layers that
function on large data set level, like convolution, average pooling, and fully
connected layers. Layers that do not change dimension (TanH and SoftMax) don’t
need large amounts of Data Comparison, a proof of function of the smallest unit
was found to be enough to proof the function of the full unit.
This report comes attached with the hardware and
supplementary files attached. This is a guide to the
file folders:
CNN-FPGA
Vivado Project (Vivado Project with full architecture)
Final Code Files (Individual Parts Verilog Files)
Screenshots and Reports (Full Screenshots and Synthesis)
Testing Scripts (All supplementary testing codes)
Weight Files (All used weight files, with IEEE variants)
Extra Convolution (Additional Convlution Architectures)
The code files are also attached at the end of this

report and linked through each memeber’s
individual report. In addition to the above
mentioned folders there are also several files.
The excel file mentioned in the testing section along
with a read me file for work load distribution.
This Report has attached files embedded into it.
Next to every needed attachable deliverable you will
find a paper clip icon that when opened will
automatically open the required file.
Synthesis was attempted for all files. And the maximum

achievable utilization for each code was attempted
trying to compromise with speed and parallelism.
In the next part each document was written entirely by

the team member whose name is mentioned before
it. The overview part was written by Ahmed Abdulkader.
Post Synthesis simulation was agreed upon to simply

cover the smallest processing unit in codes where sizes
are massive.
All original screenshots, reports, and test files are

attached with the folder supplied with this report.
Individual
Reporting
Section
The next section covers individual reports, that

contain each members independent deliverables
Part 1- Daniel Eskandar

Part 2- Ahmed Ezzat
Part 3- Omar Essam
Part 4- Ahmed Abdulkader
Part 5- Omar Tarek
Part 1
Convolution
Daniel Eskandar
Part 1-Convolution
1) Block Diagrams
Processing Element
floatA
Result
floatB
floatMult floatAdd
Convolution Unit
image
Result
CU
filter
Single Filter Layer
CU
image
RFselector
CU
Result
OutputConv
filter CU
....
x14
CU
Multi Filter Layer
image
Single Filter Layer

Result
OutputConv
Single Filter Layer

filterSet
Filters
2) Verilog Codes
convUnit.v
convLayerSingle.v
convLayerMulti.v
RFselector.v
3) Verilog Tesbench
convUnit_TB.v
convLayerSingle_TB.v
convLayerMulti_TB.v
4) Screenshots:
a. Simulation (Waveform/TCL console):
i. ConvUnit
Testing the conv unit was done using one number repeatedly for checking if the process is done
correctly quickly. The number used here is 4.
ii. Single Filter Layer

This screenshot is on a zoom full view. The red signals signify that the chip is still mid processing and filling out part
by part of the complete signal, for the final result check the next screenshot.
Here we zoomed on the end of the code run, the processing has stopped and the result is
ready!
TCL script and waveform of the final output

iii. Multi Filter Layer
All results were verified using the simulated Convolution Layer

run on python. You can find the python script in the folder
Python Tests called ‘cLayer.py’. All result comparisons are also
listed out on the Convolution1Test sheet on the attached
CNNtest excel file (CNNtest.xlsx)
Excel Proof of function:
(compared to output from simulations)
The data was copied from the TCL console and pasted against
the results from our test code as shown clearly. The numbers in
the first row are of the 6 depths of the first convolution layer.
b. Post Synthesis Timing for the basic convUnit:
(as agreed upon post timing for larger layers of hardware are not achievable with our hardware capabilities. Our
attempts reached up to 14 hours, all while stalling the progress bar. It’s not achievable on consumer hardware)
5) Clock Cycle Count:

a. Conv Unit
(Depth*FilterW*FilterH)+1
(+1 for the reset cycle)
Example:
For a filter of size 5x5 and a depth of 1 would take (1*5*5)+1 = 26 CC
b. Single Filter Layer
[(ImgH-FilterH+1)( ImgW-FilterW+1)/(ImgH-FilterH+1/2)]*[(Depth*FilterW*FilterH)+1]
(Number of ConvUnits in the single layer multiplied by time taken for each unit)
Example:
For a layer of size 32x32 and a filter 5x5, it would take
[28*28/(28/2)]*[26] = 1456 CC
c. Multi Filter Layer
(fCnt/2)*[(ImgH-FilterH+1)( ImgW-FilterW+1)/(ImgH-FilterH+1/2)]*[(Depth*FilterW*FilterH)+1]
(Half Number of Filters in the multi-layer multiplied by time taken for each single layer)
Example:
For a layer of size 32x32 and 6 filters of 5x5, it would take
3*[28*28/(28/2)]*[26] = 4368 CC
6) Synthesis Utilization Report
Conv Unit
Conv Single-Layer
Conv Multi-Layer
7) Synthesis Schematic and Comments:
The Synthesis Schematics are attached on the next page.
The number of LUTs generated is 654 for the conv unit, 48422 for the
conv layer single filter and 455605 for the conv layer multiple filters. The
number of LUTs is small for the conv unit because it contains only one
processing element which contains one floating point adder and one
floating point multiplier. The number of LUTs increases exponentially in
the single and multiple filter modules because we make a number of
instances of the conv unit equal to half the number of pixels in a single
row in the output image (14 conv units for one filter for the first
convolution layer of LeNet). Also, the logic used of slicing and indexing
the input and output arrays to send parts of the image to these conv
units and connect their output to different parts of the output of the
whole module is very complicated in synthesis which increases the
number of LUTs in the layer with single filter but especially in the layer
with multiple filters.
8) Answers to extra questions:
I have implemented the convolution part with 5 different architectures. They
are all fully functional but the changes in the design of each architecture
reduced the utilization dramatically. The differences between the 5
architectures are in the design of the convolution layer that uses a single filter.
Architecture 1: Full Parallelism
In the conv layer single filter, the number of instances of conv units is equal to
the number of pixels in the output image (784 conv units for the first layer).
The results appear of only 26 clock cycles (number of clock cycles need for a
conv unit to finish the elementwise multiplication). This is the fastest design
but the biggest design in terms of LUTs and utilization.
Architecture 2: Sequential Convolution with 28 conv units (for one filter of the
first convolution layer LeNet)
In the conv layer single filter, the number of instances of conv units is equal to
the number of pixels of one row of the output image (28 conv units for the
first layer). The results appear after 728 clock cycles. This design is slower but
has improved the utilization a lot.
Architecture 3: Optimized design of Architecture 2 (28 conv units also for the
first layer with smaller receptive field arrays)
The parts of the image sent to the conv units were stored in a large array
called the receptive field. In the previous two architectures, this array was
calculated with a combinational logic for the whole input image generating the
matrices sent to all the conv units at once. This huge array contained 196000
(=28*28*25) values (each one represented by 32 bits). The addition in this
architecture is that we added a module RF selector that receives sequentially
the row and column of the selected pixels and returns the matrices of those
pixels only shrinking the size of the array to 700 (=28*25) values to improve
the utilization of architecture 3.
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I2 O
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FDCE C
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PRE
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counter[31]_i_1
I0
3
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CE 1
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LUT2
genblk1[13].CU
Q[4:0]
clk_IBUF_BUFG
column_reg[3]
column_reg[3]_rep__1[315:0]
column_reg[3]_rep__1_0
filter_IBUF[0:399]
... image_IBUF[843:0]
internalReset_reg
0 outputConv1
outputCounter_reg[6]
outputCounter_reg[6]_0
outputCounter_reg[11]_13 D[1275:0]
outputCounter_reg[11]_14 outputConv[6288]
result_reg[0] outputConv[6301]
result_reg[0]_0 outputConv[6302]
result_reg[13]_9 result[14:0]
result_reg[13]_10 selectedInput1_reg[0]_0
result_reg[14] selectedInput1_reg[0]_2
rowNumber_reg[0]_rep__1 selectedInput1_reg[3]_5
rowNumber_reg[1] selectedInput1_reg[3]_7
rowNumber_reg[1]_rep__5_0 selectedInput1_reg[4]_1
rowNumber_reg[1]_0 selectedInput1_reg[4]_5
rowNumber_reg[3]_rep selectedInput1_reg[12]_3
rowNumber_reg[3]_rep__0_10 selectedInput1_reg[15]_0[3:0]
rowNumber_reg[3]_rep__0_11
rowNumber_reg[3]_rep__2
rowNumber_reg[3]_0
rowNumber_reg[3]_1
rowNumber_reg[3]_2
rowNumber_reg[3]_3
rowNumber_reg[3]_4
rowNumber_reg[3]_5
rowNumber_reg[3]_6
rowNumber_reg[3]_7
rowNumber_reg[3]_8
rowNumber_reg[3]_9
rowNumber_reg[3]_10
rowNumber_reg[4]_rep
convUnit_3
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outputConv_reg[304]_i_2 CLR
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I2 O GE outputConv_OBUF[231]_inst
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I O
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I1 GE outputConv_OBUF[304]_inst
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617 I O
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756
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outputConv_reg[3707]_i_2 CLR FDCE
418
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outputConv_reg[3709]_i_2 outputConv_reg[3709] outputCounter_reg[6]

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outputConv_reg[9920]_i_2 GE outputConv_OBUF[10160]_inst
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outputConv_reg[9952]_i_2 LDCE outputConv_OBUF[10240]_inst

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column_reg[3]
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rowNumber[5]_i_2 I1 O
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3 rowNumber[5]_i_1
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LUT6
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rowNumber_reg[5]
I2 O
C I3
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FDCE C
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PRE
FDPE
counter[31]_i_1
I0
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CE 0
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genblk1[13].CU
Q[4:0]
clk_IBUF_BUFG
column_reg[3]
column_reg[3]_rep__1[315:0]
column_reg[3]_rep__1_0
filter_IBUF[0:399]
... image_IBUF[843:0]
internalReset_reg
0 outputConv1
outputCounter_reg[11]_13 D[1275:0]
result_reg[13]_9 result[14:0]
rowNumber_reg[3]_rep selectedInput1_reg[12]_3
rowNumber_reg[3]_rep__0_10 selectedInput1_reg[15]_0[3:0]
rowNumber_reg[3]_0
rowNumber_reg[3]_1
rowNumber_reg[3]_2
rowNumber_reg[3]_3
rowNumber_reg[3]_4
rowNumber_reg[3]_5
rowNumber_reg[3]_6
rowNumber_reg[3]_7
rowNumber_reg[3]_8
rowNumber_reg[3]_9
rowNumber_reg[3]_10
rowNumber_reg[4]_rep
convUnit_3
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I2 O GE outputConv_OBUF[231]_inst
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520 I O
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518 I O
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617 I O
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I2 GE
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LUT4
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835 I O
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LUT4
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outputConv_reg[3072]_i_2 CLR outputCounter_reg[1]
756
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outputConv_reg[3707]_i_2 CLR FDCE
418
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outputConv_reg[3709]_i_2 outputConv_reg[3709] outputCounter_reg[6]

I0 CLR
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LUT6 outputConv_reg[3808] outputConv_OBUF[3709]_inst
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outputConv_reg[9920]_i_2 GE outputConv_OBUF[10160]_inst
LDCE I O
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I2 CLR
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GE
outputConv_reg[9952]_i_2 LDCE outputConv_OBUF[10240]_inst

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outputConv_reg[2282]_i_3 I1 O CLR OBUF
173
I0 I2 D Q
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I2 O LUT4 GE outputConv_OBUF[10474]_inst
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I4 I0 outputConv_reg[10474] OBUF
LUT5 I1 CLR
outputConv_reg[234]_i_5 I2 O D Q
I0 I3 G
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I2 LUT5 LDCE
LUT4 I0
I1 O
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outputConv_reg[10474]_i_2 G
I0 GE
I1 LDCE
90 I O
I4 D Q
I5 G OBUF
LUT6 GE outputConv_OBUF[10875]_inst
LDCE I O
outputConv_reg[10877] OBUF
88 I O
I0 G OBUF
I1 GE
I2 O LDCE
I3
I4
I0 D Q
I1 G outputConv_OBUF[10976]_inst
I O
I2 O GE
I3 LDCE OBUF
I4
I5 1
I0
LUT6
7
I1
I2 O 1
I3 7
I0 0 I1
I4
I1 I2 O
LUT5
6
I2 O I3
0
I3 I4
I4 LUT5
I5 0 outputConv_reg[113]_i_7
I0 0
LUT6 I0
6
outputConv_reg[2282]_i_4 I1 O 6
I1 O
I0 I2
I1 I3 7
I0 I3
I2 O LUT4
I1 O LUT4
I3
I3 1 I0
LUT5 I0
LUT4 6
7 I1 O
I1
I2 O 7
I0 6 I3
I1 O LUT4
0
I0 I4
I2
I1 O LUT5
LUT4 I0
LUT3 0
I0 7
6 I1
I1 O
I2 O
outputConv_reg[234]_i_6 I2 6
7 I3
I0 I3 0
I4
I1 O LUT4
LUT5
I3 I0 0
I0
LUT4 I1 O 6
6 I1 O
I2
I2
LUT3
7
I3
LUT4
7 I0
I1 O I0 7
I1
I2 I1 O
6 I2 O
I3 I2 6
I3
LUT4 LUT3
0
I4
I1 O I0 0
I0
I2 I1 O 6
6 I1 O
I3 I2
I2
LUT4 LUT3
7
I3
LUT4
I0 1
7 I0
I1 7
I1
I2 O
6 I2 O
I3 6
0 I3
I4 0
I4
LUT5
LUT5
I0
I1
outputConv_reg[11264] I2 O
CLR I3
94
D Q I4
G LUT5
GE
I O
CLR OBUF
65
D Q outputConv_OBUF[11840]_inst
I O
G
GE OBUF
I O
CLR OBUF
D Q
G
GE
LDCE
0
I0
6
I1 O
I2
7
I3
LUT4
7
I0
I1 O
6
I2
LUT3
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
0
I0
6
I1 O
I2
7
I3
LUT4
7
I0
I1 O
6
I2
LUT3
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
0
I0
6
I1 O
I2
7
I3
LUT4
7
I0
I1 O
6
I2
LUT3
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
0
I0
6
I1 O
I2
7
I3
LUT4
7
I0
I1 O
6
I2
LUT3
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
0
I0
6
I1 O
I2
7
I3
LUT4
2
I0
1
I1
0
I2 O
6
I3
I4
7
I5
LUT6
1
I0
7
I1
I2 O
6
I3
0
I4
LUT5
0
I0
6
I1 O
I2
7
I3
LUT4
7
I0
I1 O
6
I2
LUT3
7
I0
I1 O
6
I2
LUT3
4
I0
2
I1
1
I2 O
0
I3
3
I4
LUT5
7
I0
I1 O
6
I2
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7
I0
I1 O
6
I2
LUT3
3
I0
0
I1 O
1
I2
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LUT4
7
I0
I1 O
6
I2
LUT3
7
I0
I1 O
6
I2
LUT3
Architecture 4: Sequential Convolution with 14 conv units (for one filter of the
first convolution layer LeNet)
This architecture contains the improvements of all the previous architectures
(receptive field array is calculated for the selected pixels only). The number of
conv units is equal to half the number of pixels of a single row of the output
image: 14 units (for the first convolution layer of LeNet). The result appears
after 1456 clock cycles.
Architecture 5: Sequential Convolution with 14 conv units with half precision
floating point (16 bits)
Finally, I changed the floating-point precision from 32 bits to lower the
utilization in part 5 and reach the lowest utilization possible for the con layer
with multiple filters.
This comparison between architectures is done on module of the conv layer
single filter with the sizes and number of the first convolution layer.
Arch 1 Arch 2 Arch 3 Arch 4 Arch 5
Floating Point
32 bits 32 bits 32 bits 32 bits 16 bits
Precision
Number of
clock cycles
need to 26 728 728 1456 1456
output the
result
Number of
1712256 177300 135176 117521 48422
LUTS
Utilization on
707.54% 73.26% 55.86% 48.48% 19.98%
the KCU
Utilization on
738.04% 77.09% 58.77% 51.10% 21.05%
the ZCU
Note: the reports and codes for each architecture can be found in \Extra Convolution\ folder
Some reports show the synthesis on the PYNQ board and I used the number of LUTS to calculate the
utilization for the KCU and ZCU boards.
Part 2
TanH Activation
Ahmed Ezzat
Name: Ahmed Mohammed Ezzat ID: 1162033
Logic-2 tanh Function

Section1
Design
Mainly there is a whole layer which is in the module “ UsingTheTanh.v” , it controls the smaller
processing unit “HyperBolicTangent.v”.
How It Works
Mainly to save some hardware but in the opposite side clock cycles will be extended.
In the Hyperbolic Tangent:
I divide the operations into 3 Multipliers and 1 Adder.
First, the “MSquaring” is for getting the incrementing term of the x term which is x^2.
Second, the “MGeneratingXterm” is for multiplying the present x term with its next one.
Third, the “MTheCoefficientTerm” is for multiplying each corresponding final X term with its coefficient
which here I chose 4 terms for good taylor expansion coeff.
Fourth, the last step of our operation is to add each resulting term to its previous one.
Section 4&5
This is the simulation of an inrange floating number: it needs 5 clock cycles
The input here is 0.600000023842 in floating numbers is 00111111000110011001100110011010
The output here:
1. Actual is 0.53704 in floating is 00111111000010010111101101110100

2. Experimental is 0.53685 in float 00111111000010010110111101111011
Which is a very slight difference regarding Taylor approx.
Now tanh converges at |x|>pi/2 so in this case I made a constant assigned value to numbers in
convergence region which is 1 or -1
Here is an example
This is the simulation of an out of range floating number: it needs only 1 clock cycle
Here the input is 3 in floating 01000000010000000000000000000000:
1- The Actual output is 0.995

2- The simulation output is 1 because it lies in the convergence region
Now here comes the tanh layer:
Regarding the layer, the input is in kernels in the size of 25 inputs:
Post Synthesis-Timing Simulation
Here my input is:
InputNumbers = [0.6,0.5,3.2,1.4,2,1,0,0.5,-0.4,-0.5,-0.57,0.57,0.3,0.2,0.112,
0.2,-0.2,-0.5,-0.9,-0.567,-0.43,0.5,0.7,0.86543,0.4345,]
In IEEE Form:
00111111000110011001100110011010_00111111000000000000000000000000_01000000010011001
100110011001101_00111111101100110011001100110011_01000000000000000000000000000000_0
0111111100000000000000000000000_00000000000000000000000000000000_001111110000000000
00000000000000_10111110110011001100110011001101_10111111000000000000000000000000_10
111111000100011110101110000101_00111111000100011110101110000101_0011111010011001100
1100110011010_00111110010011001100110011001101_00111101111001010110000001000010_001
11110010011001100110011001101_10111110010011001100110011001101_10111111000000000000
000000000000_10111111011001100110011001100110_10111111000100010010011011101001_1011
1110110111000010100011110110_00111111000000000000000000000000_001111110011001100110
01100110011_00111111010111011000110011010010_00111110110111100111011011001001
As said before,
The number of clock cycles is 1 clock for each converged input and 5 cycles for each non-converged
input so it varies according to the input array
And here are the Outputs:
Simulation Output is =
00111111000010010110111101111011_00111110111011001001010110001011_00111111100000000
000000000000000_00111111001000100010111101000110_00111111100000000000000000000000_0
0111111001111101111101111110001_00000000000000000000000000000000_001111101110110010
01010110001011_10111110110000101000011111111000_10111110111011001001010110001011_10
111111000000111110011010001011_00111111000000111110011010001011_0011111010010101001
0011011100000_00111110010010100001110011000010_00111101111001000110101111110101_001
11110010010100001110011000010_10111110010010100001110011000010_10111110111011001001
010110001011_10111111001101011011110101000011_10111111000000110101011001001011_1011
1110110011111000010011110000_00111110111011001001010110001011_001111110001101010000
11110011001_00111111001100011100100100101110_00111110110100010111000011010101
And in decimals:
Outputs=0.536857306957,0.462078422308,1.0,0.633533835411,1.0,0.746031820774,0,0.46207842230
8,-0.379943609238,-0.462078422308
,-0.51523655653,0.51523655653,0.291312217712,0.197375327349,0.111534036696,0.197375327349
,-0.197375327349,-0.462078422308,-0.709919154644,-0.513035476208
,-0.405311107635,0.462078422308,0.603631556034,0.694476008415,0.409063965082
And the Actual Outputs are:
Actual Output is =
00111111000010010111110000010101_00111110111011001001101010011111_00111111011111110
010011010010100_00111111011000101010011001101000_00111111011101101100101010000011_0
0111111010000101111011111010110_00000000000000000000000000000000_001111101110110010
01101010011111_10111110110000101000100010101100_10111110111011001001101010011111_10
111111000000111110111010010110_00111111000000111110111010010110_0011111010010101001
0011011101101_00111110010010100001110011000010_00111101111001000110101111110100_001
11110010010100001110011000010_10111110010010100001110011000010_10111110111011001001
101010011111_10111111001101110101111101001100_10111111000000110101110111111001_1011
1110110011111000011001000110_00111110111011001001101010011111_001111110001101010110
11111011001_00111111001100101111010010011001_00111110110100010111001001001100
And in decimals:
Outputs = 0.53704957,0.46211716,0.9966824,0.88535165,0.96402758,0.76159416,0,0.46211716,-
0.37994896,-0.46211716,-0.51535928,0.51535928,0.29131261,0.19737532,0.11153403,0.19737532,-
0.19737532,-0.46211716,-0.71629787,-0.51315266,-
0.40532131,0.46211716,0.60436778,0.69904478,0.40907515
Section 6
Now here comes the Utilization of One kernel:
25 inputs kernel
And to be more real the utilization of a full 748 pixels image is:
TCL Console:
These warning mean nothing I think these are due to constant driven parameters.
File Description Table:
HyperBolicTangent.v It is considered the processing unit of the layer

which performs the tanh operation per input
[32bits]
HyperBolicTangent_TB.v It is the test bench for the tanh operation and
verifying that it is true and working either in
convergence or not
UsingTheTanh.v It is the tanh layer which takes a whole array of
inputs and produces a whole array of outputs
UsingTheTanh-TB.v It is the test bench for the layer of the tanh and
its verification of how it works on an array of
inputs
Parallelism here will over utilize the module and will result in some complications, so I preferred not to
implement it in the tanh layer. Also the utilization of my module for a whole input image is 22K LUTs
which is small compared to other layers so it is enough I think.
Section 7
The shown schematic shows all modules, Using the tanh module and hyperbolic tangent
module and how they are connected together within the controlling layer:
The Hyperbolic tangent uses 1700 LUT’s, Multiplier uses 340 LUT’s, Adder uses 540 LUTs
and finally the Using the tanh uses at 784 input 22066 LUT’s.
The final number of LUT’s can be reduced if the precision of the tanh reduced to 16 bit
without a big loss in the accuracy of the results.
I actually reduced the input bits from 32-bits to 16-bits and Part 5 now uses them
Part 3
SoftMax Activation
Omar Essam
SoftMax Report
I will discuss three different implementations of softmax and make a comparison.
1. Design 1: softmax module
2. Design 2: softmax_1 module
3. Design 3: softmax_2 module.
All Answers were double checked with a python script and are correct.
Design 1
1- Block Diagram:
Design Description: 10 exponent units, 1 floating adder , 1 multiplier, 1 division unit.

Description : 10 parallel exponent units to calculate exponent of 10 inputs, then 1 floating adder will used with
10 clock cycles to calculate their sum and send an enable signal to Newton Raphson module which will
calculate the Reciprocal after the Newton Raphson module sends the ackDiv signal , the 1 multiplier will be
used for 10 clock cycles to multiply the 10 exponents with the 10 reciprocals.
5- Clock Cycles: 31 clock cycles as shown below. ackSoft is triggered
7 – Synthesis schematic
The shown schematic shows all modules , exponent and reciprocal
and adder and multiplier and how they are connected together
with extra sequential circuits. : The exponent uses 1356 LUTs ,
Reciprocal (Newton Raphson) is 2600 LUTs , Multiplication is 340,
Addition is 540. Which is the reason the design uses 17k luts.
The overall design luts could be improved If the base unit ,
Multipliers and adders are smaller
6- Synthesis Report: 17532/53200 LUTs 32.95% utilization.
4 - Timing Diagram
Design 2
Design Description: 10 exponent units, 10 floating adder , 1 multiplier, 1 division unit.
5- Clock Cycles: 22 clock cycles as shown below, ackSoft is triggered
Description: same as Design 1 the only difference is 10 adders are generated to calculate the sum in one cycle.
6 -Synthesis Report: 22417/53200 LUTs 42.14% utilization
4- Timing Diagram:
Design 3
Design Description: Design Description: 10 exponent units, 10 floating adder , 10 multiplier, 1 division unit.
5- Clock Cycles : 11 cycles as shown. ackSoft is triggered
Description: Same as Design 2 but 10 parallel multipliers are used to multiply with the Reciprocal in one clock
cycle.
6- Synthesis Report: 25141/53200 47.26% utlization

4- Timing Diagram
Completion of part 4: Verification that the design is working

In this section I will discuss how I verified that the design is working using python scripts and Floating Point to
IEEE converter. https://www.h-schmidt.net/FloatConverter/IEEE754.html
The 10 inputs we will use to verify are 0.2 -0.2 1.2 1.3 -0.9 0.3 3.1 -0.02 1.11
0.323
The input is then run through the softmax.py file and the input binary string which is the input of the module
in the post synthesis simulation is written to log.txt.
In our case the input string is
0011111001001100110011001100110110111110010011001100110011001101001111111001100110011001
1001101000111111101001100110011001100110101111110110011001100110011001100011111010011001
1001100110011010010000000100011001100110011001101011110010100011110101110000101000111111
10001110000101000111101100111110101001010110000001000010
In the figure below is the output of the system after the ackSoft signal is High.
Hexadecimal result:
3d055aa33cb2c7a53db533933dc83a613c31989a3d1361073f1198cd3cd609d03da59f083d16ceda
Binary result:
0011110100000101010110101010001100111100101100101100011110100101001111011011010100110011
1001001100111101110010000011101001100001001111000011000110011000100110100011110100010011
0110000100000111001111110001000110011000110011010011110011010110000010011101000000111101
10100101100111110000100000111101000101101100111011011010
The binary result is then used in the split.py file to get 10 IEEE 32 bit floating point numbers.
The result of splitting this string is ['00111101000001010101101010100011',
'00111100101100101100011110100101', '00111101101101010011001110010011',
'00111101110010000011101001100001', '00111100001100011001100010011010',
'00111101000100110110000100000111',
'00111111000100011001100011001101', '00111100110101100000100111010000',
'00111101101001011001111100001000',
'00111101000101101100111011011010']
Which corresponds to these numbers
[0.0325571410358, 0.0218237135559, 0.0884772762656, 0.097767598927, 0.0108396057039,
0.0359812043607, 0.56873780489, 0.0261277258396, 0.0808697342873, 0.0368183627725]
Now after running the softmax.py we get two results , first is the softmax numbers if we use math.exponent,
and softmax if we use taylor.
Here is the results If we use actual exponent function.
RealSoftmax is [0.03182415 0.02133236 0.086507 0.09560502 0.01059334 0.03517112
0.57837666 0.02553948 0.07906144 0.03598943]
Here is the results if we use taylor exponent used in the design.
TaySoftmax is [0.03255714 0.0218237 0.08847725 0.09776757 0.0108396 0.0359812
0.56873776 0.02612771 0.08086971 0.03681836]
The Tay softmax results are very similar to the real softmax considering the approximation we used for the
exponent function. And also the Tay softmax results are the same as the output of the softmax module in the
post synthesis simulation.
Part 4
Average Pool
Ahmed Abdulkader
Part 4-Average Pooling
1) Block Diagrams
Averaging Unit
numC numD const(1/4)
numA
Avg
numB
floatAdd floatAdd floatAdd floatMult
Average Pool layer
AvgU
AvgU
image
AvgPoolOut
AvgU
....
AvgU
Average Pool Multi Layer
image Result
AvgPoolOut
AvgPoolSingle
2) Verilog Codes
AvgUnit.v
AvgPoolSingle.v
AvgPoolMulti.v
3) Testbench Codes
AvgUnit_tb.v
AvgPoolSingle_tb.v
AvgPoolMulti_tb.v
AvgPoolMulti_tb2.v
4) Screenshots:
i. AverageUnit
ii. Single Average Layer

iii. Multi Average Layer
1. Test Layer 1
2. Test Layer 2
All results were verified using the simulated Average Pool Layer run on
python. The Simulations are run on two test benches (TB1 and TB2).
You can find the python script in the folder Python Tests called
‘AvgPoolTest1.py’ and ‘AvgPoolTest2.py’. All result comparisons are
also listed out on the Convolution1Test sheet on the attached CNNtest
excel file (CNNtest.xlsx).
b. Post Synthesis Timing for the basic avgUnit:
(as agreed upon post timing for larger layers of hardware are not achievable with our hardware capabilities)

a. Average Unit
0 Clock Cycles, The circuit is combinational
b. Single Pool Layer
0 Clock Cycles, All Combinational Units in Parallel
c. Multi Pool Layer
Clock Cycles equal to the depth
6 for the first AvgPool
16 for the second AvgPool
Avg Unit
Avg Pool Layer

The Synthesis Schematic is attached on the next page.
The least number of LUTs is on the simple averaging unit, that has only 3
adders and a multiplier. The Number of LUTs significantly increases in
the single layer because it’s consistent of a lot of Avg Units stacked
together in parallel. The number does not differ a lot for the multi layer,
since it’s just a single layer with sequential input, therefore with almost
identical LUTs.
8) Answers to questions:
No questions were asked in AvgPool description
AvgOut_OBUF[0]_inst
0 I O 0
AvgOut[15:0]
OBUF
AvgOut_OBUF[1]_inst
1 I O 1
OBUF
AvgOut_OBUF[2]_inst
2 I O 2
OBUF
AvgOut_OBUF[3]_inst
3 I O 3
FADD2
OBUF
exponent1
AvgOut_OBUF[4]_inst
exponent1_0 4 I O 4
exponent1_1
OBUF
exponent1_2
numA_IBUF[0]_inst AvgOut_OBUF[5]_inst
exponent1_3 5 I O 5
0 I O 0 exponent1_4
numA[15:0] OBUF
IBUF exponent1_5
AvgOut_OBUF[6]_inst
fractionB[10:0] exponent1_6 6 I O 6
numA_IBUF[1]_inst FADD1 ...
numA[1] exponent1_7
OBUF
1 I O cout0[6:0] numA[1]_0 exponent1_8
AvgOut_OBUF[7]_inst
IBUF cout00_in[6:0] numA[7] exponent1_9 7 I O 7
exponent1_42 numA[7]_0 exponent1_10

numA_IBUF[2]_inst OBUF
exponent1_43 numA[12] exponent1_11
AvgOut_OBUF[8]_inst
2 I O exponent1_44 numA[12]_0 exponent1_12 8 I O 8
IBUF exponent1_45 numA[13][7:0] exponent1_13

OBUF
numA[1] numA[13]_0[7:0] exponent1_14
numA[1]_0 numA_IBUF[15:0] exponent1_15 0 I O 9
...
3 I O 3 numA[6] numB[3] exponent1_16
OBUF
IBUF numA[6]_0 numB[3]_0 exponent1_17
AvgOut_OBUF[10]_inst
numA[7] numB[3]_1[3:0] exponent1_18 1 I O 10
numA_IBUF[4]_inst
numA[8] numB[3]_2[2:0] exponent1_19
OBUF
4 I O 4 numA[8]_0 numB[3]_3[2:0] exponent1_20
IBUF numA[8]_1 numB[3]_4[1:0] exponent1_21 2 I O 11
numA[8]_2 numB[4] exponent1_22

numA[8]_3 numB[7] exponent1_23
5 I O 5 numA[8]_4 numB[11] exponent1_24 3 I O 12
IBUF numA[8]_5 numB[12][1:0] exponent1_25

OBUF
numA[8]_6 numB_IBUF[10:0] exponent1_26
numA[8]_7 A[9:0] numC[11] exponent1_27 9 I O 13
6 I O 6 numA[8]_8 AvgOut[8] numC[14] exponent1_28

OBUF
IBUF numA[8]_9 AvgOut[8]_0 numC_IBUF exponent1_29
numA[8]_10 AvgOut[13] p_1_in[10:0] exponent1_30 10 I O 14
numA_IBUF[7]_inst
numA[8]_11 AvgOut[13]_0 exponent1_31
OBUF
7 I O 7 numA[8]_12 AvgOut[13]_1 exponent1_32
IBUF numA[8]_13 AvgOut[13]_2 exponent1_33 4 I O 15
numA[8]_14 AvgOut[13]_3 exponent1_34

numA[8]_15 AvgOut[14] exponent1_35
8 I O 8 numA[8]_16 AvgOut[14]_0 exponent1_36
IBUF numA[8]_17 AvgOut[14]_1 exponent1_37
numA[8]_18 AvgOut[14]_2 floatAdd_0

numA_IBUF[9]_inst
numA[8]_19 AvgOut[14]_3
9 I O 9 numA[8]_20 AvgOut[14]_4
IBUF numA[8]_21 AvgOut[14]_5
numA[11] AvgOut_OBUF[4:0]
numA_IBUF[10]_inst
numA[12] S[7:0]
10 I O 10 numA[12]_0 exponent1
IBUF numA[12]_1 exponent1_0

numA[12]_2 exponent1_1
numA_IBUF[11]_inst
11 I O 11 numA[13] exponent1_3
numA_IBUF[12]_inst
numA[13]_2 exponent1_6 2
12 I O 12 numA[13]_3 exponent1_7 10
IBUF numA[13]_4 exponent1_8 3
numA[13]_5 exponent1_9[7:0]
numA_IBUF[13]_inst
13 I O 13 numA[13]_7 exponent1_11
numA_IBUF[14]_inst
numA_IBUF[15]_inst
numB_IBUF[0]_inst FADD3
numA[14] exponent1_22
0 I O 0 ... numA_IBUF[15:0] exponent1_23 AvgOut[8]

numB[15:0]
IBUF numB[3] exponent1_24 AvgOut[13]
numB[3]_0 exponent1_25 AvgOut[13]_0

numB_IBUF[1]_inst
numB[7] exponent1_26 AvgOut[13]_1
1 I O numB[8] exponent1_27 AvgOut[13]_2
IBUF numB[8]_0 exponent1_28[3:0] AvgOut[14]
numB[8]_1 exponent1_29[1:0] S[7:0] AvgOut[14]_0

numB_IBUF[2]_inst
numB[8]_2 exponent1_30[1:0] ... fractionB[10:0] AvgOut[14]_1
...
2 I O numB[8]_3 exponent1_31[2:0] numA[8] AvgOut[14]_2
IBUF numB[12] exponent1_32[6:0] numA[8]_0 AvgOut[14]_3
numB[12]_0 exponent1_33[6:0] numA[8]_1 cout0[6:0]

numB_IBUF[3]_inst
numB[12]_1 exponent1_34[1:0] numA[8]_2 cout00_in[6:0]
3 I O 3 numB[12]_2 exponent1_35[2:0] numA[8]_3 exponent1
IBUF numB[12]_3 exponent1_36[1:0] numA[8]_4 exponent1_0
numB[12]_4 exponent1_37[2:0] numA[8]_5 exponent1_1

numB_IBUF[4]_inst
numB[12]_5 exponent1_38[7:0] numA[8]_6 exponent1_2
4 I O numB[12]_6 exponent1_39[7:0] numA[8]_7 exponent1_3
IBUF numB[15] exponent1_40[1:0] numA[8]_8 exponent1_4
... numB_IBUF[15:0] exponent1_41[2:0] numA[8]_9 exponent1_5

numB_IBUF[5]_inst
numC[11] fractionB numA[8]_10 exponent1_6
5 I O numC[11]_0 fractionB_0[9:0] numA[8]_11 exponent1_7
IBUF numC[11]_1 fractionB_1[8:0] numA[8]_12 exponent1_8
numC[11]_2 p_1_in[10:0] numA[8]_13 exponent1_9

numB_IBUF[6]_inst
numC[11]_3 numA[8]_14 exponent1_10
6 I O 6 numC[11]_4 numA[8]_15 exponent1_11
IBUF numC[11]_5 numA[8]_16 exponent1_12

numB_IBUF[7]_inst
7 I O 7 numC[11]_8 numA[12] exponent1_15
IBUF numC[11]_9 numA[13] exponent1_16

numB_IBUF[8]_inst
numC[11]_11 numA_IBUF[15:0] exponent1_18
...
8 I O numC[11]_12 numB[0][1:0] exponent1_19
IBUF numC[11]_13 numB[0]_0 exponent1_20

numC[11]_14 numB[2][6:0] exponent1_21
numB_IBUF[9]_inst
numC[14] numB[2]_0[1:0] exponent1_22
9 I O numC_IBUF[15:0] numB[2]_1[6:0] exponent1_23
IBUF numD[6] numB[8] exponent1_24
numD[6]_0 numB[8]_0 exponent1_25

numB_IBUF[10]_inst
numD[6]_1 numB[8]_1 exponent1_26
10 I O numD[15] numB[8]_2 exponent1_27
IBUF numD_IBUF[15:0] numB[8]_3 exponent1_28
floatAdd numB[8]_4 exponent1_29

numB_IBUF[11]_inst
numB[8]_5 exponent1_30
11 I O numB[8]_6[2:0] exponent1_31
IBUF numB[8]_7[2:0] exponent1_32
numB[12] exponent1_33
numB_IBUF[12]_inst
... numB_IBUF[15:0] exponent1_34
12 I O numC_IBUF[15:0] exponent1_35
IBUF 1:0 numD_IBUF[2:0] exponent1_36

... ...
p_1_in[10:0] exponent1_37
numB_IBUF[13]_inst
exponent1_38
13 I O exponent1_39
IBUF exponent1_40
exponent1_41
numB_IBUF[14]_inst
exponent1_42
14 I O exponent1_43
IBUF floatAdd_1
numB_IBUF[15]_inst
15 I O
IBUF
numC_IBUF[0]_inst
0 I O 0
numC[15:0]
IBUF
numC_IBUF[1]_inst
1 I O 1
IBUF
numC_IBUF[2]_inst
2 I O 2
IBUF
numC_IBUF[3]_inst
3 I O 3
IBUF
numC_IBUF[4]_inst
4 I O 4
IBUF
numC_IBUF[5]_inst
5 I O 5
IBUF
numC_IBUF[6]_inst
6 I O 6
IBUF
numC_IBUF[7]_inst
7 I O 7
IBUF
numC_IBUF[8]_inst
8 I O 8
IBUF
numC_IBUF[9]_inst
9 I O 9
IBUF
numC_IBUF[10]_inst
10 I O 10
IBUF
numC_IBUF[11]_inst
11 I O 11
IBUF
numC_IBUF[12]_inst
12 I O 12
FM
IBUF
A[9:0] AvgOut[9]
numC_IBUF[13]_inst
numA[13] AvgOut[12]
13 I O 13 numA_IBUF[1:0] AvgOut[13]
IBUF numB[0] AvgOut[13]_0
numB[8] AvgOut_OBUF[10:0]
numC_IBUF[14]_inst
14 I O 14 numB[8]_1 exponent1_1
IBUF numB[8]_2 exponent1_2
numC_IBUF[15]_inst
numB[12] exponent1_4
15 I O numB_IBUF[2:0] exponent1_5
IBUF numD_IBUF[15:0]
numD_IBUF[0]_inst floatMult
0 I O 0
numD[15:0]
IBUF
numD_IBUF[1]_inst
1 I O 1
IBUF
numD_IBUF[2]_inst
2 I O 2
IBUF
numD_IBUF[3]_inst
3 I O 3
IBUF
numD_IBUF[4]_inst
4 I O 4
IBUF
numD_IBUF[5]_inst
5 I O 5
IBUF
numD_IBUF[6]_inst
6 I O 6
IBUF
numD_IBUF[7]_inst
7 I O 7
IBUF
numD_IBUF[8]_inst
8 I O 8
IBUF
numD_IBUF[9]_inst
9 I O 9
IBUF
numD_IBUF[10]_inst
10 I O 10
IBUF
numD_IBUF[11]_inst
11 I O 11
IBUF
numD_IBUF[12]_inst
12 I O 12
IBUF
numD_IBUF[13]_inst
13 I O 13
IBUF
numD_IBUF[14]_inst
14 I O 14
IBUF
numD_IBUF[15]_inst
15 I O
IBUF
exponent1_i_115__139
I0 O
I1
LUT2
I0
I1 O
I2
LUT3
I0
I1
I2 O
I3
I4
I5 exponent1_i_54__139
LUT6 I0
exponent1_i_118__139 I1
I0 I2 O
I1 O I3
I2 I4
I3 I5
LUT4 LUT6
I0
I1
I2 O
I3
I4
I5
LUT6
I0
I1
I2 O
0
I3
3
I4
1
I5
LUT6
I0
I1
I2 O
I3
I4
I5
LUT6
I0
2
I1
7
I2 O
I3
I4
I5
LUT6
I0
4
I1
3
I2 O
5
I3
I4
I5
LUT6
I0
I1
I2 O
I3
I4
LUT5
I0
I1
I2 O
I4 I0
LUT5 I1
I2 O
I0 O I4
I1 I5
LUT2 LUT6
exponent1_i_78__139
I0
I0 I2 O
I1 I3
I2 O I4
I3 I5
I4 LUT6
LUT6 I0
I1
exponent1_i_185__139 I2 O
I0 I3
I1 I4
I2 O I5
4 LUT6
I3
3
I4
3
I5
LUT6
I0 O
I1
LUT2
I0
I1 O
I2
LUT3
exponent1_i_207__139 exponent1_i_102__139
I0 I0
I1 I1
I2 O I2 O
I3 I3
I4 I4
I5 I5
LUT6 LUT6
I0
I1
I2 O
I3
I4
LUT5
I0
I1
I2 O
I3
I4
I5
LUT6
I0
38
I1
33
I2 O
2
I3
3
I4
1
I5
LUT6
aPoolOut_OBUF[1136]_inst_i_193
2
I0 O
2
I1
LUT2
1 1
I0 O
1
I1
LUT2
FADD1/exponent1_i_240__70
CI
CI_TOP CO[7:0]
... 7,5 DI[7:0] O[7:0]
S[7:0]
CARRY8 FADD1/exponent1_i_226__70
7
CI
CI_TOP CO[7:0]
FADD1/exponent1_i_325__70 2:0 DI[7:0] O[7:0]

1
I0 O 1 2:0 S[7:0]
1 CARRY8
I1
LUT2
exponent1_i_324__70
2 2
I0 O
I1
LUT2
exponent1_i_326__70
I0
2
I1
0
I2 O
I3
I4
LUT5
I0
2
I1
0
I2 O
I3
I4
LUT5
I0
I1
2
I2 O
I3
32
I4
LUT5
I0
2 0
I1 O
I2
I3
LUT4
I0
I1
7
I2 O
I3
I4
I5
LUT6
I0
I1
6
I2 O
I3
I4
I5
LUT6
I0
I1
5
I2 O
I3
I4
31
I5
LUT6
I0
I1
4
I2 O
I3
I4
I5
LUT6
I0
I1
3
I2 O
I3
I4
I5
LUT6
I0 I1
2
I1 I2 O
I2 O I3
I3 I4
30
I4 I5
I5 LUT6
LUT6 aPoolOut_OBUF[1136]_inst_i_290
I0 O I1
1
I1 I2 O
LUT2 I3
0 29
I0 I5
38 LUT6
I1
0
I2 O aPoolOut_OBUF[1136]_inst_i_291
I3 I0
I4 I1
0
I5 I2 O
LUT6 I3
33 28
I0 I5
38 LUT6
I1
0
I2 O exponent1_i_217__139
3 6
I3 I0
1 6
I4 I1
LUT5 I2 O
3
I3
38
3
I0 I5
I1 LUT6
0
I3 I0
38
I4 I1
0
I5 I2 O
LUT6 I3
I4
I0 LUT6
I2 O I0
I3 I1
I4 I2 O
I5 I3
LUT6 I4
4 LUT6
I0
3
5 7
I2 O I0
33 7
I3 I1
38
I4 I2 O
LUT5 3
I3
38
3
I0 I5
I1 LUT6
23
I3 I0
I4 I1
LUT5 I2 O
I3
I4
I0 LUT6
I1
33
I3 I0
38
I4 I1
LUT5 6
I2 O
3
I3
7
I4
LUT5
exponent1_i_313__139 aPoolOut_OBUF[1136]_inst_i_295
4 4
I0 I0 O
4
I1 O I1
I2 LUT2
I3
3 3
3 FADD1/aPoolOut_OBUF[1136]_inst_i_90
I0 I1 7
CI
I1 LUT2
CI_TOP CO[7:0]
I2 O
2:0 DI[7:0] O[7:0]
I3 2:0
FADD1/aPoolOut_OBUF[1136]_inst_i_189 S[7:0]
I4
CI CARRY8
I5
CI_TOP CO[7:0]
LUT6
DI[7:0] O[7:0]
S[7:0] 1 1
I0 I0 O
CARRY8
1
I1 I1
I2 O LUT2
I3 FADD1/aPoolOut_OBUF[1136]_inst_i_200
2 2
I4 I0 O
LUT5 aPoolOut_OBUF[2240]_inst_i_28 I1
3 LUT2
I0
38
3
I0 I2 aPoolOut_OBUF[1136]_inst_i_202
I1 LUT3 I0
2
I2 O I1
0
I3 I2 O
I4 I3
I5 I4
LUT6 aPoolOut_OBUF[2240]_inst_i_54 LUT5
I0
2
I1
0
I2 O
I3
I4
FADD1/exponent1_i_341__70 I5
6 6 LUT6
I0 O
6
I1 aPoolOut_OBUF[2240]_inst_i_63
LUT2 I0
I1
1
FADD1/exponent1_i_343__70 I2 O
4 4 2
I0 O I3
4
I1 I4
LUT2 1
I5
FADD1/exponent1_i_344__70 LUT6
3 3
I0 O
3
LUT2 0
I0 O
FADD1/exponent1_i_345__70 LUT1
2 2
2 6
I1 I0 O
LUT2 LUT1
FADD1/exponent1_i_346__70 aPoolOut_OBUF[2240]_inst_i_158
1 1
I0 O I0
1
I1 I1
LUT2 2
I2 O
FADD1/exponent1_i_347__70 I3
0 0
I0 O I4
0 2
I1 I5
LUT2 LUT6
7
I0 O I0
LUT1 I1
1
5
I0 O I3
LUT1 I4
1
7 LUT6
I0 O
7
LUT2 I0
0
5 0
I0 O I2
5 LUT3
I1
LUT2
7 7
I0 O
7
aPoolOut_OBUF[1136]_inst_i_190 I1
2 LUT2
I0 O
6
I0 O
6
I1
LUT2
I0
0
I1 O
0
I2
I3
LUT4
33
I0
38
33
I0 I2
38 LUT3
I1
7
I2 O
3
0 1
I4 I0
LUT5 38
aPoolOut_OBUF[1136]_inst_i_191 I1 O
1
I0 I2
I1 LUT3
1
I2 O
exponent1_i_215__139 I3 FADD1/aPoolOut_OBUF[1136]_inst_i_292
7 7
I0 I4 I0 O
I1 I5 I1
I2 O LUT6 LUT2
I3 aPoolOut_OBUF[1136]_inst_i_192 FADD1/aPoolOut_OBUF[1136]_inst_i_294
0 5 5
I4 I0 O I0 O
I5 LUT1 I1
LUT6 LUT2
I0 aPoolOut_OBUF[1136]_inst_i_307 I1
I1 I0 I2 O
32
I2 O I1 I3
I3 I2 O I4
I4 I3 LUT5
I5 I4
LUT6 I5 aPoolOut_OBUF[1136]_inst_i_308
LUT6 7
I0 O
aPoolOut_OBUF[1136]_inst_i_356 LUT1
I0
I0 I2 O
I1 I3
I2 O I4
I3 LUT5 aPoolOut_OBUF[1136]_inst_i_309
5
I4 I0 O
LUT5 LUT1
aPoolOut_OBUF[1136]_inst_i_304 aPoolOut_OBUF[1136]_inst_i_358
I0 I0
32
I1 I1
I2 O I2 O exponent1_i_337__70
36
I3 I3 I0
2
aPoolOut_OBUF[1136]_inst_i_300 I4 I4 I1
2 LUT5 LUT5 2
I0 I2 O
I1 I3
I2 O aPoolOut_OBUF[1136]_inst_i_359 I4
I3 I0 I5
I4 I1 LUT6
32 31
I5 I2 O
LUT6 aPoolOut_OBUF[1136]_inst_i_305 I3 exponent1_i_333__70
I0 I4 I0
2
I1 I5 I1
LUT6 6
I2 O I2 O
I0 I5 I1 I5
I1 LUT6 I2 O LUT6
I2 O I3
I3 I4 exponent1_i_335__70
I4 I5 I0
LUT6 2
I5 I1
LUT6 4
I2 O
30
I0 I4
aPoolOut_OBUF[1136]_inst_i_368 I1 I5
I0 I2 O LUT6
I1 I3 exponent1_i_336__70
I2 O I4 I0
2 FADD3/aPoolOut_OBUF[2240]_inst_i_20
I3 I5 I1 7
3 CI
I4 LUT6 I2 O
CI_TOP CO[7:0]
2:0 DI[7:0] O[7:0]
LUT6 aPoolOut_OBUF[1136]_inst_i_380 I0 I4 2:0
S[7:0]
I0 I1 I5
CARRY8
aPoolOut_OBUF[1136]_inst_i_369 I1 O I2 O LUT6
I0 I2 I3
I1 I3 I4 aPoolOut_OBUF[2240]_inst_i_56
LUT4 FADD3/aPoolOut_OBUF[2240]_inst_i_58
aPoolOut_OBUF[1136]_inst_i_302 I2 O I5 I0
32 CI
I0 O I3 LUT6 I1
CI_TOP CO[7:0] 1
I1 I4 aPoolOut_OBUF[1136]_inst_i_364 I2 O
DI[7:0] O[7:0] 2
LUT2 LUT5 I0 I3
30 S[7:0]
I1 I4
CARRY8
1
aPoolOut_OBUF[1136]_inst_i_381 I2 O I5
29 LUT6
I0 I3
I1 I4
exponent1_i_382__70 I2 O I5 aPoolOut_OBUF[1136]_inst_i_226
31 LUT6
I0 I3 I0
LUT5 24
I0 I2 O I2 O
I1 I3 I3
I2 O I4 I4
LUT5 25
I3 aPoolIn_IBUF[4513]_inst I5
I4 exponent1_i_383__70 LUT6
I O
I5 I0
LUT6 I1 exponent1_i_381__70 IBUF aPoolOut_OBUF[1136]_inst_i_228
aPoolOut_OBUF[1136]_inst_i_365 I2 O I0 I0
I0 I3 I1 exponent1_i_385__70 aPoolIn_IBUF[4515]_inst I1
2 6
I1 I4 I2 O I0 I2 O
LUT5 I O
I2 O I3 I1 I3
I3 exponent1_i_386__70 I4 I2 O IBUF I4
22
I4 I0 I5 I3 aPoolIn_IBUF[4517]_inst I5
I5 I1 LUT6 I4 LUT6
LUT6 37 I O
I2 O exponent1_i_384__70 I5 aPoolOut_OBUF[1136]_inst_i_229
37 LUT6 IBUF
I3 I0 I0
I4 I1 I1
2 5
I5 I2 O I2 O
LUT6 I3 I3
I4 I4
21
I5 I5
LUT6 aPoolIn_IBUF[4527]_inst LUT6
I O 34
I0
IBUF I1 O
I2
aPoolIn_IBUF[4532]_inst I3
LUT4
I O
IBUF 7
I0 O
7
I0 aPoolIn_IBUF[4533]_inst LUT2
I1 O exponent1_i_387__70 aPoolOut_OBUF[1136]_inst_i_312
I O 5
I2 I0 I0 O
IBUF 5
I3 I1 I1
LUT4 I2 O LUT2
I3 aPoolIn_IBUF[4541]_inst aPoolOut_OBUF[1136]_inst_i_317
0 0
I4 I0 O
I O 30 0
I5 I1
LUT6 IBUF LUT2
aPoolIn_IBUF[4543]_inst aPoolOut_OBUF[1136]_inst_i_319
I0
I O 28
I1 O
IBUF I2
LUT4
I O 22
aPoolOut_OBUF[1136]_inst_i_382 IBUF aPoolOut_OBUF[1136]_inst_i_366

28
I1 I1 O
I O 19
I2 O I2
I3 IBUF LUT3
LUT6 I1
I O 8
I2 O
IBUF I3
exponent1_i_239__139 aPoolIn_IBUF[4985]_inst I4
I0 I5
I O 6 LUT6
I1
I2 O IBUF
I3 aPoolIn_IBUF[4987]_inst
I O 4
I5 I0
LUT6 IBUF I1 O
I0 LUT3
exponent1_i_355__139 I2 I0
2
I0 I3 I1
LUT4 26
I1 O aPoolOut_OBUF[2240]_inst_i_149 I2 O
6
I2 I0 I3
I3 I1 O I4
LUT4 I2 aPoolOut_OBUF[2240]_inst_i_255 LUT5
exponent1_i_356__139 I3 I0 aPoolOut_OBUF[2240]_inst_i_105
0 LUT4
I0 I1 O I0
8 26 2
I1 aPoolOut_OBUF[2240]_inst_i_150 I2 I1 O
I2 O I0 I3 I2
I3 I1 O LUT4 LUT3
I4 I2 aPoolOut_OBUF[2240]_inst_i_124
4 33
I5 I3 I0
LUT6 LUT4 38
aPoolOut_OBUF[2240]_inst_i_287 I1 O
4 LUT3
4
I0 I1 I2 O aPoolOut_OBUF[2240]_inst_i_130
8
I1 O I2 O I3 I0
I2 I3 I4 I1
LUT3 I4 I5 I2 O
I5 LUT6 I3
aPoolOut_OBUF[2240]_inst_i_379 LUT6 aPoolOut_OBUF[2240]_inst_i_288 I4

I0 I0 I5
I1 O aPoolOut_OBUF[2240]_inst_i_360 I1 LUT6
3
I2 I0 I2 O FADD3/exponent1_i_161__139
4 4
I3 I1 I3 I0 O
LUT4 4
I2 O I4 I1
I3 I5 LUT2
I4 LUT6 FADD3/exponent1_i_162__139
3 3
aPoolOut_OBUF[2240]_inst_i_380 I5 I0 O
LUT6 3
I1 O aPoolOut_OBUF[2240]_inst_i_361 I0 LUT2
31
I2 I0 I1 FADD3/exponent1_i_163__139
2 2 2
I3 I1 I2 O I0 O
LUT4 2
I2 O I3 I1
aPoolOut_OBUF[2240]_inst_i_382 I3 I4 LUT2
28 30
LUT6 4 4
I1 I5 I0 O
LUT6 4
exponent1_i_246__139 I2 O aPoolOut_OBUF[2240]_inst_i_290 I1
2 LUT2
I0 I3 aPoolOut_OBUF[2240]_inst_i_362 I0
2 30
I1 I4 I0 I1 aPoolOut_OBUF[2240]_inst_i_141
1 3 3
I2 O I5 I1 I2 O I0 O
3 LUT6 3
I3 I2 O I3 I1
38 LUT2
I4 I3 I4
3 29
I5 exponent1_i_403__70 I4 I5 aPoolOut_OBUF[2240]_inst_i_142
LUT6 37 LUT6 2 2
I0 I5 I0 O
LUT6 2
I1 O aPoolIn_IBUF[8960]_inst I1
I2 aPoolOut_OBUF[2240]_inst_i_363 LUT2
I O 38
exponent1_i_310__139 I3 I0 exponent1_i_128__139
7 LUT4 IBUF
I0 I1 I0
38
I1 O I2 O aPoolIn_IBUF[8974]_inst I1
7
I2 I3 I2 O
LUT3 I O 35
I4 I3
exponent1_i_311__139 I5 IBUF I4
0 LUT6
exponent1_i_304__139 I0 aPoolOut_OBUF[2240]_inst_i_291 I5
38 LUT6
I0 I1 O aPoolOut_OBUF[2240]_inst_i_364 I0
3 0
I1 I2 I0 I1 exponent1_i_141__139
38 LUT3 30 0
I2 O I1 I2 O I0
3
I3 exponent1_i_317__139 I2 O I3 I1
1 2
I4 I0 I3 I4 I2 O
1 38 28
I5 I1 O I4 I5 I3
LUT6 2 LUT6
I2 I5 I4
LUT3 LUT6 aPoolIn_IBUF[8975]_inst I5
LUT6
I O 34
IBUF I0
0
I0 exponent1_i_404__70 I2 O
38
I1 I0 aPoolIn_IBUF[8982]_inst I3
0
I2 O I1 O I4
I O
I3 I2 I5
I4 I3 IBUF LUT6
I5 LUT4 exponent1_i_159__139
LUT6 6 6
I0 O
LUT2
I O
1 IBUF
I0 I0
9 0
I1 I1 O
5 0
I2 O I2
22 LUT4
I4 I0
LUT5 I1 exponent1_i_165__139
I2 O I0
24 0
I3 I1 O
0
I4 I2
LUT5 I3
LUT4
FADD3/aPoolOut_OBUF[2240]_inst_i_55
2 2
I0 O
I1
I0
25
I1 O
I2
23
I3
LUT4
exponent1_i_388__70
36
I0
I1
I2 O
I3
I4
I5
LUT6
36
2
I0 I1
2
exponent1_i_403__139 I1 I2 O
37
I0 I2 O I3
I1 O I3 I4
I3 I5 LUT6 I0
LUT4 LUT6 I1
35
exponent1_i_404__139 exponent1_i_388__139 I0 I3
36 2
I0 I0 I1 I4
1
I1 O I1 I2 O I5
I2 I2 O I3 LUT6
I3 I3 I4
LUT4 I4 I5
I5 LUT6
LUT6 exponent1_i_336__139 aPoolOut_OBUF[2240]_inst_i_311
6 6
exponent1_i_406__139 I0 I0 O
34 2 6
I0 I1 I1
3 LUT2
I1 I2 O
I2 O I3 aPoolOut_OBUF[2240]_inst_i_313
4 4
I3 exponent1_i_389__139 I4 I0 O
4
I4 I0 I5 I1
I5 I1 LUT6 LUT2
LUT6 I2 O exponent1_i_339__139 aPoolOut_OBUF[2240]_inst_i_314
34 3 3
I3 I0 I0 O
2 3
I4 I1 I1
0 LUT2
I5 I2 O
LUT6 I3 aPoolOut_OBUF[2240]_inst_i_317
0 0
I4 I0 O
0
exponent1_i_390__139 I5 I1
I0 LUT6 LUT2
36
I1
I2 O
I4 I0
I5 I1 O
LUT6 I2
LUT4 I0
I0 I2 O
I1 I3
I2 O I4
I3 LUT5
I5 I0
LUT6 I1
I2 O
I3
6 6
I0 O I5
6 LUT6
I1
LUT2
1 1 3
I0 O I0
1
I1 I1 O
LUT2 7
I2
I3
0 0
I0 O
0
LUT2 I0
I1
31
I2 O
I3
I0 I5
I1 LUT6
I2 O
I3
I4
exponent1_i_374__139 exponent1_i_348__139 LUT5

0
I0 I0
38
I1 I1
2 0
I2 O I2 O exponent1_i_192__139
38
I3 I3 I0
2
I4 I4 I1
I5 I5 7 I2 O
CI
LUT6 LUT6 I3
CI_TOP CO[7:0]
2:0 I4
DI[7:0] O[7:0]
2:0 I5
S[7:0]
LUT6
CARRY8
33
I0
38
aPoolOut_OBUF[2240]_inst_i_383 aPoolOut_OBUF[2240]_inst_i_347 I1
1
I0 I0 I2 O
38
I1 O I1 I3
1
I2 I2 O I4
LUT3 I3 I5
I4 LUT6
LUT5 exponent1_i_256__139
I0 I1
I1 I2 O
I2 O I3
I3 I4
I4 I5
LUT5 LUT6
I0
I1
CI
I2 O
CI_TOP CO[7:0]
I3
DI[7:0] O[7:0]
I4
S[7:0]
I5
CARRY8
LUT6
3
I0
38
I1 O
3
I2
LUT3
4 exponent1_i_322__139
I0
38
I1 O
4
I2
LUT3
exponent1_i_391__139 exponent1_i_352__139
I0 I0
I1 O I1
I2 I2 O
LUT3 I3
I4
I5
LUT6
3
I0 I1
38
I1 I2 O
3
I2 O I3
I3 I4
I4 I5
I5 LUT6
LUT6
I0
I1
I2 O
I3
I4
I5
LUT6
exponent1_i_305__139 aPoolIn_IBUF[4518]_inst
0
I0
38 I O
I1 O
0 IBUF
I2
LUT3 aPoolIn_IBUF[4534]_inst
I O
I0
I1 IBUF
I2 O aPoolIn_IBUF[4535]_inst
I3
I O
I4
I5 IBUF
LUT6 aPoolIn_IBUF[4539]_inst
I O
IBUF
I0
I1 O
I2
LUT3
aPoolIn_IBUF[4540]_inst
I O
exponent1_i_320__139 IBUF
0
I0
0
I1 aPoolIn_IBUF[9410]_inst
1
I2 O
38 I O
I3
1 IBUF
I4
LUT5 exponent1_i_379__139
5
I0 I1
38
I1 O I2 O
5
I2 I3
LUT3 I4
LUT6
I O 28
IBUF
I O 23
IBUF
I O 22
IBUF
I O 21
IBUF
I O 20
IBUF
I O 19
IBUF
I O 18
IBUF
I O 17
IBUF
I O 16
IBUF
I O 15
IBUF
I O 14
IBUF
I O 13
IBUF
I O 12
IBUF
I O 11
IBUF
I O 10
IBUF
I O 9
IBUF
I O 8
IBUF
I O 7
IBUF
I O 6
IBUF
I O 5
IBUF
I O 4
IBUF
I O 3
IBUF
I O 2
IBUF
I O 1
IBUF
I O 0
IBUF
Part 5
Integration
Omar Tarek
1) Block Diagram
(note: due to the large size and several constraints the full design was not
implemented)
Fully
Convolution
16 to 32-bit converter Connected
Part
Part
The fully implemented part is Fully Connected layer, it includes

FC1 + Tanh + FC2 + SoftMax. The code for the conv part is
written but not tested
2) Verilog Codes
IntegrationFC.v
IntegrationConv.v
3) Verilog Tesbench
IntegrationFC_tb.v
4) Screenshots:
i. Fully Connected Part
We can see clearly the sequence of activation at the fully

connected part with each layer outputting to the next. In the
next page we talk about result verification.
Using files supplied in phase 1 (C++) code, I generated a random
set of 120 numbers that were input to the module. I ran the
module and compared the output with every stage output from
the C++ files. They are attached here:
I also laid out the data in excel to make it easier to visualize.
Excel Proof of function:
(compared to output from simulations)
We notice that the numbers are a bit off but all within our
range of accuracy. Off by a small fraction due to the short range
and convergence condition of the tanh.
The data was copied from the Waveform and the results of the
C++ code.
b. Post Synthesis Timing for the basic convUnit:
(as agreed upon post timing for larger layers of hardware are not achievable with our
hardware capabilities. Our attempts reached up to 20 hours, all while stalling the progress
bar. It’s not achievable on consumer hardware)

a. Integration FC part:
FC1 -> 122
TanH-> 84*6+2
FC2-> 86
SoftMax-> 11
725 clock cycles

Integration FC part
The synthesis Schematic is attached on the next page
The LUT’s produced represent the huge amount of data
processed in this file. Synthesis caused a lot of issues
but the code is synthesizable.
8) Answers to extra questions:

No extra questions were asked in the description
address1[0]_i_2
3 address1_reg[0]
I0
6
I1 address1[0]_i_1 C
7
I2 O I0 CE 0
5 2 Q
I3 I1 O D
0 0
I4 I2 PRE
4 1
I5 I3
FDPE
LUT6 LUT4
address1_reg[1]
address1[1]_i_2 address1[1]_i_1
2
I0 I0 C
3 6
I1 O I1 CE 1
7 4 Q
I2 I2 O D
1 5
I3 I3 PRE
LUT4 1
I4
FDPE
0
I5
LUT6 address1_reg[3]
address1[3]_i_1 C
2
I0 CE 3
0 Q
I1 O D
1
I2 PRE
3
I3
FDPE
LUT4
address1_reg[4]
address1[4]_i_1
3
I0 C
1
I1 CE 4
0 Q
I2 O D
2
I3 PRE
4
I4
FDPE
LUT5
address1_reg[5]
address1[5]_i_1
4
I0 C
2
I1 CE 5
0 Q
I2 O D
1
I3 PRE
address1[7]_i_2 3
4 I4
I0 FDPE
5
2 I5
I1
LUT6 address1_reg[6]
0
I2 O
1
I3 C
3
I4 address1[6]_i_1 CE 6
5 Q
I5 I0 O D
LUT6 6
I1 PRE
LUT2
FDPE
address1_reg[7]
address1[7]_i_1 C
6
I0 CE 7
Q
I1 O D
7
I2 PRE
LUT3
FDPE
address2_reg[0]_rep__4
address2[0]_rep__4_i_1
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
1
I0 C
I1 CE
7 Q
I2 O D
7
I3 PRE
6
I4
FDPE
7
I5
LUT6
1
I0 C
I1 CE
7 Q
I2 O D
7
I3 PRE
6
I4
FDPE
7
I5
LUT6
1
I0 C
I1 CE
7 Q
I2 O D
7
I3 PRE
6
I4
FDPE
7
I5
LUT6
1
I0 C
I1 CE
7 Q
I2 O D
7
I3 PRE
6
I4
FDPE
7
I5
LUT6
1
I0 C
I1 CE
7 Q
I2 O D
7
I3 PRE
6
I4
FDPE
7
I5
LUT6 address2_reg[1]_rep__11
address2[1]_rep__11_i_1 C
1
I0 CE
Q
I1 D
7
I2 O PRE
7
I3
FDPE
6
I4
7
I5 address2_reg[1]_rep__12
LUT6
C
address2[1]_rep__12_i_1 CE
1 Q
I0 D
I1 PRE
7
I2 O
FDPE
7
I3
6
I4 address2_reg[1]_rep__13
7
I5
C
LUT6
CE
Q
address2[1]_rep__13_i_1 D
1
I0 PRE
I1
FDPE
7
I2 O
7
I3 FC2reset_reg
6
I4
FC2reset_i_2 7 C
7 I5
I0 CE
LUT6 Q
7
I1 D
6
I2 O FC2reset_i_1 PRE
7
I3 I0 O
FDPE
7
I4 I1
7 LUT2
I5
LUT6
SMaxEnable_reg
SMaxEnable_i_1
I0 C
7
I1 CE
7 Q
SMaxEnable_i_2 I2 O CLR
6 7
I0 O I3 D
7
I1 I4
FDCE
LUT2 I5
LUT6
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
7
I0 C
7
I1 CE
6 Q
I2 O D
7
I3 PRE
I4
FDPE
LUT5
address2_reg[4]
address2[4]_i_1 C
4
I0 CE 4
Q
I1 D
I2 O PRE
I3
FDPE
3
address2[6]_i_58 I4
6 3
I0 O I5 address2_reg[2]_rep__3
LUT1 LUT6
C
address2[6]_i_59 address2[5]_i_2 Q
0 0 3 I0 D
I0 O I0
I1 O PRE
LUT1 I1
I2
I2 O FDPE
address2[6]_i_78 I3
5 7 I3
I0 O LUT4 address2_reg[2]_rep__4
4
6 I4
I1
LUT5 address2[2]_rep__4_i_1 C
LUT2
I0 CE
address2[7]_i_2 Q
address2[6]_i_79 4 I1 O D
3 6 I0
I0 O I2 PRE
4 I1
I1 I3
I2 O FDPE
LUT2 LUT4
I3
3 address2_reg[2]
address2[6]_i_80 I4
1 5 5 address2[2]_i_1
I0 O I5 C
2 I0
I1 LUT6 CE 2
I1 O Q
LUT2 D
I2
PRE
address2[6]_i_81 I3
7 4 LUT4 FDPE
I0 O
0
I1
LUT2
address2[6]_i_82
5 3 address2[2]_rep__5_i_1
I0 O C
6 I0
I1 CE
I1 O Q
LUT2 D
I2
PRE
address2[6]_i_83 I3
3 2 LUT4 FDPE
I0 O
4
I1
LUT2
address2[2]_rep_i_1
address2[6]_i_84
1 1 I0 address2_reg[2]_rep
I0 O
2 I1 O
I1 C
I2
LUT2 CE
I3 Q
D
address2[6]_i_85 LUT4
0 PRE
I0 O
0 address2_reg[6]_i_6 address2[5]_i_1 FDPE
I1 5
CI I0
LUT2
CI_TOP CO[7:0] I1 address2_reg[5]
3,0 n/c 7
address2[6]_i_86 DI[7:0] O[7:0] I2 O
0 3 7 C
I0 O S[7:0] I3
6 CE 5
LUT1 CARRY8 I4 Q
7 D
I5
address2[6]_i_87 address2_reg[6]_i_16 PRE
LUT6
5 2
I0 O CI
FDPE
6
I1 CI_TOP CO[7:0]
LUT2 n/c
DI[7:0] O[7:0] address2[6]_i_1 address2_reg[6]
6
S[7:0] I0
address2[6]_i_88 C
CARRY8 I1
3 1
I0 O 7 CE 6
4 I2 O Q
I1 address2_reg[6]_i_33 7 D
I3
LUT2 CI PRE
6
I4
CI_TOP CO[7:0] 7
address2[6]_i_89 I5 FDPE
3:0 n/c
1 0 DI[7:0] O[7:0]
I0 O LUT6
2 S[7:0] address2_reg[7]
I1
CARRY8 address2[7]_i_1
LUT2 C
7
I0
CE 7
address2[6]_i_90 I1 O Q
7 7 6 D
I0 O address2_reg[6]_i_41 I2
0 PRE
I1 CI I3
LUT2 CI_TOP CO[7:0] LUT4 FDPE
n/c
DI[7:0] O[7:0]
address2[6]_i_91
5 6 S[7:0] address2[6]_i_63
I0 O 7 4
CARRY8 I0 O
6
I1 0
I1
LUT2
LUT2
address2[6]_i_92
3 5
I0 O address2[6]_i_8 address2[0]_rep_i_1 address2[6]_i_76
4 5 7 7 1 1
I1 I0 O I0 I0 O
LUT2 6 7 2
I1 I1 I1
LUT2 6 LUT2
I2 O
address2[6]_i_93 7
1 4 I3
I0 O
2 address2[6]_i_9 I4 address2_reg[0]_rep
I1 3 6
I0 O LUT5
LUT2 C
4
I1
CE
address2[6]_i_94 LUT2 address2[1]_i_1 Q
0 3 1 D
I0 O I0
7 address2[6]_i_10 PRE
I1 1 5 I1
I0 O 7
LUT2 I2 O FDPE
2
I1 7
I3
6
5 2 I4
I0 O 7
6 address2[6]_i_11 I5 address2_reg[1]
I1 7 4
I0 O LUT6
LUT2 C
0
I1
address2[0]_rep__21_i_1 CE 1
LUT2 Q
7
address2[6]_i_96 I0 D
3 1 7
I0 O address2[6]_i_12 I1 PRE
4 5 3 6
I1 I0 O I2 O
FDPE
LUT2 6 7
I1 I3
LUT2 I4
1 0
I0 O address2[6]_i_13 address2_reg[0]_rep__21
2 3 2
I1 I0 O
4 C
LUT2 I1
LUT2 Q
7
address2[6]_i_98 I0 D
5 7 7
I0 O address2[6]_i_14 I1 PRE
6 1 1 6
I1 I0 O I2 O
FDPE
LUT2 2 7
I1 I3
LUT2 I4 address2_reg[0]_rep__22
3 6
I0 O address2[6]_i_15 C
4 7 0
I1 I0 O address2[0]_rep__23_i_1 CE
0 7 Q
LUT2 I1 I0 D
LUT2 7
I1 PRE
address2[6]_i_100 6
1 5 I2 O
I0 O address2[6]_i_17 FDPE
7
2 5 7 I3
I1 I0 O
6 I4 address2_reg[0]_rep__23
LUT2 I1
LUT5
LUT2 C
address2[6]_i_101
7 4 address2[0]_rep__28_i_1 CE
I0 O address2[6]_i_18 7 Q
0 3 6 I0 D
I1 I0 O 7
4 I1 PRE
LUT2 I1 6
I2 O
LUT2 FDPE
7
address2[6]_i_102 I3
5 3
I0 O address2[6]_i_19 I4 address2_reg[0]_rep__28
6 1 5 LUT5
I1 I0 O
2 C
LUT2 I1
CE
LUT2 Q
address2[6]_i_103 D
3 2 address2_reg[6]_i_2
I0 O address2[6]_i_20 7 PRE
4 7 4 CI
I1 I0 O
CI_TOP CO[7:0] FDPE
LUT2 0
I1 n/c
... DI[7:0] O[7:0]
LUT2
address2[6]_i_104 S[7:0]
1 1 CARRY8
I0 O address2[6]_i_21
2 5 3
I1 I0 O address2[7]_i_3
LUT2 6 7
I1 I0
LUT2 6
I1 O
address2[6]_i_105 7
0 0 I2
I0 O address2[6]_i_22 7
3 2 I3
I1 I0 O
address2_reg[6]_i_3 LUT4
LUT2 4
I1 7
CI
LUT2
address2[6]_i_106 CI_TOP CO[7:0]
5 7 n/c
I0 O address2[6]_i_23 DI[7:0] O[7:0]
6 1 1
I1 I0 O S[7:0]
LUT2 2 CARRY8
I1
LUT2
address2[6]_i_107 address2_reg[6]_i_4
3 6 7
I0 O address2[6]_i_24 CI
4 7 0
I1 I0 O CI_TOP CO[7:0]
LUT2 0 6 n/c
I1 DI[7:0] O[7:0]
LUT2 S[7:0]
6:0
address2[6]_i_108 CARRY8
1 5
2 5 7
I1 I0 O
SMaxEnable_i_77 LUT2 6 address2_reg[6]_i_5
5 7 I1 7
I0 O CI
LUT2
6
I1 address2[6]_i_109 CI_TOP CO[7:0]
LUT2 7 4 n/c
I0 O address2[6]_i_26 DI[7:0] O[7:0]
0 3 6
I1 I0 O S[7:0]
SMaxEnable_i_78 LUT2 4 CARRY8
3 6 I1
I0 O
LUT2
4
I1 address2[6]_i_110
LUT2 6 3
5 1 5 address2[6]_i_50
I1 I0 O 5 7
SMaxEnable_i_79 2 I0 O
LUT2 I1
1 5 6
I0 O I1
LUT2
2 LUT2
LUT2 3 2
4 7 4 address2[6]_i_51
I1 I0 O 3 6
SMaxEnable_i_80 0 I0 O
LUT2 I1
7 4 4
I0 O I1
LUT2
0 LUT2
LUT2 1 1
2 5 3
I1 I0 O
LUT2 6
SMaxEnable_i_81 I1
1 1 LUT2
I0 O
2 address2[6]_i_113
I1 0
LUT2
0 3 2
I1 I0 O
LUT2 4
SMaxEnable_i_82 I1
0 0 LUT2
I0 O
SMaxEnable_reg_i_33
I1
CI address2[6]_i_31
LUT2
1 1
CI_TOP CO[7:0] I0 O
... ... n/c 2
SMaxEnable_i_83 DI[7:0] O[7:0] I1
5 7 LUT2
I0 O S[7:0]
6 CARRY8
I1
LUT2 address2[6]_i_32
7 0
I0 O
0
SMaxEnable_i_84 I1
3 6 LUT2
I0 O
4
I1
LUT2 SMaxEnable_i_34 address2[6]_i_34
5 7 5 6
I0 O I0 O
6 6
SMaxEnable_i_85 I1 I1
1 5 LUT2 LUT2
I0 O
2
I1
LUT2 SMaxEnable_i_35 address2[6]_i_35
3 6 3 5
I0 O I0 O
4 4
I1 I1
LUT2 LUT2
SMaxEnable_i_86
0 4
I0 O SMaxEnable_i_36 address2[6]_i_36
7 1 5 1 4
I1 I0 O I0 O
LUT2 2 2
I1 I1
LUT2 LUT2
SMaxEnable_i_87
5 3
6 SMaxEnable_i_37 7 3
I1 7 4 I0 O
I0 O 0
LUT2 I1
0
I1
LUT2
SMaxEnable_i_88 LUT2
3 2
4 SMaxEnable_i_38 5 2
I1 5 3 I0 O
I0 O 6
LUT2 I1
6
I1
LUT2
2 1
I0 O address2[6]_i_39 address2[6]_i_53
1 SMaxEnable_i_39 3 1 7 4
I1 3 2 I0 O I0 O
I0 O 4 0
LUT2 I1 I1
4
I1
LUT2 LUT2
0
I0 O address2[6]_i_40 address2[6]_i_57
0 SMaxEnable_i_40 1 0 7 0
I1 1 1 I0 O I0 O
I0 O 2 0
LUT2 I1 I1
2
I1
LUT2 LUT2
LUT2
SMaxEnable_i_41 SMaxEnable_reg_i_5
7 0 7
I0 O CI
0
I1 CI_TOP CO[7:0]
LUT2 n/c
DI[7:0] O[7:0]
S[7:0]
CARRY8
address2[6]_i_42
5 7
I0 O
6
I1
LUT2
address2[6]_i_43
3 6
I0 O
4
I1
LUT2
counter_reg[17] address2[6]_i_44
1 5
I0 O
C 2
I1
CE
Q LUT2
CLR
1
D
address2[6]_i_45
FDCE 7 4
I0 O
0
I1
counter_reg[25] counter_reg[18] LUT2
C C
CE CE counter_reg[9] address2[6]_i_46
Q Q 5 3
CLR CLR I0 O
1 2 C 6 SMaxEnable_i_46
D D I1 5 3
CE I0 O
Q LUT2
FDCE FDCE 6
CLR I1
1 LUT2
D address2[6]_i_47
counter_reg[26] counter_reg[19] 3 2
I0 O
FDCE SMaxEnable_i_47
4
C C I1 3 2
I0 O
CE CE counter_reg[10] LUT2
4
Q Q I1
CLR CLR
C address2[6]_i_48 LUT2
2 3
D D 1 1
CE I0 O
Q 2 SMaxEnable_i_48
FDCE FDCE CLR I1 1 1
2 I0 O
D LUT2
2
counter_reg[27] counter_reg[20] I1
FDCE address2[6]_i_49 LUT2
C C 7 0
counter[0]_i_2 I0 O
CE CE counter_reg[11] 0 SMaxEnable_i_49
Q Q I0 O I1 7 0
CLR CLR I0 O
C LUT1 LUT2
3 4 0
D D I1
CE
Q LUT2
FDCE FDCE CLR
3
D SMaxEnable_i_71
counter_reg[28] counter_reg[21] 1 5
counter_reg[1] counter_reg[0]_i_1 I0 O
FDCE
2
C C CI I1
C
CE CE counter_reg[12] CI_TOP CO[7:0] LUT2
Q Q CE V=B"00000001"
CLR CLR Q DI[7:0] O[7:0]
4 5 C CLR SMaxEnable_i_72
D D 1 S[7:0] 0 4
CE D I0 O
Q CARRY8
FDCE FDCE 7
CLR I1
FDCE
4 LUT2
D
counter_reg[29] counter_reg[22]
FDCE counter_reg[2] counter_reg[0]
SMaxEnable_i_73
C C 5 3
C C I0 O
CE CE counter_reg[13] 6
Q Q CE CE I1
CLR CLR Q Q
C CLR CLR LUT2
5 6
D D 2 0
CE D D
Q SMaxEnable_i_74
FDCE FDCE CLR
FDCE FDCE 3 2
5 I0 O
D 4
counter_reg[30] counter_reg[23] I1
FDCE LUT2
C C
CE CE counter_reg[14] SMaxEnable_i_75
Q Q counter_reg[3] SMaxEnable_reg_i_67 1 1
CLR CLR I0 O
6 7 C CI 2
D D C I1
CE CI_TOP CO[7:0]
Q CE LUT2
FDCE FDCE CLR Q DI[7:0] O[7:0]
6 CLR
D 3 S[7:0]
D SMaxEnable_i_76
CARRY8
FDCE 0
I0 O
FDCE
0
address2_reg[6]_i_7 I1
counter_reg[31] counter_reg[24] counter_reg[15] 7 LUT2
CI
C C C CI_TOP CO[7:0]
counter_reg[4]
CE CE CE DI[7:0] O[7:0]
Q Q Q
CLR CLR CLR C S[7:0]
7 0 7 CARRY8
D D D CE
Q
CLR
FDCE FDCE FDCE
4
D
FDCE address2_reg[6]_i_68
7
CI
counter_reg[24]_i_1 counter_reg[16]_i_1 counter_reg[8]_i_1
7 7 7 CI_TOP CO[7:0]
CI CI counter_reg[16] CI
DI[7:0] O[7:0]
CI_TOP CO[7:0] CI_TOP CO[7:0] CI_TOP CO[7:0] counter_reg[5]
C S[7:0]
DI[7:0] O[7:0] DI[7:0] O[7:0] DI[7:0] O[7:0]
CE C CARRY8
S[7:0] S[7:0] Q S[7:0]
CLR CE
CARRY8 CARRY8 CARRY8 Q address2_reg[6]_i_69
0
D CLR 7
5 CI
D
FDCE CI_TOP CO[7:0]
FDCE DI[7:0] O[7:0]
S[7:0]
CARRY8
counter_reg[6]
CE
Q
CLR
6
D
FDCE
counter_reg[7]
C
CE
Q
CLR
7
D
reset_IBUF_inst
FDCE
I O
reset
IBUF
counter_reg[8]
CE
Q
CLR
0
D
FDCE

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CNN

This section is a summary and outline of the project

All modules are verfied to be functional and synthesizable. The testing

The last layer in the leNet-5 architecture is a SoftMax activation layer.

Special testing procedure for Convolution and AvgPool:

The code files are also attached at the end of this

Synthesis was attempted for all files. And the maximum

In the next part each document was written entirely by

Post Synthesis simulation was agreed upon to simply

All original screenshots, reports, and test files are

The next section covers individual reports, that

Part 1- Daniel Eskandar

Single Filter Layer

Multi Filter Layer

Single Filter Layer

Single Filter Layer

ii. Single Filter Layer

TCL script and waveform of the final output

All results were verified using the simulated Convolution Layer

5) Clock Cycle Count:

outputConv_reg[21531]_i_4 LUT6 G OBUF

outputConv_reg[26139]_i_3 LUT5 LDCE

outputConv_reg[19589]_i_2 outputConv_reg[19589] OBUF

outputConv_reg[58395]_i_2 outputConv_reg[58395] OBUF

outputConv_reg[3709]_i_2 outputConv_reg[3709] outputCounter_reg[6]

outputConv_reg[9952]_i_2 LDCE outputConv_OBUF[10240]_inst

outputConv_reg[3709]_i_2 outputConv_reg[3709] outputCounter_reg[6]

outputConv_reg[9952]_i_2 LDCE outputConv_OBUF[10240]_inst

Logic-2 tanh Function

In the Hyperbolic Tangent:

I divide the operations into 3 Multipliers and 1 Adder.

The input here is 0.600000023842 in floating numbers is 00111111000110011001100110011010

The output here:

1. Actual is 0.53704 in floating is 00111111000010010111101101110100

Which is a very slight difference regarding Taylor approx.

Here the input is 3 in floating 01000000010000000000000000000000:

1- The Actual output is 0.995

2- The simulation output is 1 because it lies in the convergence region

Now here comes the tanh layer:

Regarding the layer, the input is in kernels in the size of 25 inputs:

Post Synthesis-Timing Simulation

Here my input is:

And here are the Outputs:

And the Actual Outputs are:

File Description Table:

HyperBolicTangent.v It is considered the processing unit of the layer

Design Description: 10 exponent units, 1 floating adder , 1 multiplier, 1 division unit.

6- Synthesis Report: 17532/53200 LUTs 32.95% utilization.

6- Synthesis Report: 25141/53200 47.26% utlization

Completion of part 4: Verification that the design is working

floatAdd floatAdd floatAdd floatMult

Average Pool layer

Average Pool Multi Layer

ii. Single Average Layer

5) Clock Cycle Count:

Avg Pool Layer

exponent1_42 numA[7]_0 exponent1_10

IBUF exponent1_45 numA[13][7:0] exponent1_13

numA[8]_2 numB[4] exponent1_22

IBUF numA[8]_5 numB[12][1:0] exponent1_25

6 I O 6 numA[8]_8 AvgOut[8] numC[14] exponent1_28

numA[8]_14 AvgOut[13]_3 exponent1_34

8 I O 8 numA[8]_16 AvgOut[14]_0 exponent1_36