3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)
PWM Waveform Generation Using Rotary
Encoder on Spartan-3E Starter Kit
Shilpa Thakral1,a, Amit Mahesh Joshi1,a and Unnati Mehta2,a
a
Department of Electronics and Communication
1
Malaviya National Institute of Technology, Jaipur, India
2
ABES Engineering College, Ghaziabad, India
Abstract—A PWM waveform generator with variable duty
cycle has been designed and implemented in this paper. The
design has been simulated for different frequencies. The
waveform is generated on Spartan 3E FPGA starter kit
which has on board rotary encoder. The on board clock
signal and rotary encoder generates the required PWM
signal. The duty cycle of PWM is varied by rotating the
encoder in clockwise and anticlockwise directions. Various
frequencies of PWM signal is generated by pressing it up
and down. The design has been proposed where duty cycle
can be varied from 0 to 100%. The frequency of the on
board clock signal i.e., 50 MHz and this has been varied to
generate different frequencies. The output can be observed
on DSO and CRO. The PWM is used in controlling
inverters, electrical motors and many communication and
control applications. The usage of FPGA provides the
reconfigurable architecture and also provides flexibility as
well as economically viable.
Keywords: Duty Cycle; FPGA; PWM; Rotary encoder;
Spartan 3E; Verilog; Xilinx.
I. INTRODUCTION
Pulse width modulated signal is widely used in a number
of applications such as generating regulated DC voltage
from unregulated supplies[1], controlling inverters, ac
and dc motors[2], ac machine drives[3], analog to digital
conversion, communication and control applications and
many more. PWM inverters are used to control both
frequency and magnitude of the voltage and current
applied to the motor in AC motor drives [4]. PWM
generators are used to trigger thyristors, Insulated-Gate
Bipolar Transistors (IGBTS), Metal Oxide
Semiconductor Field Effect Transistors (MOSFET), etc.
which are used as switches for regulating voltages [5].
Nowadays they are also widely used in multilevel
multiphase converters [6]. PWM waveform is basically a
waveform whose pulse width can be varied according to
the amplitude of the modulating signal by keeping the
time period of the waveform constant. In this paper the
on board clock signal is used as the carrier signal whose
duty cycle and frequency has been varied using the rotary
encoder available on Spartan 3E FPGA starter kit. FPGA
has flexible architecture and the duty cycle of PWM can
be varied accordingly. The reconfigurable structure of
FPGA provides an advantage of programmable design
for specified application [7]. The duty cycle of a signal is
defined as the ratio of on time to the total time period of
the signal. If a pulse is ON for ‘т’ duration and OFF for
‘t-т’ duration where ‘t’ is the total time period of the
signal, then duty cycle is given by ‘т/t’ in percentage as
shown in Fig. 1. The frequency of the signal is given by
the reciprocal of time period of the signal.
978-1-5090-6218-8/17/$31.00 ©2017 IEEE
1
Fig
. 1. Duty cycle and frequency of PWM signal
The main advantage of Pulse Width Modulation is
that it has very low power loss in switching devices and
higher frequency. Only digital circuits can produce PWM
signals. FPGA based PWM provides flexibility to the
design. They are less costly, have small design period,
can be easily reprogrammed, all these features make
them economically viable for small designs. In many
control system applications FPGAs are replacing
microcontrollers [8].
The design has been simulated for different
frequencies that are generated by processing the on board
clock’s frequency. The clockwise and anticlockwise
rotation of the knob has been programmed to vary the
duty cycle of the on board clock. Rotating the knob
clockwise increases the duty cycle and rotating it
anticlockwise decreases the duty cycle and hence
variation from 0 to 100% can be easily obtained. The
push button movement of the rotary encoder has been
programmed to vary the frequency of the clock with the
help of rotating motion. The FPGA kit has been
programmed using Verilog code. The technique
suggested in this paper is one of the simplest method to
generate a variable duty cycle and frequency PWM
waveform.
Various attempts have been made to generate a
variable duty cycle and frequency PWM waveform. Most
of them have used less flexible, complex and limited
functionalities approach to generate the PWM signal.
Kirnapure and Wadhankar have designed a high speed
PWM waveform using registers, counters, latches and
comparator and obtained upto 248.69 MHz with a
resolution of 0.39% [9]. Koutroulis et al. have
successfully prototyped a PWM generator with
maximum frequency 3.985 MHz and with a duty cycle
resolution of 1.56% [10]. Suneeta et. al. have developed
a variable duty cycle PWM generator on FPGA using
VHDL. They have implemented the design using N-bit
free running counter, comparators and latches [11].
The contribution of this paper is to design a PWM
waveform generator with variable duty cycle at different
frequencies. The proposed method is a very flexible,
simple and economical approach as a very few resources
have been used along with simple programmable logic
 3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

without using any complex mathematical operations. corresponding to ROT_A and eventually it will have a
Spartan 3E FPGA kit has been used to implement the contact with inner ring corresponding to ROT_B.
design and for simulation and synthesis purposes using
Xilinx ISE 14.7 has been used.
The paper is organized as follows. Section II
describes the working and operation of rotary encoder.
Section III describes the implementation of the proposed
generator. Simulations and results are described in
Section IV and conclusion is given in Section V.

II. ROTARY ENCODER Fig. 3. ROT_A and ROT_B signals on rotation

Rotary encoder is an electromechanical knob type

arrangement which has two types of motions, one is
circular movement which can be either clockwise or
anticlockwise and the other one is push button
movement. Rotary encoder basically consists of a cam-
shaft arrangement connected with two switches as shown
in Fig. 2. With each ‘click’ of the shaft the cam moves by
one step of 18˚ and a led blinks to show the movement
[12]. Initially both the switches are closed, based on the
direction of rotation one switch is opened before the
other and as the process continues one is closed before
the other, this feature is used to increase or decrease the
duty cycle. There is one more switch(push button
arrangement) connected with the cam-shaft arrangement Fig. 4. Ring arrangement of Rotary encoder
which is normally open and when the cam is pushed
towards the base, the switch is closed and get connected After contact with outer ring, it will be released first
to 3.3 V. These two movements have been used to followed by the loss of contact with inner ring. Every
program the rotary encoder to work according to our step movement of Rotary knob involves such kind of
requirements. When the knob is rotated clockwise the actions in it and after that it will achieve defined position
duty cycle of the PWM waveform increases and similarly that can be called as rest position. Framing it logically, if
anticlockwise movement of the cam results in the we examine ROT_A and ROT_B signals, for clockwise
decrease of duty cycle. When we combine the push movement ROT_A signal will go high first follows by
button movement with the circular movement we can ROT_B. After that, ROT_A will go low and at the end
modify the frequency of the waveform. While pressing ROT_B will go low as shown in the Fig. 3 and vice versa
the switch and rotating the knob clockwise, increases the for the anticlockwise rotation. We just need to analyze
frequency and rotating it anticlockwise decreases the the signal ROT_A and ROT_B to determine the direction
frequency. As each step is of 18˚, we can generate 40 of rotation.
different duty cycle and frequencies by 360˚ rotation.
III. IMPLEMENTATION OF THE DESIGN

The block diagram of the proposed design is shown as

Fig. 5. As shown in the Fig. 5, the movement of rotary
encoder generates three signals, ROT_A, ROT_B and
ROT_CENTER which are given as input along with the
50 MHz on board clock. The ‘clk’ signal to FPGA logic
is used to generate PWM waveform ‘clk_out’ signal with
variable duty cycle at different frequencies.

Fig. 2. Rotary encoder

Circular movement of knob can be detected by using

ROT_A and ROT_B signals as shown in Fig. 3. Inside
the rotary encoder, there are two concentric conductive
rings which represents ROT_A(outer ring) and
ROT_B(inner ring) and rotary shaft is connected with Fig. 5. Block Diagram of PWM waveform generator
logic high as shown in the Fig. 4. If we rotate the knob
clockwise then shaft will have a contact with outer ring ROT_A and ROT_B are used to determine the direction
of rotation and ROT_CENTER is used to detect the push

2
 3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)

button movement. While explaining the working of

rotary encoder we have considered that the switch is
chatter-free that suggests that it does not bounce back
[13]. Since the switch is a mechanical arrangement and
has some spring action due to which it bounces back and
forth before settling down to its rest position. This
bounce may result in false detection of rotation as the
signal will momentarily go high and then low before
settling down to its actual high value. In order to combat
this issue, we have detected only the first change in the
signal and ignoring all subsequent activity on the same
signal until the other switch also changes its own state.
Flip flops are used to save the state of the signal. We Fig. 6. ROT_A1 and ROT_B1 signals
have used ROT_A1 and ROT_B1 signals to keep track of
the event at which switch goes on for the first time. The In order to get the simulation results at different
pseudo code for the Logic of this chatter-free detection is frequencies, we have used the same concept that we have
given below: used for the variation of duty cycle but with a little
modification. The frequency of the waveform will
change only when ROT_CENTER signal is high and the
knob is rotated clockwise or anticlockwise. Pressing the
knob towards the base results in the connection of the
push button switch with 3.3 V supply which turns it on.

IV. SIMULATION AND RESULTS

We have simulated our design using XILINX ISE 14.7.

The behavior of ROT_A1 and ROT_B1 are defined as
follow. ROT_A1 will be set when both ROT_A and
ROT_B will be high and will be reset when both signals
go low [14]. In all other cases of change ROT_A1 will
remember the current state at input side. ROT_B1 is in
set state when ROT_A is at low and ROT_B is at high.
However, it is in reset state when ROT_A is at high and
ROT_B is at low. For all other combinations of inputs,
ROT_B1 will remember the previous state. As shown in
Fig. 6, by application of this filter we get two signals
ROT_A1 and ROT_B1. Every rising edge of the
ROT_A1 represents the step movement and at that time
ROT_B1 value represents the direction of rotation. So,
therefore we can use ROT_A1 to determine the rotating
event and ROT_B1 to indicate the direction of rotation.
Consider the case when ROT_A1 is high and ROT_B1 is
low, this condition implies the clockwise rotation of the
knob which means the duty cycle of the waveform will
increase. This can be achieved by comparing the delayed
version of signal ROT_A1 with its current value to
determine its rising edge and then at that same time
instant observing the signal ROT_B1in order to detect
the direction of rotation. In Fig. 6, the bold lines indicate
where each signal is being forced and the normal lines
indicate where the flip-flop memory is retaining the
current state.
The functionality is designed using Verilog language and
subsequently is implemented on FPGA. The results have
been verified using ISIM simulator. The design has been
synthesized on XILINX synthesizer XST. For hardware
implementation we have generated the UCF file and
loaded it into the SPARTAN 3E FPGA Starter kit and
interfaced the output pin with the connecting probe of
CRO or DSO.
The on board clock of SPARTAN kit has been used as
the basic waveform on which operations have been
applied to get the desired results. The simulation results
with variable duty cycles at different frequencies are
shown in Fig. 7, 8 and 9. As shown in Fig. 7, the
waveform is ON for 20µs and OFF for 80µs and total
time period of the signal is 100µs which results in 20%
duty cycle (20/100) and frequency of 10KHz
value(1/100µs). Similarly in Fig. 8 signal is ON for 30µs
and OFF for 70µs resulting in a duty cycle of value 30%
and same frequency as above. In Fig. 8, the time period
of signal is changed to 1ms resulting in frequency of
1KHz value and the signal is ON for 0.35ms and OFF for
0.65ms resulting in 35% duty cycle signal. Similarly, we
can generate a large number of waveforms with variable
duty cycles at different values of frequencies.
Fig. 7. 20% Duty cycle with 10 KHz frequency

3
 3rd IEEE International Conference on "Computational Intelligence and Communication Technology" (IEEE-CICT 2017)
Fig. 8. 30% Duty cycle with 10 KHz frequency
Fig. 9. 35% duty cycle with 1 KHz frequency
V. CONCLUSION
We have designed a PWM waveform generator in which
the duty cycle of the waveform has been varied from 0 to
100%. The changes can be observed at different
frequencies of waveform. The proposed design has been
implemented on SPARTAN 3E FPGA Starter kit and the
waveform of the same is observed on DSO. 40 different
duty cycles have been generated by rotating the knob of
the rotary encoder. A number of frequencies can be
generated by varying the time period of on board clock
signal. The generator proposed in this paper is very easy
to implement and require minimal hardware and software
resources. FPGAs are more flexible and reliable than
other traditional microcontrollers. PWM waveforms are
often used to drive dc motors, ac motors, power
inverters, converters, triggering transistors and many
more. Depending upon the requirement of applications a
number of different PWM signals can be generated using
this approach.
REFERENCES
[1] R. Miftakhutdinov, A. Nemchinov, V. Meleshin, S. Fraidlin,
“Modified Asymmetrical ZVS half-bridge DC–DC converter”,
Applied Power Electronics Conference and Exposition,
Vol. 1, 1999, pp. 567–574.
[14] M. W. Naouar, E. Monmasson, A. A. Naassani, I. S.
Belkhodja, N. Patin, “FPGA based current controllers for ac
machine drives—A review,” IEEE Trans. Ind. Electron., vol. 54,
no. 4, pp. 1907–1925, Aug. 2007.
[2] Shruti Shrivastava , Jageshwar Rawat , Amit Agrawal,
“Controlling DC Motor using Microcontroller (PIC16F72) with
PWM”, International Journal of Engineering Research., Vol .1,
Issue No.2, s. 45-28, 01 Dec. 2012.
[3] Youichi Ito and Scoichi Kawauchi, “Microprocessor –Based
Robust Digital control for UPS with three phase PWM Inverter,”
IEEE Transactions on Power Electronics, Vol.10, No.2, March
1995.
[4] R. K. Pongiannan, S. Paramasivam, N. Yadaiah, “Dynamically
Reconfigurable PWM Controller for Three-Phase Voltage-Source
Inverters”, IEEE Transactions on Power Electronics, Vol. 26,
No. 6, s. 1790-1799, June 2011.
[5] Rahim N.A., Islam Z., “Field Programmable Gate Array-Based
Pulse-Width Modulation for Single Phase Active Power Filter”,
American Journal of Applied Sciences, Vol.6 ,pp. 1742-1747 ,
Feb. 2009.
[6] Ó. López, J. Álvarez, J. D.Gandoy, F. D. Freijedo, “Multilevel
Multiphase Space Vector PWM Algorithm”, IEEE Transaction on
Industrial Electronics, vol. 55, no. 5, May 2008.
[7] Joshi, Amit M., Anand Darji, and Vivekanand Mishra. "Design
and implementation of real-time image watermarking." In Signal
Processing, Communications and Computing (ICSPCC), 2011
IEEE International Conference on, pp. 1-5. IEEE, 2011.
[8] Joshi, Amit M., and Anand Darji. "Efficient dual domain
watermarking scheme for secure images." In Advances in Recent
Technologies in Communication and Computing, 2009.
ARTCom'09. International Conference on, pp. 909-914. IEEE,
2009.
[9] Sneha Kirnapure, Vijay R. Wadhankar, “Design of Pulse Width
Modulation Controller on FPGA using HDL”, International
Journal of Innovative Research in Computer and Communication
Engineering(An ISO 3297: 2007 Certified Organization)Vol. 3,
Issue 7,pp 6785- 6790, July 2015.
[10] Eftichios Koutroulis, Apostolos Dollas, Kostas Kalaitzakis ,
“High-frequency pulse width modulation implementation using
FPGA & CPLD ICs”, Journal of Systems Architecture 52 (2006)
332–344,pp 332-344, 25 Oct. 2005.
[11] Suneeta, R Srinivasan, Ramsagar, “ Generation of Variable Duty
Cycle PWM using FPGA”, IOSR Journal of VLSI and Signal
Processing (IOSR-JVSP), Vol. 4, pp 01-03, Nov. 2014 .
[12] “Spartan-3E FPGA Starter Kit Board User Guide”
[Online].Available from:
https://www.xilinx.com/support/documentation/boards_and_kits/u
g230.pdf
[13] “Rotary Encoder Interface for Spartan-3E Starter Kit” by Ken
Chapman [Online].Available from:
https://www.xilinx.com/products/boards/.../files/s3esk_rotary_enc
oder_interface.pdf