Dac Architecture

IL2220
Lecture 12
Nyquist-Rate
Digital-to-Analog Converters
1
IL2220/Spring 2008 Ana Rusu
Outline
Introduction
Voltage-Scaling DACs
Current-Steering DACs (Current-Switch DACs)
Charge Redistribution DACs
Hybrid & Segmented DACs
Special Improvement Techniques
Summary
2
1
Introduction - Digital-to-Analog Conversion
D/A Conversion is accomplished through the scaling (division or

multiplication) of a reference voltage, current or charge. The DAC
linearity is limited by the precision of division or multiplication.
• DACs tend to be architecturally simpler.
• Usually DACs require a decoder to control the switches.
• Fewer architectures are available for DACs. The DACs can be
divided in two main types:
Nyquist-rate D/A conversion
Oversampling D/A conversion
3
Introduction - Digital-to-Analog Conversion

Vout = Vref (b1 2 −1 + b2 2 − 2 + ... + bN 2 − N ) = Vref Bin
Nyquist-Rate DACs can be classified by:

1. D/A Conversion Time
Serial – 1 bit at a time (1 clock pulse), than the conversion
time is N*T - Slow
Parallel – all bits at the same time , than the conversion time
is T; Increased area for high resolution and large ratios for
matching
2. Reference Scaling Type: Voltage, or Current, or Charge
Serial DACs can be: Serial Charge redistribution DAC,
Algorithmic DAC, Pipelined DAC
Parallel DACs can be: Resistor String, Current Steering,
Charge Redistribution
Parallel with trade-off in area and component ratios results
improved approaches:
Hybrid DAC
Segmented DAC
4
2
Introduction - Binary and Thermometer-code
Thermometer-code differs from a binary code in that a thermometer-code

has 2N-1 digital inputs to represent 2N different digital values. Typically, in a
thermometer-code the number of 1s represents the decimal value.
Thermometer-code versus Binary-code:
+ Low DNL errors
+ Guaranteed monotonicity
+ Reduced glitch area
- Increased complexity (a binary code needs only N digital inputs to
represent 2N different digital values).
5
1. Voltage Scaling DACs

Basic idea: the element values are given by voltage levels.
1.1. Resistor-String DACs

Concept
Voltage scaling converts the
reference voltage to a set of 2N
voltages that are decoded to a single
analog output by the input digital word.
The decoder connects one of the
reference voltages to the output.
Voltage scaling normally uses series
resistors connected between Vref and
ground to selectively obtain voltages
between these limits.
An opamp can be used to buffer the
resistor string to prevent loading.
The voltage scaling DACs are well
suited for MOS technology.
6
3
Resistor-String
The MOS DAC is based on selecting one
3-bit DAC with tree tap of the segmented resistor string by a
decoder switch network. The switch network
(implemented with NMOS transistors or
CMOS Implementation transmission gates) is connected in a tree
decoding structure.
Advantages
• Simple
• Inherently monotonic
• Fast
• Small chip area for implementation
under 8 bits
Disadvantages
• Accuracy and INL depend on resistor
matching (type of resistors)
• Large chip area for more than 8 bits
• NMOS switches (2^N Ron in serie)
• The delay through the switches network
is the major limitation on speed (Ron &
parasitic caps)
• Speed performance is limited by the
opamp as well. 7
Resistor-string DAC with logic decoding
For high-speed:
A single switch is connected between
each node of the resistor string and the
output. Which switch is closed depends
on the logic circuit (N-to- 2N decoder).
This approach:
+ Reduces the series resistance of the
switches at each switch node,
-Takes more area for the decoder
- Results in a large capacitive loading
on the single bus (2N transistor
junctions).
An area-performance tradeoff solution:
some bits can be determined directly
by the switch decoder and the rest
indirectly by the logic decoder (a X-Y
scheme)
8
4
Folded Resistor-String DAC – to reduce the total
decoding area and the capacitive loading.
A X-Y scheme: a given pair identifies one and only one voltage
of the divider.
2 N resistors are divided into 2 N / 2
lines and arranged into a
serpentine fashion between
Vref and GND. Each line
represents one of the 4MSBs
of the digital input. The MSBs
decoder selects a word line
while the LSBs decoder picks
up a bit of the line.
A set of transistors is
connected directly to the output
line and another set is
connected to the chosen bit
line. Then, the total number of
transistor junctions on the
output line is only 2√ 2N . The increase in speed is not the same. 9
Multiple R-string DAC

High-resolution DACs require large number of resistors and
switches. Solution: the DAC can be decomposed into a coarse
and fine part that requires only 2x2N/2 equal resistors.
A 2nd tapped resistor string is connected
between the ywo intermediate buffers
whose inputs are 2 adjacent nodes of the
1st resistor string. The MSBs determine
which 2 adjacent nodes of the 1st resistor
string are connected to the two buffers.
The 2nd resistor string linearly interpolates
between the 2 adjacent voltages from the
1st resistor string. The output is determined
by the lower LSBs with extra logic.
+ Reduced number of resistors - Suitable
for high-resolution and low-power
+ Guaranteed monotony (if the opamps
match, voltage-insensitive offset voltages)
+ Relaxed matching requirements for 2nd
resistor string (it decodes only LSBs)
- Need fast and low noise opams. 10
5
1.2. Binary scaled DACs
• Are not intrinsically monotonic; require tight device

matching to achieve monotonicity (DNL<1LSB)
• Exhibit large glitch impulses, which can affect the
dynamic response
Implementations:
- Binary-weighted resistor D/A Converters
- R-2R ladder D/A Converters
Performance Improvement:
- use Thermometer-code and/or Segmentation
11
1.2. Binary scaled DACs

A. Binary-weighted resistor D/A Converters
Utilizes a number of reference elements that are binary weighted.
Popular for bipolar technology where high-quality resistors are available.

+ Low numbers of resistors, switches
- Large resistor and current ratios (in order of 2N), switches must be scaled.
- Very sensitive to mismatch errors
- Monotonicity is not guaranteed
- Glitches problems at high-speed operation
12
6
B. R-2R ladder D/A Converters
The binary weighted currents are realized with a small number of
components and resistors ratio of only 2 (independent of N)
R-2R versus Binary-weighted

+ Implemented with a single-size resistors (resistors of size 2R are made out of
2 resistors of size R) to improve the matching properties
+ Smaller size
+ Better accuracy
+ Low resistor ratio
- Current ratios still large -switches must be scaled.
- Monotonicity is not guaranteed 13
- Glitches effects
C. Improved R-2R ladder DAC
Equal currents flow through all switches.

+ Does not require devices scaling, than it reduces chip area
- Require tighter matching
- Possible large glitch area (possible skew between switching instants generate
glitches)
- Slow, because the internal nodes of R-2R ladder now exhibit voltage swings.
14
7
1.3. Thermometer-code D/A Converters
Method to build a thermometer-code: build (2N-1) equal-sized resistors and

switches attached to the virtual ground of an opamp.
+ Minimizes glitches compared to binary-array DACs
+ Low mismatch effect
+ Guaranteed monotonicity
+ Does not increase the analog circuitry compared to binary-weighted DACs
- Binary-to-Thermometer code conversion requires large area and power
dissipation for high resolution.
15
2. Current-Steering DAC (Current-Switch DAC)

Basic idea: to switch currents (SI) to either the output or to ground.
The high-speed DACs are based on current-switch, because they can
drive resistive loads directly.
2. 1. Binary-weighed current-scaling DAC
The SI technique is a natural approach in a
CMOS process. The current sources are
typically implemented with cascode NMOS
or PMOS transistors.
+ Very high power efficiency since all power
is directed to the output
+ Quite small area for resolution less than
10bits
+ Very fast
- Sensitivity to devices mismatch
- Glitches are the major limitation for high-
speed DACs that have the digital logic
directly connected to switching signals
To achieve monotonicity and reduce the
influence of glitches, the thermometer code
can be used or DAC should be segmented.16
8
Glitches
Glitches are the major limitation during high-speed DACs, which have
digital logic directly related to switching signals. Glitches are mainly
the result of different delays occurring when switching different
signals.
Glitches can be reduced by: limiting the BW (C in parallel with Rf,
which reduces the speed), using S/H at the output, or by using
thermometer-code.
17
2.2. Thermometer-Code Current-Steering D/A Converters

The unit current sources are
arranged in a 2-dimensional array
with an optimum shape – a
square with 16 rows and 16
columns if N=8 bits resolution.
The simplest thermometer
selection is sequential by row and
column starting from the corner of
the array. Current is switched to
the output when both the row and
column are high.
+ Inherent monotonicity
+ Good DNL performance
+ Reduced glitches noise
- Large number of identical current
sources
- Random mismatch of unity current
sources affect DAC linearity. A
more complex selection technique
18
IL2220/Spring 2008 Ana Rusu can reduce nonlinearity.
9
3. Charge Redistribution DACs
Basic idea - to use a programmable array of capacitors. Charge
scaling DAC are not popular stand alone circuits (only in ADCs)
because they required buffer to drive resistive loads.
Idea: to replace the input capacitor of an
SC gain amplifier by a programmable
capacitor array of binary-weighted
capacitors or thermometer-coded.
The charge stored on a number of scaled
capacitors is used to performed the
conversion (capacitive divider).
+ Insensitive to opamp input-offset
voltage, 1/f noise, finite opamp gain
-Matching of capacitors – use unit
elements
- Number of elements increases
exponentially with N
- Ron switches
- Finite BW of opamp
- Carefully generated clock waveforms
required to minimize the voltage
if its not signal dependent dependence of clock feedthrough.
19
3.1. A binary-array charge-redistribution DAC
- Usually, the weighted capacitors are created using a number of unit

capacitors.
- A reset phase preceed the conversion phase to discharge the capacitors
- The bit sign is obtained by interchanging the clock phases.
20
10
3.2. A thermometer-code charge-redistribution DAC
All unit capacitors
21
4. Hybrid & Segmented DACs
Need to realize a trade-off in area and component ratios.

It uses different architectures to improve the overall performance.
Hybrid DAC
Combines the various scaling methods in order to get the best
characteristics of each scaling approach. It is possible to combine
tapped resistor strings with SC techniques in different ways.
Segmented DAC
Combines DACs using similar scaling methods. The individual DACs or
subDACs can be combined and summing their analog outputs together
for the overall analog output.
Basic idea: the top few MSBs in one segment and the rest of LSBs in
another segment. Use equal unit currents for MSBs ( in a thermometer-
code) and binary-weighted current sources for LSB’s.
· It can reduce the area for large N while ensuring monotonicity (at least
for the MSBs).
22
11
4.1. Resistor-Capacitor Hybrid D/A Converter
Resistor-string (7 MSBs)
determines which pair of
voltage across a single R is
passed on the 8-bit SC
array
SC Binary-weighted
(8LSBs) performs an
interpolation between the
pair of voltages
Guaranteed monotonic
15 bit at 100kHz, 10mW,
assuming the SC array
accuracy to only 8-bit.
23
4.2. Segmented D/A Converter

Trade-off between area and linearity
SFDR/Glitch amplitude limited by the segment MSB
A coarse (2MSBs) thermometer-code current switches and a fine
(4LSBs) binary-weighted current switches
A 6-bit segmented DAC

The coarse and fine output currents
are added and converted into a voltage
Generate equal currents
Its accuracy requirements are

very relaxed (not guaranteed monotonic)
VSS 2 MSBs 4-bit binary LSB segment

coarse fine 24
12
Segmented D/A Converter
Thermometer code
&
unit capacitors
Binary-weighted
capacitor-array
25
Special Improvement Techniques

To reach very high performance, some additional techniques can or
must be used: calibration, trimming of internal reference values,
randomization, dynamic element matching
Use of an additional DAC

to compensate and
calibrate errors in the
transfer function of the
original DAC.
Randomization of bits in
a thermometer-coded
DAC. The matching error
becomes uncorrelated
with the signal.
26
13
Dynamically Matched Current Sources
• In high resolution DACs the mismatch of current sources must be
small.
• Use the dynamic technique with current switching for realizing very
well matched current sources.
A 16 bit audio DAC: 92 dB
SNDR/94 dB SNR, 20mW at
3V supply voltage
- 6MSBs thermometer-code
current-mode:(63+1) accurately
matched current sources.
- 10LSBs binary array (reduced
accuracy requirements)
Each current source is
periodically calibrated with a
single Iref and a shift register.
Idi do not need precisely equal
Iref, but do need to accurately
match each to other Extra current
(independent of mismatch and source for continuously
operation even
charge injection). one Idi is calibrated
27
Dynamically Matched Current Sources

Calibration Technique
Current source connected to Iref, Id1 remains nearly equal Iref assuming VDS
Q1 diode connected doesnt change and small charge injection. Id1
determined by V on Cgs
Major limitation: charge injection and clock feedthrough of S1
Needs: Cgs and Vgs large
Solution: Add 0.9Iref parallel to Q1 and then Q1 needs only to source a
current of 0.1Iref. Then a large, low-gm transistor can be used (W/L=1/8)
28
14
Summary
Source: Holberg 29
Source: Wilkner 30
15
Source: Wilkner
31
Summary
The usual trade-off in D/A converter design is

between resolution and bandwidth
Implementation techniques: voltage-scaling, current
steering, charge-redistribution, etc.
Different approaches differ in speed, chip area,
power efficiency, achievable accuracy, etc.
It is necessary to find out which is the best
architecture for a specific application.
32
16
References
[1] David A. Johns, Ken Martin, Analog integrated circuit

design, Wiley & Sons, Inc.m 1997.
[2] Behzad Razavi, Principles of data conversion system
design, IEEE Press, 1995
[3] Philip E. Allen, Douglas R. Hollberg, CMOS analog
circuit design, Oxford University Press, 2002.
[4] M. Gustavsson, J.J. Wikner, and N. N. Tan, ”CMOS
Data Converters for Communications” Kluwer 2000.
[5] Franco Maloberti, Data Converters, Springer, 2006
33
17

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IL2220

D/A Conversion is accomplished through the scaling (division or

Introduction - Digital-to-Analog Conversion

Nyquist-Rate DACs can be classified by:

Thermometer-code differs from a binary code in that a thermometer-code

1. Voltage Scaling DACs

1.1. Resistor-String DACs

Resistor-string DAC with logic decoding

Multiple R-string DAC

• Are not intrinsically monotonic; require tight device

1.2. Binary scaled DACs

Popular for bipolar technology where high-quality resistors are available.

R-2R versus Binary-weighted

C. Improved R-2R ladder DAC

Equal currents flow through all switches.

Method to build a thermometer-code: build (2N-1) equal-sized resistors and

2. Current-Steering DAC (Current-Switch DAC)

2.2. Thermometer-Code Current-Steering D/A Converters

3.1. A binary-array charge-redistribution DAC

- Usually, the weighted capacitors are created using a number of unit

All unit capacitors

4. Hybrid & Segmented DACs

Need to realize a trade-off in area and component ratios.

4.2. Segmented D/A Converter

A 6-bit segmented DAC

Generate equal currents

Its accuracy requirements are

VSS 2 MSBs 4-bit binary LSB segment

Special Improvement Techniques

Use of an additional DAC

Dynamically Matched Current Sources

 The usual trade-off in D/A converter design is

[1] David A. Johns, Ken Martin, Analog integrated circuit

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The usual trade-off in D/A converter design is