İSTANBUL ÜNİVERSİTESİ – CERRAHPAŞA

MÜHENDİSLİK FAKÜLTESİ
BİLGİSAYAR MÜHENDİSLİĞİ BÖLÜMÜ

BİLGİSAYAR MİMARİSİ DÖNEM PROJESİ

Pipelined Processor Implementation

Team members :

Muhammed Mubakeroğlu 1306180164

Dema kalahji 1306180160
Mueyyed garzuddin 1306180132
Dua Mimar 1306180151
Humam alayad 1306180155
Kifah kenco 1306180169
1.Introduction

In our project, we designed a simple 16-bit RISC processor with seven 16-bit
general-purpose registers: R1 through R7. R0 is hardwired to zero and cannot be
written, so we are left with seven registers.

We also used one special-purpose 16-bit register, which is the program counter (PC).
All instructions are 16 bits.

We divided the work into several steps:

1. Circuit design using the Draw.Io program.

2. Design of single datapath circuit and Pipeline circuit
3. Implementation of circuits on Logisim.
4. Test single cycle datapath by running a sequential instruction as a program to
an array to find sum of two arrays and save the result to first array ( according
to doctor request)
5. Think about how the processor could be developed in the future.

We used two different types of memory 1.ROM for instruction memory 2.RAM for stored data

Most of our works was in the sub circuits like Register file , alu…..etc

We add new parts to the sub circuit to ensure all works is done

For example, the multiplexer which have 2 input we made it with 4 inputs

to choose between Rs and Rt and R1 to R7 to determine the register destination

In this circuit, to ensure the correct selection of multiplexer between many circuits we had to
make several gates like AND, OR… this selection depends on single branch, single J and
single JR instruction. All of this instruction determines the second multiplexer which value
will be taken.

The 4. multiplexer determines JR instruction if it selects 1 it will jump to the address which is
stored in Rs register else it will jump to the address that will be determined by J instruction

The 5. multiplexer it selects between branch equal and jump instruction which controlled by
control unit

The 6. multiplexer it select between the result that come from ALU or LUS ,JAL instruction

The 7. multiplexer selects between the values that come from the 6. multiplexer and coming
from the memory.
 Figure: 16-Bit Single Cycle Processor Schematic

2.Register File :

Implement a Register file containing Seven 16-bit registers R1 to R7 with two read
ports and one write port. R0 is hardwired to zero.

In “Register File”, there are 16 registers to hold data in CPU and they are open
to write or read operation for only specific “rs” and “rt”. “rs” and “rt” represent
address bits of the register. Since there are 8 registers, we have only used the
least significant 3 bits of “rs”, “rt” and “rd”. “rd” works to

It takes 16 bits of data as input and writes this value to 8 different registers. The
register that the data will be written into is determined by the data that comes to
the decoder.

To identify the value that enters the decoder, 3 multiplexers have been used.
The first one is used to identify which register to write. This writing operation
will be done in ALU or from memory . Then the second selection is done by
the second multiplexer. It will decide which registers will be read. Reading
operations will be done in Register file and other different ways.
Lastly, by using the last multiplexer, which data to write on the registers will
be decided. This operation is done in ALU .

There are 7 registers and according to the output of the decoder, reading or
writing operations are done. The system gives the two related registers as an
output so that they will be operated accordingly.determine where to write
calculated data in register file. “Write data” collects data to be written in
registers from ALU or memory. “Data 1” and “Data 2” pins represent the data
which come from registers that are selected by “rs” and “rt”. “regWrite” is a
control signal to control whether a data is to be written in register file or not.

Figure: Register File

3.ALU :

ALU (Arithmetic Logic Unit) takes 4 inputs which are “Data1”, “Data2”, and
two input as selection the convenient operation . In ALU there are several
arithmetic operations (i.e. addition, multiplication, …). “op” code selects which
operation will be done by using a multiplexer . “Data1” and “Data2” are 16-bits
data coming from the register file or one of them from “Immediate” and they
will be entered into operation by ALU. On the “Data2” branch, there is a
multiplexer which is controlled by the Control Unit to determine if it is a
R-Type or I-Type operation. According to the type of operation “shamt”
represents shift amount. Since ALU has a shifter circuit , “data2 ” is used to
shift “data1 ”. There is also “zero” output from ALU to indicate whether
“Data1” and “Data2” are equal or not or “less than”.

Figure:ALU circuit

4.ALU Control :
It control the instruction that come from the ALU
it takes 4 signal from control unite and 2 signals from function based on them
we decide the type of instruction (add,or,and,sll…)
we have 2 outputs , the left one controls the type of instruction (logical ,
mathematical …..)
the other one the sub instructions.
 Figure:ALU control

5.Control Unit :

Control unit is used to determine select bits of all multiplexers in the circuit to
achieve correct operation. Operation can be arithmetic, load, read, branch or
unconditional branch.

The last 5 signale it's so important because they go to the ALU control.

to divide the 16 bit instruction to R-type , I-type and J-type .

The input of the control unit = 5 bit (opcode of the instruction).

For example: the opcode of AND instruction = 00000

The signal control of AND instruction

ALU ALU
Reg Reg Reg ALU Bran Mem Mem TO TO ALU ALU ALU ALU
Des1 Des2 WR SRC ch Bne J JR wR Rd Reg Reg2 LUIS OP1 OP2 OP3 OP4

0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

For each instruction we put AND gate

For first 4 instruction AND , OR , XOR , NOR we used one and gate because
this instructions have the same control signal
For the add, sub, slt, sltu instruction we used one and gate because these
instructions have the same control signal.

For the remaining instruction we used one AND gate for each of them.

The output of each OR gate is a control signal.

JR control signale don't need to take OR gate because it is set by 1 only with
JR instruction.
Figure: Control Unit
6.Pipeline Design:

The pipelined processor takes the same control signals as the single-cycle
processor and therefore uses the same control unit. The control unit examines
the opcode and funct fields of the instruction in the Decode stage to produce
the control signals. These control signals must be pipelined along with the data
so that they remain synchronized with the instruction.
The entire pipelined processor with control. RegWrite must be pipelined into
the Writeback stage before it feeds back to the register file, just as WriteReg
was pipelined.

We start by building the datapath and control of a single-cycle processor and

ensure its correctness. We have succeeded in doing this, converting our design
and implementing a pipelined-datapath and its control logic. A five-stage
pipeline was constructed and we added pipeline registers between stages.

We designed the control logic to detect data dependencies among instructions.

For branch and jump instructions, we reduced the delay to one cycle only. And
stalled the pipeline for one clock cycle after a jump or a taken branch
instruction.

Also we stalled the pipeline after a LW instruction.

Figure : Pipeline Design

 Figure: Forward Control Unit

7.Logisim Design :

In the last step of the project, the control unit is designed and all
components are gathered. Control unit basically creates the needed
signals for the components. For the control unit, a finite state machine
with a few states is created.
8.TEST PART :

8.1. ALU Testing :

- We test ALU Circuit with multi situation according to the below control table (where 1)
Logic 2) Shift controls 3) Arithmetic 4) Comparing control bits are taken from same
place):

Op selection

Shift 00

SLT 01

Arithmetic 10

Logic 11

Logical Shift Selection Arithmetic Comparing

Selection

AND SLL ADD SLT 00

OR SRL SUB SLTU 01

NOR SRA ADD SLT 10

XOR ROR SUB SLTU 11

- Next Page you can find screenshots for executing some instruction on this circuit:
SLL:

SLT:
ADD:

SUB:
OR:

AND:

Some equations of this circuits

8.2. ALU Control testing :
This circuit takes control bits from the control unit and configures it to let the ALU
work correctly regarding the shared instruction table. It works fine as we test it and
here’s some examples:
SLTU:

SLL: if(Is R type) is of then fn will be discarded as shown in image

8.3. Register file testing :
The aim of this circuit is to hold data temporarily while executing cpu instructions, r0
is zero as mentioned in the first photo. Below also some tests were done on this
circuit and it works great.

R0 = 0000 hex (zero)

R1 = 1111 hex
R2 = 10f2 hex

READING EXAMPLE :
WRITING EXAMPLE: writing: 0xF0F1 to the $r7

8.4.Control Unit Test:

This circuit takes op code 5 bit and decode it to required control signals , below some
tests of this circuit:
a- ORI:
b- JAL:
9.4.Shifter testing :

This Circuit is a sub circuit of ALU circuit which is responsible of the 4 shifting
functions:

a- SLL: 3 bit

b- SRL: 3 bit
c- SRA: 3 bit (keeping signal bit)

d- ROR: 3 bit
9.Notable Feature For Our Processor :
We can add 8 instructions because the opcode = 5 .

We can change the Register write control signal to 2 bit so we have places to
write data.

We can add division instructions. we have to modify just ALU.

DOWN THERE are some example: we can add instruction:

sub rd,rt,rs ;rd = rs_(rs+rt)

We can also add multiply instruction : mult rs , rt ; hi , lo = rs*rt

And we can add instruction :

addm rd , SBT(RS) ; RD = M [RS] + SBT