Chapter 13 Floor Planning of Mixed-Signal IC

- Mixed-Signal IC Floor Plan

- Examples of ADC Floor Plan
- Examples of DAC Floor Plan

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 Mixed-Signal IC Floor Planning

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 Chip Floor Plan Example

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 Initial Floorplan

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 Power Distribution

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 Clock Distribution

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 Standard-Cell-Based ASIC

◆ Logic cells caned standard cell library (AN , OR, multiplier, DFF … )
◆ Pre-designed mega-cells (fully-custom functions, system-level macros,
fixed blocks, cores, functional standard blocks)
◆ All mask layers are customized transistor and interconnect
◆ Custom blocks can be embedded
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 Routing Cell-Based IC

◆ Cell height
◆ Feed though
◆ Channel routing
◆ Power lines 8
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 Leaf Cell

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 Analog Floorplan & Power Routeplan

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 Power Routeplan in Sensitive Channel

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 Floorplan of Chip

TRACK-
OP AMPS & CLOCKED SIGNAL
AND-
SWITCHS HOLD OUT

DPGAS AND INTEGRATING

CAPACITOR DECODE
R
DPGA SWITCHES
PROGRAMING BUS
DPGA SWITCHES
SIGNAL
IN
DPGAS & INTEGRATING
CAPACITORS

ANALOG ROUTING
BETWEEN INTEGRATORS
CLOCK
GENERATOR
OP AMPS & CLOCKED
SWITCHES

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 Programmable Logic Devices

◆ No customized mask layers or logic cells

◆ Fast design turnaround
◆ A single large block of programmable interconnect
◆ A matrix of logic macro cells that usually consist of programmable array
logic follow by a flip-flop or latch
- Read Only Memory (ROM) , mask ROM
- Programmable ROM (PROM)
- Electrical Programmable ROM (EPROM)
- Electrical Erasable PROM (EEPROM) 13
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 Field Programmable Gate Arrays (FPGA)

◆ None of the mask layers are customized

◆ A method for programming the basic logic cells and the interconnect
◆ The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic
◆ A matrix of programmable interconnect surrounds the basic logic cells
◆ Programmable I/O cells surrounds the core
◆ Very shot design turnaround
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 Structured Gate Array

◆ Only interconnection is customized

◆ Custom blocks embedded (e.g. memory)

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 PAD Placement

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 Floorplan of the Eight-Order Modulator

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 Program Counter with Stack Pointer-Chip Floorplan

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 RAM Architecture

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 Block Diagram of the ADC

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 8-Bits 250MHz Per Second ADC Operation Without a
Sample & Hold

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 (a) with separated unit resistor (b) without separated
unit resistor
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 Input Distribution

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 Intermeshed Resistor Reference Ladder

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 Ladder Loading Correction Circuit

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 Reference Ladder Configuration in the Second Stage

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 Resistor Network For the Video DAC

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 (a) pattern folding of comparator (b) continuous
service layout of analog ground&supply voltage line
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 First-Stage Comparator

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 Basic Current in a DRL Comprising Comparators with
Differential Ential-Pair Stages

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 First-Stage Layout

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 ADC Floorplan

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 Analog Preprocessing

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 Floorplan of Folding and Interpolating Converter Versus
Full-parallel Converter

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 Full-Parallel Flash ADC signals

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 DAC

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 12bit Segmented Current-Steering DAC

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 Basic Architecture of DAC

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 Current Distribution of Current Source

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 Two-Step Decoding

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 High-Speed Decoding Circuit

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 DAC Architecture

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 Floorplan of the Proposed Segmented DAC Architecture

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 Circuit Diagram of LSB Cascode Current Source

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 3.3v-110Mhz 10-bit CMOS Current-Mode DAC

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 (a) unary current source implemented as one unit (b)
as four units in parallel c-as 16 units in parallel
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 Different Layout Arrangement For the Device M2 and
Mc in Each Current Source (4 unit cell & 5 unit cell)

M2 M2 M2 M2

Mc
Mc
M2

M2 M2

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 The Proposed Segmented 6+2+4 Current Steering
Architecture

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 Double Centroid Switching Scheme

M0 B0 B0 B1 B0 M0

16 14

8 4 2 6 6 2 4 8

5 1 3 7 7 3 1 5

13 15 15 13

B2 B1 B1 B4

B2 B1 B1 B4

13 15 15 13

5 1 3 8 7 3 1 5

7 4 2 6 6 2 4 8

16 14 14 16

M0 B0 B0 B1 B0 M0

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 Switching Sequence of Matrix

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 Symmetrical Switching

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 Poly-Diffution Capacitor with Top-Plate Shield

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 Unit Capacitor For C-2C Ladder Implementation

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