BINARY to GRAY code convertor

Code:-
library IEEE;
use IEEE.std_logic_1164.all;
entity bcdTOgrey is
port(B: in std_logic_vector(3 downto 0);
G: out std_logic_vector(3 downto 0));
end bcdTOgrey;
architecture BCDtoGREY of bcdTOgrey is
begin
G(3)<=B(3);
G(2)<=B(3) xor B(2);
G(1)<=B(2) xor B(1);
G(0)<=B(1) xor B(0);
end BCDtoGREY;

Output:-
GRAY to BINARY code convertor
Code:-
library ieee;
use ieee.std_logic_1164.all;
entity grayTObinary is
port(G: in std_logic_vector(3 downto 0);
B: out std_logic_vector(3 downto 0));
end grayTObinary;
architecture GRAYtoBINARY of grayTObinary is
begin
B(3)<=G(3);
B(2)<=G(3) xor G(2);
B(1)<=G(3) xor G(2) xor G(1);
B(0)<=G(3) xor G(2) xor G(1) xor G(0);
end GRAYtoBINARY;

Output:-
BCD to EXCESS 3 code converter
Code:-
library ieee;
use ieee.std_logic_1164.all;
entity excess is
port(
B: in std_logic_vector(3 downto 0);
A: out std_logic_vector(3 downto 0));
end excess;
architecture dataflow of excess is
begin
A(0) <= not B(0);
A(1) <= ((not B(1)) AND (not B(0))) OR (B(1) AND B(0));
A(2) <= ((NOT B(2)) AND B(0)) OR ((NOT B(2)) AND B(1)) OR (B(2) AND (NOT B(1))
AND (NOT B(0)));
A(3) <= B(3) OR (B(2) AND B(0)) OR (B(2) AND B(1));
end dataflow;

Output:-
BCD to 7 SEGMENT code converter
Code:-
library ieee;
use ieee.std_logic_1164.all;
entity segment is
port(
B: in std_logic_vector(3 downto 0);
A: out std_logic_vector(6 downto 0));
end segment;
architecture dataflow of segment is
begin
A(0) <= B(3) or (B(2)and not B(1)) or (B(1)and not B(0)) or (B(1)and not B(2));
A(1) <= B(3) or (not B(1)and not B(0)) or (B(2)and not B(0)) or (not B(1)and B(2));
A(2) <= (not B(2) and not B(0)) or (B(1)and not B(0));
A(3) <= B(3) or (B(1)and not B(2)) or (B(1)and not B(0)) or (not B(2)and not B(0)) or
(B(2)and not B(1)and B(0));
A(4) <= B(2) or not B(1) or B(0);
A(5) <= not B(2) or (not B(1)and not B(0)) or (B(1)and B(0));
A(6) <= B(3) or B(1) or (not B(2)and not B(0)) or (B(2)and B(0));
end dataflow;

Output:-