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  • Vlsi Exp 8 2004051

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    Arvindh Sudhakar
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    This document describes the design and simulation of a 4-bit array multiplier using Verilog. It includes the Verilog code for the array multiplier module, RTL schematic, test vectors in a test bench, and simulation waveform. Half adders and full adders are used as basic building blocks. The design is synthesized to target a specific FPGA by providing an implementation constraint file mapping inputs and outputs to FPGA pins.

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    VLSI EXP 8 2004051

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    This document describes the design and simulation of a 4-bit array multiplier using Verilog. It includes the Verilog code for the array multiplier module, RTL schematic, test vectors in a test bench, and simulation waveform. Half adders and full adders are used as basic building blocks. The design is synthesized to target a specific FPGA by providing an implementation constraint file mapping inputs and outputs to FPGA pins.

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    17 views5 pages

    Vlsi Exp 8 2004051

    Uploaded by

    Arvindh Sudhakar
    This document describes the design and simulation of a 4-bit array multiplier using Verilog. It includes the Verilog code for the array multiplier module, RTL schematic, test vectors in a test bench, and simulation waveform. Half adders and full adders are used as basic building blocks. The design is synthesized to target a specific FPGA by providing an implementation constraint file mapping inputs and outputs to FPGA pins.

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    of 5

    EXP.

    NO: 8 DESIGN AND STIMULATION OF MULTIPLIERS AASHICA A C


    DATE: 03/05/2023 2004051

    4-BIT ARRAY MULTIPLIER

    VERILOG CODE

    BEHAVIOURAL MODELLING

    module array_mul(product,inp1,inp2);

    output [7:0]product;

    input [3:0]inp1;

    input [3:0]inp2;

    assign product[0]=(inp1[0]&inp2[0]);

    wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;

    HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));

    FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);

    FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);

    HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);

    HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));

    FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);

    FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);

    FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);

    HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));

    FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);

    FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);

    FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);

    endmodule
    EXP. NO: 8 DESIGN AND STIMULATION OF MULTIPLIERS AASHICA A C
    DATE: 03/05/2023 2004051

    RTL SCHEMATIC

    SIMULATION WAVEFORM
    EXP. NO: 8 DESIGN AND STIMULATION OF MULTIPLIERS AASHICA A C
    DATE: 03/05/2023 2004051

    module HA(sout,cout,a,b);

    output sout,cout;

    input a,b;

    assign sout = a^b;

    assign cout = a&b;

    endmodule

    module FA(sout,cout,a,b,cin);

    output sout,cout;

    input a,b,cin;

    assign sout = a^b^cin;

    assign cout = ((a&b)|(b&cin)|(a&cin));

    endmodule
    EXP. NO: 8 DESIGN AND STIMULATION OF MULTIPLIERS AASHICA A C
    DATE: 03/05/2023 2004051

    IMPLEMENTATION CONSTRAINT FILE:

    NET "inp1[0]" LOC = "P57";

    NET "inp1[1]" LOC = "P56";

    NET "inp1[2]" LOC = "P55";

    NET "inp1[3]" LOC = "P51";

    NET "inp2[0]" LOC = "P50";

    NET "inp2[1]" LOC = "P48";

    NET "inp2[2]" LOC = "P47";

    NET "inp2[3]" LOC = "P46";

    NET "product[0]" LOC = "P74";

    NET "product[1]" LOC = "P67";

    NET "product[2]" LOC = "P66";

    NET "product[3]" LOC = "P64";

    NET "product[4]" LOC = "P62";

    NET "product[5]" LOC = "P61";

    NET "product[6]" LOC = "P59";

    NET "product[7]" LOC = "P58";


    EXP. NO: 8 DESIGN AND STIMULATION OF MULTIPLIERS AASHICA A C
    DATE: 03/05/2023 2004051

    TEST BENCH:

    module array_mul_tb;

    reg [3:0] inp1;

    reg [3:0] inp2;

    wire [7:0] product;

    array_mul uut (

    .product(product),

    .inp1(inp1),

    .inp2(inp2)

    );

    initial begin

    inp1 = 0; inp2 = 0;

    #100;

    inp1 = 10; inp2 = 12;

    #30;

    inp1 = 13; inp2 = 12;

    #30;

    inp1 = 10; inp2 = 15;

    #30;

    inp1 = 11; inp2 = 15;

    #30;

    inp1 = 12; inp2 = 15;

    #30;

    end

    endmodule

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