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10-28-16 VM CPU Vsphere World
10-28-16 VM CPU Vsphere World
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
vRealiz vmw- - 4 11,70 11,70 6.81 0% 1,946 1,573 0% 0.000 0% 0.8 % Powe
e dell3. Core 4 4 % .77 .87 4% red
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vMA vmw- - 1 2,660 2,660 3.18 0% 168.4 131.4 0% 0.000 0% 0.93 Powe
dell1. Core MHz % 7 MHz 4% % red
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Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )
Name Pare Confi Confi Entitl Limit Cont Swap Dem Usag Swap IO Co- Idle Powe
nt gure gure eme from entio wait and e Wait Wait stop (%) r
Host d d nt Abov n (%) (%) (MHz (MHz (%) (%) (%) (at State
(MHz (Core (MHz e (at ) (at ) (at (at (at (at CPU|
) s) ) (MHz CPU| CPU| CPU| CPU| CPU| CPU| CPU
) CPU CPU CPU CPU CPU CPU Cont
Cont Cont Cont Cont Cont Cont entio
entio entio entio entio entio entio n (%)
n (%) n (%) n (%) n (%) n (%) n (%) maxi
maxi maxi maxi maxi maxi maxi mum
mum mum mum mum mum mum )
) ) ) ) ) )