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Ladder Diagram and Petri-Net-Based Discrete-Event Control Design Methods

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IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART C: APPLICATIONS AND REVIEWS, VOL. 34, NO. 4, NOVEMBER 2004
Ladder Diagram and Petri-Net-Based Discrete-Event
Control Design Methods
Shih Sen Peng, Senior Member, IEEE, and Meng Chu Zhou, Fellow, IEEE
Abstract—Ladder diagrams (LDs) for a programmable logic
controller are a dominant method in discrete event control of
industrial automated systems. Yet, the ever-increasing function-
ality and complexity of these systems have challenged the use of
LDs to design their discrete-event controllers. Researchers are
constantly pursuing integrated tools that eliminate the limitations
of LDs. These tools are aimed not only for control but also system
analysis, evaluation, and simulation. For the past several decades,
Petri nets (PNs) have emerged as an important tool to provide an
integrated solution for modeling, analysis, simulation, and control
of industrial automated systems. Different types of PN-based
controllers are proposed and intended to apply in the industry.
There is a need for more benchmark studies of PN and LD
methods in order to form a structured and integrated framework
for logic control software development. This paper, for the first
time, presents a comprehensive survey on the recent methods for
discrete event control design.
Index Terms—Discrete event control system (DECS), ladder dia-
gram (LD), Petri nets (PN), programmable logic controller (PLC).
I. INTRODUCTION
I N INDUSTRIAL practice, programmable logic controllers
(PLCs) are programmed using a low-level language such
as ladder diagrams (LDs), resulting in large and unwieldy pro-
grams. The overall design is experience-based, and verification
is typically done only through experiments or simulation. Due
to the complexity of control programs and manufacturing sys-
tems, either verification option is time-consuming and expen-
sive. Also, there are too many different logic control-program-
ming languages used by the industry. In June 2000, a workshop
with participants from industry and academia held at the Uni-
versity of Michigan discussed the coordination and sequencing
problems.
They try to create an understanding of the gaps that exist be-
tween the theories of discrete-event control systems (DECS) and
their industrial implementation. They indicate that the prolifer-
ation of multiple standards makes true standardization difficult
in practice. Hence, no consensus of logic control emerges be-
Manuscript received March 1, 2002; revised October 31, 2003. This work was
supported in part by the New Jersey Commission on Higher Education via the NJ
I-TOWER project of New Jersey Institute of Technology (NJIT), by the CNSF
under Grant No. 60228004, and by the Mechatronic Control System Research
Project at the Chinese Military Academy, Taiwan. This paper was recommended
by Associate Editor J. Wang.
S. S. Peng is with the Department of Mechanical Engineering, Chinese
Military Academy, Feng-Shan City, 830 Taiwan, R.O.C. (e-mail: pengss@
cc.cma.edu.tw).
M. C. Zhou is with the Department of Electrical and Computer Engineering,
New Jersey Institute of Technology, Newark, NJ 07102 USA and also with the
Lab of Complex Systems and Intelligent Science, Institute of Automation, CAS,
Beijing 100080, China (e-mail: zhou@njit.edu).
Digital Object Identifier 10.1109/TSMCC.2004.829286
1094-6977/04$20.00 © 2004 IEEE
523
tween academia and industry. Industry expresses a desire for
researchers to carry out a critical comparison of the capabilities
of different approaches and offer a better education in logic con-
trol. Industry also perceives that new languages are required to
remove the barriers and build a collaboration avenue between
academia and industry. This paper reviews some recently pub-
lished papers on Petri nets (PNs) and LD-based methods and
their conversion for the control design and emphasizes that PN
can be developed to establish an open system controller to var-
ious PLC in more flexible and understandable way than LD is.
II. LADDER DIAGRAMS
In 1968, the Hydromatic Division of GM wrote a design spec-
ification for a new type of PLC that would eventually be pro-
grammed using LD. LDs are a graphical programming language
that uses software “device” to emulate the hardwired devices of
the relay ladder logic scheme [23], [28]. They are developed
to smooth the transition from relay control systems to PLC.
The initial intent of LD is to allow plant maintenance personnel
to troubleshoot, maintain and make minor modifications of the
system. PLC has greatly improved the flexibility of DECS and
reduced the downtime required to make modifications. How-
ever, the larger DECS, the more difficult to determine the initial
design specifications by examining the control logic. Further-
more their usage is limited only to control the system but not
to analyze and evaluate the qualitative and performance char-
acteristics. This still holds true today despite the definition of
other languages in the IEC 1131-3 standard [22]. The standard
suggests five languages for PLC programming: instruction list
(IL), structure text (ST), function block diagram (FBD), sequen-
tial function chart (SFC), and finally LD. It is claimed in IEC
1131-3 that all five languages are equivalent. Yet, this claim
is not verified in the standard since none of the suggested lan-
guages are design methodologies, nor are they widely accepted
or tested, with the exception of LD [32]. Due to these reasons
modern DECS have challenged the use of LDs to design se-
quence controllers. Researchers are seeking integrated tools that
eliminate the limitations of LDs. Such tools aim not only at con-
trol, but also system analysis, evaluation, and simulation. PN
originated from the field of computer science hold a great po-
tential to evolve into such a tool as evident from their versatile
applications in DECS.
III. PNS
A manufacturing system can be viewed as a sequence of dis-
crete events that can be sequential, asynchronous, concurrent
and mutually exclusive. PNs have proven to be a useful tool
524 IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART C: APPLICATIONS AND REVIEWS, VOL. 34, NO. 4, NOVEMBER 2004
for its modeling, control and performance evaluation [25], [47],
[49]. Different types of PNs are used to model, analyze, and con-
trol discrete manufacturing systems briefed below.
A. Ordinary PNs
Ordinary PNs have several basic elements, as follows.
1) Places (circles) are used to represent conditions
(true/false), resource availability, or a process status.
2) Transitions (bars) are used for the occurrence of events.
3) Input functions are defined as “arcs” from places to
transitions.
4) Output functions are defined as “arcs” from transitions to
places.
They define a PN structure. The PN state is defined by its
marking denoted as an -vector M, where is the total number
of places. Its component , represents the number of tokens
in place . In order to simulate the dynamic behavior of a system
or the flow of tokens, a state or marking is changed according to
the defined “firing” rules. These firing rules are also referred to
as the rules of a token player game. For more information, refer
to [25], [49].
B. Timed PNs
Time can be incorporated into ordinary PN by associating a
deterministic delay to a transition. This results in a timed tran-
sition PN. If the transition times are random variables, the re-
sulting PN is a stochastic timed PN (STPN) [25], [49]. The tran-
sition times may follow one of several distributions. If they all
follow an exponential distribution, these nets become Stochastic
PNs. When a transition becomes enabled in an STPN, it fires
after a random interval time. This is useful for modeling op-
eration, failure, and repair times of individual machines. If an
STPN contains both immediate transitions with zero time delay
and timed ones with exponential distribution, then a generalized
stochastic PN results. This is useful for modeling activities that
occur almost instantly along with processes that take a longer
random amount of time.
C. Colored PNs (CPNs)
The CPN [15], [16], [45] is an important extension to ordi-
nary PN. It provides compact models for large systems with a
higher level of abstraction and an improved graphical represen-
tation capability. The analysis of CPNs is mainly done with in-
variant matrix-based techniques. It exploits the symmetries that
exist in a PN model by grouping identical places and transitions
together, and defining appropriate matrix functions to represent
the nodes, arcs, colors, marking, and invariants.
D. PNs as Real-Time Controllers
A controller in a hierarchical structure must be able to process
commands sent from higher levels, to synchronize the activ-
ities of the equipment below it, and to report status back. In
DECS, there is a need for a large number of controllers and
therefore a large amount of software development. More impor-
tantly, the controllers should be able to handle the addition of
equipment and should be easily transportable to other worksta-
tions. Some common controllers are PLC, microprocessors, and
PC and coded in general purpose languages or LD. The problem
is that the mapping between sequential information and the code
is not straightforward, and hence the sequencing information is
hard to see by just looking at the code. The PN can be used to
design the sequence of operations in a manufacturing system.
As transitions fire, events are made to occur and so the flow
of tokens through the net can be used as a real-time controller.
The controller can also be analyzed for deadlock, boundedness,
etc., and evaluated against various performance measures. PNs
have been augmented and implemented in a variety of ways to
achieve real-time control as shown in Table I [44]. They include
the use of a compiler [5], interpreter [26], [41], execution algo-
rithms and software [2], [6], simulator [31], and/or token players
[44], [46].
IV. PN- AND LD-BASED METHODS AND THEIR CONVERSION
For the past decades, researchers have developed many de-
sign methods based on PN and LD from specification for PLC
programming.
From specification, the existing work intends to:
1) design LD and PN directly for design comparison;
2) design and convert LD to PN for analysis and validation;
3) design and convert PN to LD for PLC implementation.
A. From Specifications to PN and LD for Design Comparison
The specification and discrete-event control of a system using
PN can be dated back to [5], [30], and [41]. Boucher et al. [2]
developed a controller for a robot and numerically controlled
lathe with the PN and LD loaders and compliers. They compared
their control performance and reported that the PN described
the flow of the process more efficiently than the corresponding
LD. Jafari and Boucher [14] developed an interface between
a high-level specification of a system and its logic controller.
Their interface is based on a number of rules to transform an
IDEF0 specification into a PN-based controller and to transfer
the intermediate specification into a LD. These rules could be
used as a basis for developing an expert system to handle the
interface.
Baker and Song [1] proposed PN as a substitute for LD. They
defined an extended PN, the programmable logic controller net
(PLCNet) to simplify the PN structure by defining more com-
plex semantics. A set of operation rules is formally synthesized
in order to implement the semantics of the PLCNet. The op-
eration rules constitute those in the rule base of the tool. The
database of the simulation tool is composed of the underlying
models in the first order predicate. Their simulation tool makes a
user-friendly graphical environment. But the representation ap-
pearance is different from that of LD. For complex systems with
many I/O, the method needs a more consistent development of
the logic controllers to meet the specification formalism and de-
sign criteria.
Sato and Nose [29] described a method for automated gen-
eration of a ladder list program for a PLC used for sequence
control of industrial machinery. The method enhances the read-
ability of sequence control specification that is expressed by a
sequence of motions and logic tables. PNs specify the sequence
of motions combined with the on/off readings of sensors. Logic
PENG AND ZHOU: LD AND PN-BASED DISCRETE-EVENT CONTROL DESIGN METHODS 525

TABLE I
VARIOUS METHODS OF PN-BASED SEQUENCE CONTROL [44]

tables specify the on/off logic of switches and actuators. The

specifications that are independently expressed by PN and the
logic table are converted to the ladder list program by rules. The
generated program can be linked to the simulator of the machine
motions to simplify verification and debugging of the control
specifications. The method was proved effective through its ap-
plication to a press machine and reduced the period for making
a ladder list program by about 75% as compared with a conven-
tional method that directly prepares it.
Ferrarini and Maffezzoni [8]–[10], proposed a CAD/CAE
environment for the design, synthesis and analysis of PN-based
sequence controllers. Their representation formalism for the
particular algorithms is developed under the CAD environment
to meet the consistent requirement for both PN and LD. To
reduce the complexity of logic controller design with PN,
an incremental approach by using simple rules and theorems
to create both sequential part (SP) and standard control unit
(SCN), where SP is modeled as a PN and SCN represents a
control module developed for logic controllers. The control
unit as shown in Fig. 1 can make decisions on its own on the
basis of the values measured from the field and send them to
actuators or to other controllers through the analog-to-binary
converter (ABC), input combinatorial net (ICN), SP, and output
Fig. 1. The standard control unit developed for logic controllers by Ferrarini
et al. [8]–[11].
combinatorial net (OCN). The method allows a decomposition
of the original control problem into a number of subproblems.
The SP has been substantially modeled as a PN and the PN
properties are verified at every step of design.
Ferrarini et al. [11] also presented PN-based modular simu-
lation for logic, distributed, and real-time control systems by
using their developed CAD environment. The simulation of
PLC is essentially modeled as a module consisting of both I/O
combinational nets and an ordinary PN to implement the SP
(memory) of PLC.
Cazzola et al. [3] investigated how the performance and cor-
rectness of a logic controller algorithm are affected by the par-
ticular way in which a PN scheme is converted into an algorithm
526 IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART C: APPLICATIONS AND REVIEWS, VOL. 34, NO. 4, NOVEMBER 2004
Fig. 2. PNs and LD modeling of logic constructs [49].
running on a PLC. The interpretation rules of PN for logic con-
trol were established.
Venkatesh et al. [43]–[44] presented a methodology for auto-
matic generation of PN models and proposed a new class of PNs
called real-time PNs (RTPN) from logic control specification.
The RTPN design algorithm mainly consists of: 1) dividing the
sequence of events into groups; 2) building the PN models via
top-down refinement; and 3) merging the common place/paths
within the model. An RTPN can be obtained by associating
timing, and I/O sensory information to the untimed PN. It is
an eight tuples and defined as: RTPN=(P, T, I, O, m, D, X, Y)
with the first five to represent the five tuples of the untimed PN
and the last three as extensions, timing vector (D), input signal
vector (X), and output signal vectors (Y). RTPNs are suitable at
the lower level of system control since they model the system
more realistically by naturally mapping the limit switches, start,
PENG AND ZHOU: LD AND PN-BASED DISCRETE-EVENT CONTROL DESIGN METHODS
and stop buttons to places with attributes and actuators as tran-
sitions with attributes.
The systematic methods to formulate PN for PLC and com-
pare PN and LD for industrial systems can be seen in [49]. The
modeling logic constructs by PN and LD as shown in Fig. 2 can
be used to estimate the number of basic elements needed for PN
and LD.
The comparison criteria include design complexity, under-
standability, flexibility, and response time. Design complexity
is measured by the number of the basic nodes and links. Un-
derstandability is the ability to evaluate the programmed logic,
verify its correctness, and maintain the control system. Flexi-
bility measures how easy it is to modify the control system when
the specification changes. The response time is the scan time in
LD and execution time in PN.
Several benchmark studies [42]–[44] are used to evaluate and
compare the number of nodes and links in LD and PN as a mea-
sure to compare the design complexibility and response time.
The result indicates that PN gives 50% shorter model than LD.
Zhou and Twiss [48] first use an industrial scale system to com-
pare LD and PN design method. Both LD and PN are designed in
a top-down method given the same specification and compared
for their design complexity. The result of their study concludes
that when the specification of logic design is more complex, PN
are more easily modifiable and hence maintainable than LD.
B. Design of and Conversion from LD to PN for Analysis
Jackman et al. [13] proposed a conceptual model and working
algorithm for converting relay ladder logic (RLL) to PN models
in order to provide future system designers with a common lan-
guage for design, analysis and documentation. Future and ex-
isting RLL models can be converted to PNs for verification and
validation prior to their implementation on the factory floor. The
algorithm is demonstrated using an RLL model. A comparison
of the PN and RLL is performed through an example. Neverthe-
less, the drastically increased number of the PN basic elements
has resulted in the difficulty of the PN implementation. The re-
sulting PN suffer from the same drawbacks of the original RLL
since they cannot reveal sequential, concurrent behavior of the
system by visualization compared with the PN derived directly
from the specification.
Lee and Lee [20], [21] presented a methodology of obtaining
an augmented PN from LD by introducing the new augmented
elements such as preservation arc, buffer place, and reset arc.
The augmented graph is also compared with the conventional
PN by using the timing chart to evaluate the conversion result.
A conversion table that converts the LD core functions into PN
is then constructed. This equips LD programs with the formal
analysis capability normally available in PN. The state equa-
tion of PN is used as an analysis technique to validate the cor-
responding flow mechanism of the generated PN. Yet, the total
number of nodes and links in the generated PN (164) increases
almost double than that of the original LD (84).
C. Design of and Conversion from PN to LD for PLC
Implementation
Taholakian and Hales [32] introduced a PN PLC method-
ology that designs PNs from specifications and then converts
527
Fig. 3. Implementation scheme of PN-based controllers by Taholakian and
Hales et al. [32].
them to LDs. The rules are proposed for creating PN and sub-
sequently translating to LD. This can prevent designers from
developing uncodable design. The proposed design rules derive
a PN by focusing on outputs (internal and external) and their
switching on and off, respectively one by one. The similar idea
is applied to translate a PN into an LD. The presented example
also shows that the resulting LD is less complex than the direct
translation of its SFC representation. The PN simulation is used
to validate the resulting design. The application of this method-
ology to a sizable system remains to be seen while it is a signif-
icant step to allow engineers to design LD using a PN method.
The implementation scheme of their approach can be summa-
rized in Fig. 3.
Jones et al. [17], [18] created a new concept for converting
PNs into LD using the token pass ladder logic (TPLL). This new
technique makes use of the fact that the prime control mecha-
nism within the PN is the token. The program control is achieved
through the use of flags or auxiliary relays. The methodology
is extended to embrace T-Timed PNs by using delay timers in
different contexts. The fundamental T-Timed PN structure and
their associated ladder logic equivalents have been established.
Uzam et al. [34]–[37] introduced the TPLL technique in both
methodology and application facets to convert CPN controllers
into LD. This technique can also provide a straightforward map-
ping between the basic sequencing information and the pro-
gramming steps. The fundamental T-timed PN structures and
their associated LD equivalents are described. They also devel-
oped a heuristic PN controller for DECS and a methodology
to derive structured LD. Since their advent of TPLL, the con-
version technique has been developed for ordinary, P-timed,
T-timed and Colored PNs. They also extended this technique to
design PNCs by including actuators and sensors as formal struc-
tures within PNC. They established a set of additional features
for ordinary PN that facilitate the addition of sensor readings at
transitions and both the impulse and level control of actuators,
resulting in automation PN (APN). Given a system’s specifica-
tion, an APN is first created by constructing a PN module for
each actuators on and off and sequence modules and adding en-
abling (self-loop) and disabling arcs (inhibitor arcs) for certain
specifications. Then every place is associated with a memory
word, also called counter, or bit (for a safe place). Every tran-
sition’s enabling and firing rules are converted into LD rungs
one module after another. Initialization and certain places also
need LD rungs during the conversion from APN to LD. After
the PN-based formal controller is introduced, Uzam et al. [38]
considered the IEC1131-3 standard for the possible implemen-
tations of APNs using an IL code. Then, in [39], the method-
528 IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART C: APPLICATIONS AND REVIEWS, VOL. 34, NO. 4, NOVEMBER 2004

Fig. 4. Implementation scheme of PN-based controllers by Uzam and Jones

[34]–[40].

ology is extended to embrace the IEC1131-3 LD standard for
PLC.
Uzam et al. [40], proposed a bottom-up synthesis technique
involving the construction of the reachability graph of the con-
trolled APN model of the system. A supervisor as a controller
of the system, which is obtained by using the uncontrolled APN
model and the token pass marking (TPM) rules, is related to the
forbidden state specifications. The TPM rules are obtained di-
rectly from the forbidden state specifications and implemented
through the use of a mixture of enabling arcs and inhibitor arcs,
which are connected from the corresponding places to the re-
lated controllers’ transitions. This design technique is called
C-TPM rule method. Their approach is summarized in Fig. 4.
Feldmann et al. [7] designed and implemented logic control
structures that allow a combination of the advantages of clas-
sical techniques for the development of PLC code and elimi-
nation of disadvantages such as the lack of formal validation.
They first introduced ordered colored PNs (OCPN) in combi-
nation with some extensions as a modeling tool for logic con-
trollers. The OPCN-based model of a logic control system is
made up of two main structures: a model of the coordination
control system and a submodel for some elements of the first
model, obtained after a refinement of transition. The validation
of both the model and specifications of logic control structures
are then pursued through structural analysis of the net. They then
developed a method to automatically generate code for a PLC
from a validated textual description of OCPN. A special com-
plier that generates code according to standard IEC 1131-3, the
IL, is discussed as in Fig. 5. The modeling and implementation
of a logic control system of a flexible assembly cell serves as an
illustrated example for this methodology.
Park et al. [27] proposed a control logic generation method
for machining systems using PN. Two PNs are used to repre-
sent control logic: one for the mode decision and the other for
the sequence. The PN control logic for each operation can be
generated from the operation module templates by replacing the
I/Os for the corresponding sensors, actuators, and operator com-
mands. The proposed formal and modular PN representation of
the control logic is still under study and expecting to provide a
way for automatically generating verified control logic code of
IEC 1131-3 programming languages. The proposed scheme is
shown in Fig. 6.
Kato et al. [19] proposed a modular machine PLC control
modeling approach using PN. They used the PN PLC method
in [32], and [43]–[44] for both “building” and “validation” steps.
An automated CNC lathe door interlocking control program is
Fig. 5. Implementation scheme of PN-based controllers by Feldmann et al.
[7].
Fig. 6. Implementation scheme of PN-based controllers by Park et al. [27]
(dotted boxes to be implemented).
used as an example, for which its PLC control model is con-
structed, and validated via PNs.
Chirn and McFarlane [4] proposed a method to design an
LD for a PLC based on a PN modeling approach. A general
method for mapping PNs to LDs is implemented using a variety
of PLCs. To complete LD for an industrial application, the ap-
proach also considers the combinational logic of action outputs
to the external environment.
Minas and Frey [24] developed a new approach for the
visual programming of PLCs using signal-interpreted PNs
(SIPNs) that are able to model the causality and the con-
currency of control algorithms. An SIPN is described by a
9-tuple with the first four
to represent an ordinary PN and the last five as extensions,
logical input signals (I), logical output signals (O), Boolean
function as the firing condition associated to every transition
(o), a mapping associated every place, and the output function
combines the output u of all marked places (U). By using
four established firing process rules, an SIPN can be obtained
by associated each transition with a firing condition given
as a Boolean function of the input signals. The places of an
SIPN are associated with actions specifying output signals.
A prototypical tool for the editing, visualizing, animating,
analyzing, and translating SIPNs has been implemented using
the Diagram Editor Generator (DiaGen), an environment for
PENG AND ZHOU: LD AND PN-BASED DISCRETE-EVENT CONTROL DESIGN METHODS
Fig. 7. Proposed technique steps of the design/implementation of a logic
controller by Tzafestas et al. [33].
rapidly developing diagram editors from a formal specification
of the diagram language based on hypergraph grammars and
hypergraph transformation [12]. The DiaGen tool provides
a tailored graphic editor for SIPNs and translates SIPNs to
equivalent IL programs implementing the SIPN behavior on
a logic controller. The tool moreover provides interfaces for
further analyzing and accessing SIPNs.
Tzafestas et al. [33] proposed a method for using PN models
in order to design and implement a sequence controller for a
small scale robotic cell which consists of a robotic manipulator,
a variety of sensors and electro-pneumatic actuators. The exper-
imentation was applied on an educational system using Allen
Bradley PLC as a controller for programming. This educational
system incorporates a variety of sensors and actuators, most of
them found in real-life industrial systems and a quite simple
logic of operation. The PLC was programmed using the previ-
ously generated PN model, as the proposed technique described.
The method leads directly to generate the associated LD for the
PLC and it has proved to be effective through the application
to sequence control of a small-scale industrial system. It also
has reduced the period for developing, debugging and reengi-
neering of the LD, compared to the traditional method that di-
rectly prepares an LD for the PLC implementation. The whole
implementing process of the proposed technique is depicted in
Fig. 7.
All the approaches discussed above intend to apply some
user-friendly high-level languages or the hardware configura-
tion to generate a PN-based controller to be checked, analyzed
and maintained reliably. Furthermore, they convert PN into the
required IEC 1131-3 standard languages for PLC. Obviously,
if the conversion methodologies between PN and IEC 1131-3
programming languages can be verified and automated, the sig-
nificance would be tremendous in the automation industry.
529
V. CONCLUSIONS AND FUTURE RESEARCH
As automated manufacturing systems become more complex,
there is a growing need for an effective design tool to produce
their DECS. PNs represent the most effective method for de-
sign and implementation of DECS. The conversion of PN into
real-time applications has been greatly simplified in several ap-
proaches. These techniques have been developed for various
types of PN.
Topics for future research include improving logic control
software design and implementation through integrated diag-
nostics, better human-machine interfaces, validation, and auto-
mated code generation following IEC 1131-3. IEC 1131-3 de-
fines a program as a logical assembly of all programming ele-
ments and constructs for the intended signal processing required
for the control of a machine or process by a programmable con-
troller system. Its languages are as follows.
1) LD.
2) IL: A low level “assemble like” language based on similar
languages found in many of PLCs.
3) FBD: A graphical language for depicting signal and
data flows through function blocks-reusable software
elements.
4) ST: A PASCAL language that encourages structured pro-
gramming with PASCAL-like language structure.
5) SFC: A graphical language used for defining time and
event-driven control sequences.
6) FBs: A reusable software integrated circuits concept as
ICs. Using high-level languages such as visual BASIC
and C++, it can develop specific function block object
libraries, e.g., PID algorithms, fuzzy logic controllers,
PN-based controllers, and alarm handlers.
The standard allows users to select any languages and mix
their use in the program. They can choose the best language
for each part of an application. Since the current specification
formalisms and design criteria are still far from being standard-
ized and able to meet characteristics like easy maintenance to
support the new processes, it still requires great effort on the
PN-based controller development for PLC programming. To fill
the gap between academic research and industrial applications,
researchers need to combine different languages directly from
the standard into PN-based controllers for implementation.
To establish a consistent standard of IEC languages, re-
searchers as well as the industry need to build reusable function
block software as PN-based controllers for the PLC in the
future. Furthermore, as distributed control becomes more
popular in implementations, design and analysis techniques for
distributed logic control systems are needed. A system with
thousands of I/O points will end up with complex implemen-
tation. Effective compositional methods for distributed control
systems through the modular design using PN techniques are
of increasing importance. The most important research issues
are related to the interfaces or interlocks between different
PN-based control modules. Specification, modeling, and
analysis of these interlocks remain an open area of research.
530 IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART C: APPLICATIONS AND REVIEWS, VOL. 34, NO. 4, NOVEMBER 2004
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PENG AND ZHOU: LD AND PN-BASED DISCRETE-EVENT CONTROL DESIGN METHODS
[46] M. C. Zhou, F. DiCesare, and D. Rudolph, “Design and implementation
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Shih Sen Peng (M’01–SM’01) received the B.S. de-
gree in mechanical engineering from CCIT, Taiwan,
R.O.C., in 1960, the M.S. degree from the University
of Oklahoma, Norman, in 1979, and the Ph.D. degree
from Lamar University, Beaumont, TX, in 1996, both
in industrial engineering.
He is currently an Associate Professor in the
Department of Mechanical Engineering, Chinese
Military Academy, Taiwan, R.O.C. His research
interests include automated manufacturing sys-
tems, computer-integrated manufacturing, and
discrete-event control system modeling.
Dr. Peng is a senior member of the Institute of Industrial Engineers (IIE).
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Meng Chu Zhou (S’88–M’90–SM’93–F’03)
received the B.S. degree from Nanjing University
of Science and Technology, Nanjing, China, in
1983, the M.S. degree from Beijing Institute of
Technology, Beijing, China, in 1986, and the Ph.D.
degree in computer and systems engineering from
Rensselaer Polytechnic Institute, Troy, NY, in 1990.
He joined New Jersey Institute of Technology
(NJIT), Newark, in 1990, and is currently a Professor
of electrical and computer engineering and the
Director of Discrete-Event Systems Laboratory. His
research interests are in computer-integrated systems, Petri nets, semiconductor
manufacturing, multilifecycle engineering, ad hoc networks, and system
security. He has authored over 200 publications, including four books, over 50
journal papers, and ten book chapters. He co-authored (with F. DiCesare) Petri
Net Synthesis for Discrete Event Control of Manufacturing Systems (Boston,
MA: Kluwer, 1993), edited Petri Nets in Flexible and Agile Automation
(Boston, MA: Kluwer, 1993), and co-authored (with K. Venkatesh) Modeling,
Simulation, and Control of Flexible Manufacturing Systems: A Petri Net
Approach (Singapore: World Scientific, 1998). He has been invited to lecture in
Australia, Canada, China, France, Germany, Hong Kong, Italy, Japan, Korea,
Mexico, Taiwan, and the U.S. He has led or participated in 26 research and
education projects funded by the National Science Foundation (NSF), the
Department of Defense, the Engineering Foundation, the New Jersey Science
and Technology Commission, and by industry.
Dr. Zhou served as Associate Editor of IEEE TRANSACTIONS ON ROBOTICS
AND AUTOMATION from 1997 to 2000 and is currently an Associate Editor of the
IEEE TRANSACTIONS ON SYSTEMS, MAN AND CYBERNETICS, PART C (SMC)
and the IEEE TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING.
He has been an editor of the International Journal of Intelligent Control and
Systems since 1996. He has organized and Chaired over 60 technical sessions
and served on program committees for many conferences. He was Program
Chair in 1998 and Co-Chair in 2001 for the IEEE International Conference on
SMC and the 1997 IEEE International Conference on Emerging Technologies
and Factory Automation. He was Guest Editor for the IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS and the IEEE TRANSACTIONS ON SEMICONDUCTOR
MANUFACTURING. He was General Co-Chair of 2003 IEEE International Con-
ference on SMC, held in Washington, DC, in 2003 and a Founding General
Co-Chair of the 2004 IEEE International Conference on Networking, Sensing,
and Control. He was the recipient of the NSF’s Research Initiation Award, the
CIM University-LEAD Award from the Society of Manufacturing Engineers,
the Perlis Research Award from NJIT, the Humboldt Research Award for U.S.
Senior Scientists, the Leadership Award and Academic Achievement Award
from the Chinese Association for Science and Technology-USA, and the Asian
American Achievement Award from the Asian American Heritage Council of
New Jersey. He was Founding Chair (founding) of the Discrete Event Systems
Technical Committee of the IEEE SMC Society, and Co-Chair (founding) of the
Semiconductor Factory Automation Technical Committee of the IEEE Robotics
and Automation Society. He is a Life Member of the Chinese Association for
Science and Technology-USA and served as its President in 1999.