Chapter 5: Conclusion and Future Scope

This chapter presents the conclusions based on the research work done for designing

SHA-less 16-bit 125 MS/s digitally calibrated Pipelined ADC. It also covers the

recommendations and the research work that may be done in near future.

Conclusion

Following are the major components considered in this thesis to achieve the goal of high

performer, high resolution Pipelined ADC:

1. Multi-bit front-end stage has been used here to achieve desired ADC’s resolution.

The number of bits resolved in each stage were explored based on research work and

optimization methods. The choice of resolution of each stage affects the overall noise

and area performance. For this design implementation of 16 bits, the first and second

stages are chosen as 3.5 bit and stages from 3 to 7 are chosen as 2.5 bit each, and the

last stage is chosen as 3-bit Flash ADC.

2. A two stage amplifier with a gain-boosted structure is realized in the first stage by

using high swing and high gain op-amp.

3. Two separate voltage references are used here to avoid interference between stages

and to save power. A large transient current is needed to charge and discharge

capacitors if only one voltage reference would be used for all stages.

4. The reduction of SHA (Sample and Hold) circuit saves the power and little area but

only at the expense of higher circuit complexity of 1st stage. Removal of SHA allows

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 use of smaller input capacitor to improve circuit’s drivability but can create a

sampling mismatch problem for high input frequency applications. This problem is

more serious for multi-bit stages because of limited built-in redundancy. The

sampling clock skew problem is considered here and proposed a solution also.

5. Due to capacitor mismatching and other non-idealities of Op-amp, the ADC transfer

function may be affected by discontinuities revealed by DNL errors.

6. A digital Calibration technique, a combination of Signal Dependent Dithering (SDD)

and Butterfly Shuffler (BS) technique is proposed here to correct small signal

linearity errors and the capacitor mismatch errors.

7. In fixed magnitude PN dithering methods, the dither magnitude and measurement time

are big constraints. The proposed calibration technique gave a solution of all these

problems. A large dither could be injected without lowering the signal range and it

can maintain the signal-to-dither ratio low to reduce the calibration time.

8. An extra circuit for calibration algorithm is required in between sub-ADC and sub-

DAC which could introduce an extra delay and can reduce the settling time for

residue amplifier. So, an accurate clock is needed to control the switch to short

differential outputs of Op-amp in hold phase.

9. A novel architecture of redundant signed digit (RSD) is also proposed here to reduce

time and to improve circuit performance.

10. Finally, designed digitally calibrated ADC’s with the aim to minimize the power

dissipation, control the noise interference from the input source and to improve the

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 static and dynamic performance with increased resolution of Pipelined Analog to

Digital Converter at high sampling frequency.

Future Scope

In general, we can say that some improvements are still awaited to be a collection of

features that includes sophisticated system implanting with minimal complexity of

analog sub circuits and a précised system with cheap digital processing resources. In

future, the same calibration technique with some modifications can be used to for other

applications also like Consumer electronics i.e. digital cameras, DVD, display

electronics, enhanced-definition TV, test and measurement instrumentation. In future,

this thesis work can be extended for final chip fabrication. The same calibration

technique can be used for a time-interleaved architecture and multichannel pipeline ADC

for high resolution and speed applications. The work can be extended to multiplexing

which is beneficial to conserve area when the performance of a pipeline ADC is

inadequate due to error sources independent to the conversion rate. The architecture

proposed here can be used to implement A/D interface for similar multichannel systems.

The work could be extended to save more power at higher input sampling frequency.

Moreover, the proposed calibration technique can be employed in other types of

multistage ADCs of different resolution and with different bit size stages. The proposed

calibration technique can be useful in cascaded sigma–delta modulators also.

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