ASSIGNMENT 5

ON TOPICS:
1. ELECTROMIGRATION EFFECTS IN VLSI
2. IR DROP ISSUES
3. PARASITIC EXTRACTION
4. PREFERENCE OF METAL LAYERS

Submitted By:
Arnon Pukhrambam
Trainee (KNK Technologies)
ELECTROMIGRATION EFFECT IN VLSI

Electromigration:
When a high current density passes through a metal interconnect, the
momentum of current-carrying electrons may get transferred to the metal ions
during the collision between them. Due to the momentum transfer, the metal
ions may get drifted in the direction of motion of electrons. Such drift of metal
ions from its original position is called the electromigration effect.
Current density J is defined as the current following per unit cross-section area.
J = I/A
Where ‘I’ is the current and ‘A’ is the cross-section of the area of interconnect.
As the technology node shrinks, Cross-sectional area of the metal interconnects
also shrinks and the current density increases in great extent in the lower node.

Electromigration Phenomenon:

Fig. 1. Electromigration Phenomenon

Fig.1. Shows the phenomenon of electromigration effect. A potential difference
is applied across a metal interconnect which setups an electric field from anode
side to cathode side as shown. This electric field causes to move the electron in
the opposite direction of the electric field. This momentum of electron cause
flow of current in the electron. These moving electrons have momentum and
when it collides with the metal ions the metal ions feel two forces in the
opposite direction as shown in the figure. One force and due to electric field and
other is due to strike of electrons wind. If the current density is high the force
due to electron wind is greater than the force due to the electric field.
Depending on the current density, the subjected metal ion started drifting in the
opposite direction of the electric field. If the current density is high, the
interconnect may get affected of EM instantly or sometimes the effect may
come after months/years of operation depending on current density. So, the
reliability of IC will depend upon this EM effect.
Mean Time To Failure (MTTF) is an indication of the life span of an
integrated circuit. MTTF is calculated using Black's equation as bellow.
Ea
A ( )
MTTF = N e KT
J

Where, A = Cross-Sectional area

J = Current density
N = Scaling factor (normally set to 2)
Ea = Electromigration Activation energy
K = Boltzmann's constant
T = Temperature in Kelvin

Effects of EM:
Damage to the metallization lines is caused by divergences in atomic flux.
When the amounts of matter leaving and entering a given volume are unequal,
the associated accumulation or loss of material results in damage. This results in
two types of inequalities:

1. Depletion of atoms (Voids): If the incoming ion flux is lesser than the
outgoing ion flux, It will create a void in interconnect. A void can lead a
discontinuity in the interconnect and result an open circuit.

2. Deposition of atoms (Hillocks): If incoming ion flux is greater than the

outgoing ion flux, It will cause the accumulation of ions and create a
hillock in the interconnect. A hillock can increase the width of a metal
interconnect and touch the neighbouring metal interconnect which may
result in a short circuit.
Factors affecting electromigration:
Wire Material: It is known that pure copper used for Cu-metallization is more
electromigration-robust than aluminium. Copper wires can withstand
approximately five times more current density than aluminium wires while
assuming similar reliability requirements. Since copper wire has more
electromigration activation energy, it can withstand more current density than
an aluminium wire.
Wire Temperature: In Black’s equation, which is used to compute the mean
time to failure of metal lines, the temperature of the conductor appears in the
exponent, i.e. it strongly affects the MTTF of the interconnect. The temperature
of the interconnect is mainly a result of the chip environment temperature, self-
heating effect of the current flow, heat of the neighbouring interconnects or
transistors, and thermal conductivity of the surrounding materials.
Wire Size: As Black’s equation shows, current density J is used to compute
MTTF and J is given by I/A. So, if area of a wire increases, the current density
decreases and hence increase resistance to electromigration. So, wire size
constitutes the main parameter affecting the MTTF of a wire.

Prevention techniques for EM:

With the scaling of the technology node, the interconnect used is also changed.
Initially, pure Aluminium was used as interconnect then industry started using
the Al-Cu alloy and later shifted to Copper interconnects. Copper interconnects
can withstand approximately 5 times more current as compared to Aluminium
interconnect while maintaining similar reliability requirements.
During the physical design, the following techniques could be used to prevent
the EM issue.
 Increase the metal width to reduce the current density
 Reduce the frequency
 Lower the supply voltage
 Keep the wire length sort
 Reduce the buffer size in clock lines
To prevent the EM issue, EM Checks is performed during the physical signoff
stage with respect to the EM rules provided by the foundry.
Electromigration-aware design:
 Bamboo structure and metal slotting
A wider wire results in smaller current density and, hence, less likelihood of
electromigration. Also, the metal grain size has influence; the smaller grains,
the more grain boundaries and the higher likelihood of electromigration
effects. However, if you reduce wire width to below the average grain size of
the wire material, grain boundaries become "crosswise", more or less
perpendicular to the length of the wire. The resulting structure resembles the
joints in a stalk of bamboo. With such a structure, the resistance to
electromigration increases, despite an increase in current density. This
apparent contradiction is caused by the perpendicular position of the grain
boundaries; the boundary diffusion factor is excluded, and material transport
is correspondingly reduced.
However, the maximum wire width possible for a bamboo structure is
usually too narrow for signal lines of large-magnitude currents in analog
circuits or for power supply lines. In these circumstances, slotted wires are
often used, whereby rectangular holes are carved in the wires. Here, the
widths of the individual metal structures in between the slots lie within the
area of a bamboo structure, while the resulting total width of all the metal
structures meets power requirements.
 Blech length
There is a lower limit for the length of the interconnect that will allow higher
current carrying capability. It is known as "Blech length". Any wire that has
a length below this limit will have a stretched limit for Electromigration.
Here, a mechanical stress build-up causes an atom back flow process which
reduces or even compensates the effective material flow towards the anode.
The Blech length must be considered when designing test structures to
evaluate electromigration.
 Via arrangements and corner bends
Particular attention must be paid to vias and contact holes. The current
carrying capacity of a via is much less than a metallic wire of same
length. Hence multiple vias are often used, whereby the geometry of the
via array is very significant: multiple vias must be organized such that the
resulting current is distributed as evenly as possible through all the vias.
 Attention must also be paid to bends in interconnects. In particular, 90-
degree corner bends must be avoided, since the current density in such
bends is significantly higher than that in oblique angles.
 Electromigration in solder joints
The typical current density at which electromigration occurs in Cu or Al
interconnects is 106 to 107 A/cm2. For solder joints (SnPb or SnAgCu
lead-free) used in IC chips, however, electromigration occurs at much
lower current densities, e.g. 104 A/cm2. It causes a net atom transport
along the direction of electron flow. The atoms accumulate at the anode,
while voids are generated at the cathode and back stress is induced during
electromigration. The typical failure of a solder joint due to
electromigration will occur at the cathode side. Due to the current
crowding effect, voids form first at the corners of the solder joint. Then
the voids extend and join to cause a failure.
 Electromigration due to IR drop noise of the on-chip power grid
network/interconnect
The Electromigration degradation of the on-chip power grid
network/interconnect depends on the IR drop noise of the power grid
interconnect. The Electromigration-aware lifetime of the power grid
interconnects as well as the chip decreases if the chip suffers from a high
value of the IR drop noise.
IR DROP ISSUES IN VLSI

IR Drop:
The power supply (VDD and VSS) in a chip is uniformly distributed through
the metal rails and stripes which is called Power Delivery Network (PDN) or
power grid. Each metal layers used in PDN has finite resistivity. When current
flow through the power delivery network, a part of the applied voltage will be
dropped in PDN as per the Ohm's law. The amount of voltage drop will be V =
I.R, which is called the IR drop.

Fig. 1. IR Drop in metal net

Fig. 1. Shows the IR drop in the Power net. Any metal net can be assumed as a
combination of small R and C.
If the resistivity of metal wire is high or the amount of current following
through the power net is high, A significant amount of voltage may be dropped
in the power delivery network which will cause a lesser amount of voltage
available to the standard cells than the actual amount of voltage applied.
If V1 voltage is applied at the power port and current I is following in a
particular net which has total resistance R, then the voltage available (V2) to the
other end for the standard cell will be V2 = V1 - I.R. Standard cells or macros
sometimes do not get the minimum operating voltage which is required to
operate them due to IR drop in power delivery network even the application of
sufficient voltage in the power port. Voltage drop in the power delivery network
before reaching the standard cells is called IR drop.
This drop may cause the poor performance of the chip due to the increase of
delay of standard cells and may cause the functional failure of the chip due to
setup/hold timing violation. To avoid this issue, IR analysis must be done and
consider its effect in timing analysis in the design cycle.

Types of IR drop:
1. Static IR drop:
Static IR drop is the voltage drop in the power delivery network (PDN) when
there are no inputs switching means the circuit is in the static stage. It is
dependent on the RC of the power grid connecting the power supply to the
respective standard cells. It is always desirable to create the power grid in
higher metal layers. Higher metal layers mean more wide wires and hence
lower resistance. Lower resistance would mean IR drop will be lower and
hence lesser impact on setup-timing.
Capacitance of metal wires would be the combination of gnd and coupling
capacitance. If for some reason, the capacitance is too large, it is indeed the
reason for IR drop. It could be due to
 Long wire length resulting in higher wire capacitance.
 High fan-out of the net resulting in higher load-cap
 High routing congestion in a particular area resulting in high coupling
capacitance with neighbouring nets.
A simple equation representing static IR drop would be
V static =I avg∗R wire
drop

2. Dynamic IR drop:
It is the voltage drop in the PDN when the inputs are continuously switching
means the circuit is in a functional state. It depends on the switching rate of
instances. Dynamic IR drop is more than the static IR drop. Dynamic IR
drop is sometimes referred to by the term Voltage ‘Droop’.
It is contingent upon the current drawn by the standard cells and that brings
in a time-dependent variation of current. It is represented by the equation
 di
V dynamic =L( )
drop
dt

Reasons for IR drop:

 Poor design of power delivery network (lesser metal width and more
separation in the power stripes)
 Inadequate via in power delivery network
 Inadequate number of de-cap cells availability
 High cell density and high switching in a particular region
 High impedance of the power delivery network
 Rush current
 Insufficient number of voltage sources
 High RC value of the metal layer used to create the power delivery
network

Effects of IR drop:
Delay of standard cells depends on the available power supply to the cell and if
the power supply decreases the delay of cell increases. The increase in delay of
a cell could affect the performance of the design. It is also possible that if the
available voltage to a standard cells gets below a particular level, then the cell
may stop function completely and could result in functional failure of the
design. Or sometimes the IR drop is within the limit and only delay of cells get
increased which affects the setup and hold timing of design and sometimes it
causes failure of setup and hold timing.

Fig. 2. Voltage Droop and Ground Bounce

A sudden drop in the VDD line is also possible if the demand of current gets
increased suddenly due to a large number of switching activities in a particular
area of design. Such type of drop in VDD level is called voltage droop. Or it
may cause sudden raise the level of ground voltage, which is called ground
bounce. These are collectively called power noise. Fig.2. shows the power noise
due to IR drop.
In short IR drop could result in
 Change in the delay of cells
 Could violate the setup and hold timing
 Introduction of power noise in power supply nets

IR analysis and fixes:

Every EDA companies have their own IR analysis tool which performs the IR
analysis and based on the analysis the techniques for the IR fixes are applied.
Two most popular tools for IR analysis used in industry are:
 RedHawk of Ansys
 Voltus of Cadence Design System
Based on the analysis there are various techniques to fix the IR drop are applied.
Some of the fixes which generally performed are:
1. Padding clock cells:
Clock structure is the primary culprit for the power consumption of the chip
due to high clock switching. However, with padding clock cells technique,
clock buffers/inverters and clock gate cells are given extra area as keepout
regions to avoid placement of standard cells and any excessive cell density
around them. This helps to prevent the dynamic IR drop.
2. Cell Padding/Decap insertion around cells within a dynamic IR
hotspot region:
They are placed around cells within a dynamic IR hotspot region. Some cells
with high driving strength create dynamic IR drop issue. We can give cells
padding to these cells or insert decap cells around IR hotspot region to
prevent IR drop issues.
3. RC corner:
The RC corner where the physical design engineers should analyze for IR
drop would be the case when the RC product is worse. And that would
indeed be the (RC) max corner, also referred to as the RC worst corner.
 4. PVT conditions:
PVT conditions would typically impact the standard cells. For IR drop
analysis, we would be concerned about the case when we expect the highest
switching activity for standard cells. High temperature might seem an
anomaly but higher temperature would mean higher resistance as well and
hence higher IR drop.

PARASITIC EXTRACTION:
Parasitic extraction (PEX) is calculation of the parasitic effects in both the
designed devices and the required wiring interconnects of an electronic circuit:
parasitic capacitances, parasitic resistances and parasitic inductances,
commonly called parasitic devices.
The major purpose of parasitic extraction is to create an accurate analog model
of the circuit, so that detailed simulations can emulate actual digital and analog
circuit responses. Digital circuit responses are often used to populate databases
for signal delay and loading calculation such as:
 Timing analysis
 Power analysis
 Circuit simulation
 Signal integrity analysis
Analog circuits are often run in detailed test benches to indicate if the extra
extracted parasitics will still allow the designed circuit to function.

Different categories of Parasitics:

Front-end of the Line (FEOL): Parasitics associated with the semiconductor
devices.
Middle-end of the Line (MEOL): Parasitics associated with the contacts on
semiconductor devices.
Back-end of the Line (BEOL): Parasitics associated with the interconnect
layers.
Effects of Parasitic devices on circuit design:
 Extra power consumption:
1. Violates the power specification
2. Extra power dissipation can increase total temperature which can affect
other components.
 Effect of Delay of circuit:
1. Causes timing violations.
2. Can impact IR drop.
 Increase signal noise:
1. Introduces unwanted delay which can impact timing numbers.
2. Speed up the signal which impacts the timing numbers.
3. Can change the logic (0 to 1) or (1 to 0) causing logic failure.
 Increase IR drop on power supply lines that affects delay

Parasitic extraction methods:

Fields Solver Based:
In this method, the PEX engine solves Maxwell’s equations to calculate the
parasitic R, C, L or K. This method is referred to as 3D extraction. It is a higher
accuracy method than the rule-based method, but also takes more processing
power and is not used for full-chip extraction. Within the field solver category,
you could have finite element or random walk algorithm being employed –
tradeoff being processing time vs. accuracy, finite element algorithm being
more accurate.
Rule Based:
In this method, the PEX engine uses a look up table to calculate the parasitic R
or C. This method is referred to as 2D or 2.5D extraction. It can support full-
chip extraction.

Where we can use Parasitic Extraction:

 During Static Timing analysis: It helps us to find out R/C (Delay) of the
network and delay helps us to do timing analysis
 During Noise analysis, crosstalk analysis and signal integrity check:
 1. For noise and cross talk analysis, it is important to know the
relationship between 2 wires, how these wires transfer information
between themselves.
2. Coupling capacitance is the mode of interaction between them.
Parasitic extraction helps us to find coupling capacitance between 2
wires which help us further to do SI (Noise/cross talk) analysis.
 During IR analysis:
Parasitic Extraction outputs resistance of the network which helps us in
IR analysis.
 Substrate noise analysis:
1. In analog design, a lot of noise through the substrate passes to other
part of the design.
2. We know that any channel through which any information can transfer
have finite resistance. Parasitic extraction also helps us to find
resistance of the substrate, which help further into substrate noise
analysis.
Below 180nm, these parameters (Interconnect Delay, Coupling capacitance)
plays a majority of role. So, it is very important to extract this information
correctly. More accurate result means more runtime. So, there are several ways
a user can extract only required information. Few of them are:
1. Extract Resistance only
2. Extract Capacitance only
3. Extract both.

Capacitance are of 2 types:

1) Decoupled capacitance:
Net to net capacitance are lumped to ground. In place of 1 cap value
between Net A and Net B, we will get 2 cap values. Capacitive coupling
effects are not there in this mode. So, we can’t use netlist during the SI
analysis. It is comparatively less accurate but it can speed up the
simulation.
 Fig. Decoupled Capacitance
2) Coupled Capacitance:
Net to net parasitic capacitance are extracted and be part of output netlist
separately. It replicates the practical scenario and help in SI analysis. This
mode though take more time for simulation. Runtime of Extraction can
also be decreased by compromising with the accuracy of the results.

Fig. Coupled Capacitance

Preference of metal layers:
Due to the fact that higher metal layers have more width and higher
conductivity than lower metal layers, higher metal layer possess lesser sheet
resistance leading to lesser IR drop. So, this context we want to use higher
metal layers as much as possible.
But also, the cost of each layer of metal are different due to the materials used.
As the metal layers gets higher, the cost gets higher too. So, we want to choose
metal layer which can carry the max current retaining minimum cost of
fabrication.