1 IEEE CICC 2022
A 1.8GΩ-Input-Impedance 0.15μV-Input-Referred-Ripple
2022 IEEE Custom Integrated Circuits Conference (CICC) | 978-1-6654-0756-4/22/$31.00 ©2022 IEEE | DOI: 10.1109/CICC53496.2022.9772860
near-zero power (Fig.1). However, 1mm
Chopper Amplifier with Local Positive Feedback and
SAR-Assisted Ripple Reduction
Tianxiang Qu, Qinjing Pan,Xiaoyang Zeng,Zhiliang Hong, Jiawei Xu
Fudan University, Shanghai, China
Many sensors exhibit output impedances greater than a few MΩ, and
the subsequent instrumentation amplifier (IA) must be carefully
designed to meet the requirements of high input impedance (R in), low
noise and low offset. Chopping is a power-efficient technique to
achieve low offset and low 1/f noise without noise aliasing [1-4], but
at the expense of a lower Rin (10-100MΩ [1][4][5]). Positive feedback
loop (PFL) can boost Rin of a capacitively-coupled chopper IA (CCIA)
by providing a large portion of input source current [4]. However, in
practice, the PFL is not suitable for a generic chopper amplifier to
achieve a high Rin above 100MΩ, because the actual impedance
boosting factor highly depends on the absolute accuracy of the
feedback elements and the overall gain of the IA. For instance, to
compensate input parasitic capacitance of 100fF by the PFL, an IA
with a voltage gain of 100 requires a very small feedback capacitor
of 1fF. Meanwhile, this feedback capacitor must be reconfigured with
different IA gains. For the same reason, the PFL is not applicable to
a chopper operational amplifier (OPA) either due to its ill-defined
open-loop gain. Apart from the limited Rin, chopper amplifiers also
suffer from output ripple, i.e. the up-modulated offset. Prior art ripple
reduction loop (RRL) can realize a sub-μV residual input referred
ripple [1][3], but this often involves an active loop integrator with large
DC gain and time constant, resulting in power and area overhead.
This work proposes a high-input-impedance chopper IA based on the
current feedback instrumentation amplifier (CFIA) topology (Fig.1).
The IA can be easily reconfigured to a chopper-stabilized OPA. By
utilizing the current balance input stage, gain-independent negative
capacitance (NC) and SAR-assisted passive RRL, both the chopper
CFIA and the chopper OPA benefit from very high Rin and low ripple
while retaining the merits of chopping. As for the CFIA, the R in and
input referred ripple are 1.8GΩ (min) and 0.15μV (max), respectively,
at least 18x and 1.3x improvements on the state of the art [1][3][5].
Fig.1 shows the block diagram of the CFIA, including a high-gain low-
frequency path (LFP) and a low-gain high-frequency path (HFP). The
LFP employs chopping to mitigate its offset and 1/f noise while the
same error sources of the HFP are suppressed by the high gain of
the LFP when referring to the IA’s input. The HFP is also responsible
for compensating the chopping-induced notch of the LFP, hence the
overall IA exhibits a smooth transfer function [1]. The LFP utilizes
chopper-stabilized input and feedback transconductors (Gm11=Gm12).
Gm,sum and Gm3 are intermediate stages providing extra gain. Gm4 is
a class-AB output stage for improved driving capability.
In contrast to conventional CFIA’s transconductors implemented with
differential pairs [1][3], this work employs a current balance stage
with gain-independent negative capacitor to realize high intrinsic Rin
(Fig.2). The gate-source capacitances (Cgs) of M1 and M2 are self-
bootstrapped, so the residual input capacitance is mainly composed
of Cgd and Ctraces (Fig.2). To compensate these capacitances, the
input stage utilizes a local positive feedback loop (LPFL) consisting
of a feedback resistors RT, a voltage buffer and a 6-bit adjustable
capacitor array CF. By selecting RT =0.4*RS (Fig.2) and connecting
them in series at the sources of M1 and M2, the input signal is only
amplified by a low gain of 1.4 and then buffed to drive CF. The LPFL
provides a part of the input source current in the same manner as a
negative capacitor. Furthermore, the low gain implementation of the
LPFL significantly alleviates the practical constraint to realize a sub-
fF level CF. For instance, to compensate input capacitance of 100fF,
the optimum CF of 250fF can be easily implemented with a 6-bit array,
and so is less sensitive to parasitic capacitances. As derived in the
bottom of Fig.2, the equivalent negative capacitance CNEG formed by
the LPFL can fully cancel the total input parasitic capacitance C P,
thereby boosting the limited Rin due to chopping. Note that the NC-
based impedance boosting is independent of the CFIA’s voltage gain,
this makes the NC technique also valid for the chopper OPA (bottom
right of Fig.1).
To reduce the ripple at chopping frequency, a passive high pass filter
(HPF) is inserted to block any offset of Gm11, Gm12 and Gm,sum with
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these transconductors also induce
a large open-loop gain, which can CLOCK
result in Gm,sum saturation even with Gen.
SAR
an input offset voltage of tens of μV.
0.9mm
CM1 VDD
The ill-defined output offset not only LFP Cc Output
reduces the IA’s output headroom
Stage
VSS
CM2
HFP BG
but also deteriorates the gain of the
LFP and its capability to suppress
the offset of the HFP. To prevent
Gm,sum from saturation, an SAR- Die micrograph.
assisted current-steer DAC (IDAC)
is proposed to calibrate the total offset of Gm11, Gm12 and Gm,sum. The
7-bit IDAC has polarity-outputs with an LSB of 15nA and it can cover
the maximum input referred offset (Vos) of approximately 10mV. The
auxiliary OTAs (A1-A4) are used to regulate the drain voltages of the
current mirrors and improve the current replication accuracy between
Gm11(Gm12) and Gm,sum. Hence, the open-loop gain variation under
different input common-mode voltages is reduced, improving both
reliability of the offset calibration and the CFIA’s linearity.
The offset calibration is performed by shorting the inputs of Gm11 and
Gm12 to the common-mode voltage. As shown in Fig.3, the differential
outputs of Gm,sum are compared in every calibration clock cycle to
determine the SAR codes. After seven cycles, both outputs move
close to the mid-supply voltage and the amplifier is then switched to
normal operation mode automatically. The passive HPF, consisting
of a pair of 25pF capacitors and switched-capacitor 10MΩ resistors,
has a cut-off frequency of 600Hz. It allows the up-modulated signals
pass while filtering the offset and 1/f noise of Gm11, Gm12 and Gm,sum.
The unity-gain bandwidth of the CFIA is set to 9MHz by choosing
Gm21 (Gm22)=170μS. In the OPA mode, the parallel connected input
transconductance leads to a 2x bandwidth of 18MHz.
The chip was fabricated in a 0.18μm CMOS process and occupies
an area of a 0.9mm2 including a bandgap and a clock generator. The
CFIA draws 1.07mA current at 5V supply voltage. As shown in Fig.3,
with the SAR-assisted calibration enabled, the Vos from 10 samples
is reduced from the maximum 600μV to 4μV (max). Fig.4 shows the
measured Rin of the CFIA, and the minimum Rin at 5Hz is 1.8GΩ (10
samples). The measured output ripple at a chopping frequency of
25kHz is also given in Fig.4 (bottom left) and the harmonics at 50kHz
are due to charge injection and clock feedthrough. The histogram of
10 samples indicates the maximum input referred ripple of 0.15μV.
Fig.5 shows the noise performance, The chopper CFIA achieves an
input referred noise density of 38nV/√Hz. The bottom left of Fig.5
shows that the minimum CMRR at 5Hz is 129dB (10 samples). When
configured at the gain of 10, the CFIA exhibits a -3dB bandwidth of
850kHz (bottom right of Fig.5), in line with the simulated unity-gain
bandwidth of 9MHz.
The performance metrics of the chopper CFIA and the chopper OPA,
in comparison with state-of-the-art are summarized in Fig.6. Thanks
to the current balance input stage and the gain-independent NC, both
the CFIA and the OPA achieve the highest R in of 1.8GΩ (min) and
0.9GΩ (min), respectively, 90x and 18x improvements on [1] and [5].
The SAR-assisted passive RRL facilitates a very low input referred
ripple of 0.15μV (max) and an input offset of 4μV (max), respectively.
Meanwhile, the proposed CFIA and OPA also exhibit great power
efficiency, in terms of the highest ratio of GBW/I SUPPLY.
References:
[1] Q. Fan et al.,“A 21 nV/√Hz Chopper-Stabilized Multi-Path Current-
Feedback Instrumentation Amplifier With 2μV Offset,” IEEE JSSC,
Dec. 2011.
[2] Y. Kusuda et al., "A 5.6 nV/√Hz Chopper Operational Amplifier
Achieving a 0.5μV Maximum Offset Over Rail-to-Rail Input Range
with Adaptive Clock Boosting Technique," IEEE JSSC, Sept. 2016.
[3] F. Butti et al., "A Chopper Instrumentation Amplifier with Input
Resistance Boosting by Means of Synchronous Dynamic Element
Matching," TCAS-I, April. 2017.
[4] Q. Fan et al., "A 1.8 μW 60nV/√Hz Capacitively-Coupled Chopper
Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor
Nodes," IEEE JSSC, July 2011.
[5] Analog Devices Inc., “AD8237 datasheet”
[6] Analog Devices Inc., “ADA4051 datasheet”
 IEEE CICC 2022 2

From Gm11 From Gm12

Low Frequency Path RSC
VINP CP VOS1 On-Chip RC
SAR Calibration
+ - Oscillator
VOUT1P VOUT1N VOUT2P VOUT2N
VINN Gm11 SAR Logic
VOUT1N VOUT1P
- + VREG1P VREG1N VREG2P VREG2N
7 7
CP FCHOP FSC_RES FCAL VREG1P VBCASP VREG1N
A1 A2 A3 A4
VCM 25KHz 1MHz 1KHz
CF X1.4 10pF
7bits RSC x1.4 x1.4
Neg-Capacitance VOS3 IDAC CC CM1
x1 2K 2K x1
CF X1.4 RT RT
Gm,sum HPF Gm3 Cgs RS
5K 5K
RS Cgs VOUTP CMFB VOUTN
VFBP CP VOS2 CF CF
+ - CC=25pF CC M1
AC Ground
M2
RSC 10pF CM1
VFBN Gm12 RSC=10M
Cgd
- + VCM Ctraces FCHOP Cgd
Ctraces
CP

High Frequency Path

+ -
VOS4 Gm21 1.6K Ctrl<6:0> 1LSB=15nA 1.6K
- + VSS VINP VINN
VOUT
VOS5
Gm4 Gm11 (Gm12) Gm,sum
+ - External Load
Gm22 Capacitor CL Residual capacitance: CRES = Cp+CNEG = Cp-(GPF-1)CF
- +
(150pF, MAX) CP CNEG CF
Conventional PFL: GPF=GIA>100 CF<0.01CP
GPF
• Hard to implement sub-fF-level capacitance
VINP VINP
VIN VOUT VOUT Rin CF • CF sensitive to parasitic capacitance
VINN VINN CP CNEG
VIN • Limited impedance boosting factor
VFBP VFBP
VCM Proposed Neg-C: GPF=1.4 (Independent of GIA) CF=2.5CP
VFBN R1 VFBN R1 CNEG = (1-GPF)CF • CF is easy to implement
CP = Cgd +Ctraces • CP=68fF(Cgs)+10fF(Ctraces) (Post simulation)
R2
IA Configuration R2 OPA Configuration • 6bit-CDAC, 1LSB = 8fF
VCM VCM
Fig. 2. Circuits diagram of Gm11, Gm12, Gm,sum, and the principle of gain-
Fig. 1. Block diagram of the proposed chopper IA and chopper OPA independent local positive feedback loop (LPFL)
5
CAL_EN

5G
Rin w/o Neg-C 4 10 samples

Number of Samples
Rin w/ Neg-C
0 1G
0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 500M 3
5

Rin[]
100M
CLK

2
50M
0 1
0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 10M
5 VOUTP 5M
Output of Gm,sum [V]

0
VOUTN 10 100 1k 10k 1.6G 2.0G 2.4G 2.8G 3.2G 3.6G
4 Frequency[Hz] Rin @5Hz []
3
2
1
12.0μ
Output Amplitude [V]

0 1 2 3 4 5 6 7 Gain=100 10 samples
3

Number of Samples
0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 10.0μ Output Ripple
Time[S] @25KHz
8.0μ Glitch
2
10 samples 3 10 samples @50KHz
4 6.0μ
Number of Samples
Number of Samples

3 4.0μ 1
2
2.0μ
2
0.0 0
1 10k 15k 20k 25k 30k 35k 40k 45k50k 0.09 0.10 0.11 0.11 0.12 0.13 0.14 0.16
1 Frequency [Hz] Input Ripple [V]

0 0
-600-400-200 0 200 400 600 -3 -2 -1 0 1 2 3 4 5
Vos(V) Without Calibration Vos(V) With Calibration Fig. 4. Measured input impedance Rin vs. frequency (top left) and histogram
Fig. 3. Illustration of SAR-assisted offset calibration and measured input- of Rin at 5Hz (top right), measured output ripple and glitch (bottom left) and
referred offset wo/w calibration histogram of input-referred ripple (bottom right).
Input Noise Density [V/sqrtHz]

100n IA W/ Neg-C High Frequency

IA W/O Neg-C
OPA W/ Neg-C
Path Instrumentation Amplifiers Operational Amplifiers
210uA 20% Others
50n [1] [3] [5] [4] [6] [1] [2]
40n
OPA W/O Neg-C 20uA This This
Output 2% JSSC TCAS AD JSSC ADA4 JSSC JSSC
30n work 12 17 8237 11
work 051 12 16
Stage
20n 350uA Technology (nm) 180 700 320 NA 65 180 NA 700 350
33%
Supply voltage 5V 5V 3.3V 5V 1V 5V 1.8V 5V 5V
10n
Architecture CFIA CFIA CFIA CFIA CCIA OPA OPA OPA OPA
5n
4n Low Frequency Path
Rin Boosting Yes No Yes No Yes Yes No No No
3n 480uA 45%
100 200 400 1k 2k 4k 10k 20k 40k Rin @5Hz (Ω) 1.8G 20M 25M 100M 30M 0.9G 8M 10M NA
Frequency[Hz]
Input bias current (pA) 65 220 300 650 NA 130 50 110 400
Input referred ripple (μV) 0.15 0.39 0.2 100* 3 0.15 35* 0.39 15
140 21
130
GBW (MHz) 8 0.9 0.04 0.2 NA 16 0.115 1.8 4
18 Supply current (mA) 1.07** 0.14 0.17 0.13 0.0018 1.07** 0.018 0.143 1.4
120
110 15 -3dB BW=850KHz GBW / ISUPPLY 7.5 6.3 0.24 1.5 NA 15 6.4 12.6 2.86
CMRR[dB]

Gain [dB]

3 10 samples Gain = 20dB Input offset voltage

Number of Samples

100 12 4 2 2 75 1 2 17 1 0.5
(max) (μV)
90 2
9 CMRR (dB) 129 137 120 106 110 129 105 137 142
80 1 Input voltage noise
6 39 21 18 68 60 20 95 10.5 5.6
70 (nV/√Hz)
0
60 128 130 132 134 136 138 140 142 3 IOUT,MAX (mA) 19*** NA NA 4 NA 19*** NA NA NA
CMRR @5Hz [dB]

50 0 Slew Rate (V/μs) 9.7 NA NA 0.05 NA 9.7 0.03 NA 0.5

10 100 1k 10k 1k 10k 100k 1M
Frequency[Hz]
Frequency [Hz] * According to the datasheet, this value is measured when configured as a unity-gain buffer.
** Where 350μA is consumed by the Class-AB output stage for high driving capability of 19mA.
Fig. 5. Measured input-referred noise density (top left), current consumption ***At IOUT=19mA, the maximum output voltage can reach VSUPPLY-100mV with a THD of 0.047%.
breakdown (top right), CMRR vs. frequency (bottom left), measured transfer
curve of the CFIA (bottom right) Fig. 6. Performance summary and comparison with the state of the art

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