Ministry of Higher Education Course: - BSC 215

Higher Technological Institute Second level

Computer Science Department

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 Introduction.

 Half adders and full adders.

 Decoder and encoder.

 Multiplexer and de-multiplexer.

 Memory, PLA and PAL.

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 Chapter 4
Combinational logic circuits

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 The digital circuit is divided into combinational circuits and
sequential circuits. The combinational circuit is a connected
arrangement of logic gates (OR, NOR, NOT, AND, NAND)
with a set of inputs and outputs. At any given time, the
binary output is a function of the binary combination of the
inputs present at that time. This figure shows the block
diagram of the combinational logic circuit.

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 The sequential circuit is a combinational circuit with
additional memory elements. Each output at any instant of
time (present state) depend not only at the inputs present at
the same time but also the outputs at the last time instant
(last state).

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 Half adders :
▪ It is a combinational circuit that forms arithmetic
sum of two bits .
a) Block diagram b) Truth Table:
input output
y x s co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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 c) Outputs expressions

d) Logic diagram

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 Full adders :
▪ It is a combinational circuit that forms arithmetic
sum of three bits. input output
a) Block diagram z y x s co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
b) Truth Table:
1 0 1 0 1
1 1 0 0 1
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 c) Outputs expressions

d) Logic diagram

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 4-bit binary adder

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 4-bit binary adder/subtractor

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 Binary incrementor

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 Binary incrementor/ decrementor

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 Decoder
▪ It is a combinational circuit that used to generate
2 n (or less) minterms of n-input variables.
a) Block diagram b) Truth table
enable input output
E X Y D3 D2 D1 D0
1 0 0 0 0 0 1
For example
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0
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c) Outputs expressions d) Circuit diagram

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 Inverted decoder
▪ It is a combinational circuit that used to generate
2 n (or less) minterms of n-input variables.
a) Block diagram b) Truth table
enable input output
E Y X D3 D2 D1 D0
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1
1 X X 1 1 1 1
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c) Outputs expressions d) Circuit diagram

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 Implement 4x16 decoders using 2x4 decoder

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 Implement full adder using 3x8 decoder

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 Implement the following functions using
a) 3 x 8 decoder
b) 3 x 8 inverted decoder

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 BCD to 7-segment decoder
▪ The 7-segemnt display consists of 7 Light emitting diodes (LEDs). The
LED is a diode that emits photons when it is connected in forward
bias. Figure shows The LED is connected with a DC bias + 5 V

▪ We have two types of 7-segment display

1) Open collector 7-segmenet display

1) Common cathode 7-segmenet display

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 Encoder
▪ It is a digital circuit that produces a reverse
operation from that of a decoder. It has a
maximum of 2n inputs and n output lines. The
output lines generate the binary code of the 2n
input variables.
a) Block diagram
b) Output expression

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 c) Truth table
Input output
D3 D2 D1 D0 x Y
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

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 Multiplexer
▪ It is a combinational circuit that selects binary
information from one of many input lines and
directs it to a single output.
a) Block diagram b) Truth table
input output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
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c) Output expression

d) Circuit diagram

▪ Note: found enable MUX

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 Demultiplexer
▪ It is used to propagate one input among 2n
outputs lines according to n-control (address)
lines .
a) Block diagram

b) Truth table

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 c) Output expression

d) Circuit diagram

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 • Memory

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Example:
Using 8 x 2 ROM show how to get
b) 16 x 2 ROM
c) 8 x 4 ROM
d) 16 x 4 ROM

• Composition of ROM
The 2n x m memory is composed
of
a) n x 2n decoder
b) m x 2n programmable fuses
c) m OR gates
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