A Multi-Mode Transmitter Supporting BT/BLE and 802.
11b/g/n/ax
for IoT Applications
Chao Lu Jun Liu
ASR Microelectronics Inc. ASR Microelectronics (Shanghai) Ltd.
San Jose, CA Shanghai, China
chao.lu@ieee.org
Shr-Lung (Calvin) Chen Pengfei Yue
2021 IEEE 7th World Forum on Internet of Things (WF-IoT) | 978-1-6654-4431-6/21/$31.00 ©2021 IEEE | DOI: 10.1109/WF-IoT51360.2021.9595148
ASR Microelectronics Inc. ASR Microelectronics (Shanghai) Ltd.
Irvine, CA Shanghai, China
Chin-Ming Chien
ASR Microelectronics Inc.
Irvine, CA
Abstract—A multi-mode 2.4GHz transmitter is presented to
support Bluetooth classic （BT), Bluetooth low energy (BLE)
and 802.11b/g/n/ax. The proposal features two separately
optimized signal paths with a single RF port. Through a multi-
level buck converter, PA power supply is designed adaptive to
operation modes ensuring high power efficiency. In WiFi mode,
21.5dBm mask compliant output power can be measured with
22%/20% PA/Tx efficiency. With 40MHz 1024-QAM (MCS11)
signals, the transmitter achieves -35dB EVM at 16dBm output
power without digital pre-distortion (DPD). At BT basic rate,
the output power is 15.8dBm and PA/Tx efficiency can be up to
27%/25%, respectively. The output power reaches 13dBm with
EDR3 signals. The transmitter can deliver 10.5dBm power in
BLE mode with 28%/21% PA/Tx efficiency. Implemented in
22nm CMOS technology, the transmitter (including phase
modulator PLL) occupies 0.7mm2 silicon area.
Keywords— transmitter, 802.11ax, BT, BLE, power efficiency,
power amplifiers (PA), CMOS.
I. INTRODUCTION
The prevailing of IoT applications presents many new
challenges in transceiver design. Some different from smart
phones, these devices need to operate over a wide scope with
home infrastructure hubs but also more on peer-to-peer
interconnections. On-state duration may vastly vary
depending on application scenarios and battery life is usually
more critical for IoT including wearable devices. Irregular
data transmission ranges from bandwidth hungry data
streaming to collective sensor interface for fitness and
healthcare applications, and this demands a set of wireless
connectivity protocols for best user experience. For high
integration and thereby smaller form factor, a combo chip is
preferred over standalone devices, and the design challenges
lie in lieu of ensuring power efficiency with a cost-effective
solution.
Separating 2.4GHz WiFi pin from Bluetooth costs extra
board of materials (BoM) in a typical wireless connectivity
combo chip [1]. An on-chip SP3T switch is employed in [2]
to combine WiFi output with BT transmitter. In [3], the WiFi
signal path is designed to be reconfigurable as Bluetooth.
Since the output power target is quite different, it is difficult
to optimize efficiency for both standards and demands a
tunable impedance matching network (IMN) and external
balun in [3]. Even though output power and performance
requirement of a single-stream device for most IoT
applications can be relaxed relative to that for APs [4],
802.11ax prefers a large transmission power control (TPC)
range and specifies 1024-QAM modulation scheme. 1024-
978-1-6654-4431-6/21/$31.00 ©2021 IEEE 25
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Jian Bao
ASR Microelectronics (Shanghai) Ltd.
Shanghai, China
Jianqiu Chen
ASR Microelectronics (Shanghai) Ltd.
Shanghai, China
QAM demands superior transmission signal quality with -
35dB or better error vector magnitude (EVM). Various factors
can contribute to EVM degradation including phase noise,
thermal noise, IQ mismatch and nonlinearity. This extends
WiFi performance gap further away from BT/BLE and leads
to higher difficulty in preserving power efficiency across
different protocols, especially BLE, where power saving is
more critical.
In this work, we present a highly efficient transmitter
solution supporting 802.11ax, BT and BLE. The measured
output power in WiFi mode is as high as 21.5dBm with 22%
PA drain efficiency and 20% overall transmission (Tx) power
efficiency, in par with [2] and [5] where digital power
amplifier (DPA) with DPD is deployed. With 40MHz
MCS11 signals, the output power can reach 16dBm and EVM
is better than -35dB. When operating as BT transmitter, the
achievable output power is 15.8dbm for basic rate signals. PA
efficiency is up to 27% and overall Tx efficiency reaches 25%.
The transmitter can deliver 13dBm output power with 3Mbps
EDR (EDR3) signals. In BLE mode, 28% PA power
efficiency and 21% Tx efficiency can be achieved with
10.5dBm output power. Attributed to the proposed
architecture, the power efficiency from this fully integrated
combo chip is comparable to or better than state-of-the-art
standalone BT/BLE solutions [7,8].
II. MULTI-MODE TX ARCHITECTURE
The block diagram of the proposed multi-mode transmitter
is shown in Fig. 1. The proposal features two separate signal
paths: one optimized for linearity (L-Path) and the other more
for efficiency (S-Path). The fully integrated transmitter can be
configured as WiFi, BT or BLE transmission with one single
RF port. A multi-level buck converter (ML DC-DC) is
employed as PA power supply to further enhance power
saving across operation modes.
The highly reconfigurable transmit signal L-path is shared
between WiFi and BT (EDR mode) for high linearity. A linear
class-AB PA (L-PA) is deployed as a compromise between
linearity and efficiency, and a power mixer is designed to
directly drive L-PA. The elimination of PA driver (PAD) stage
leads to a smaller chip area and lower current consumption. A
separate path (S-path) is employed for BT basic rate and BLE
where signals are with constant envelope. A switching mode
PA is deployed for better efficiency. The PA core (S-PA) is
driven with rail-to-rail (GFSK modulated) signals, derived
from a phase-locked loop (PLL) with built-in phase
modulation. Different from [3], the same impedance matching
 network (IMN) is shared between two signal paths, and there
is no need for complicated LC network and external balun.
VBAT
Mode Ctrl Ref- Vref ML
(WiFi, BT or BLE) Gen DC-DC
VPA
I
DAC LPF
L-PA
Q
DAC LPF
L-Path
PM Phase
DIV2 S-PA
Modulator
S-Path
Fig. 1 Multi-mode transmitter architecture
To ensure power efficiency across distinct output power
requirements, PA power supply is set differently according to
system operation modes. This is achieved through ML DC-
DC. The output of buck converter, VPA, scales to its reference
voltage (Vref). The stair-case reference is derived from a
refence generator block based on mode control signals. For the
given target power levels, the buck converter is configured to
output 2.2V, 1.0V and 0.5V when operating in WiFi, BT and
BLE, respectively.
Although the design of buck converters is outside the
scope of this paper, a few facts are worth mentioning. The
buck converter in this case generates stair-case output voltages
as PA power supply, the allowed transition time from one
level to another is more than 100us. Thereby, there is no need
for fast switching or high bandwidth DC-DC converters as
that in envelope tracking, and very little design overhead is
needed.
III. BUILDING BLOCK DESIGN
In 802.11ax, Orthogonal frequency division multiple
access (OFDMA) distributes grouped subcarriers (resource
unit) among stations. It allows multiple-user access by
subdividing a channel to make more efficient use of the
spectrum. TPC is mandatory to ensure proper signal power
levels arriving at AP (from different stations). 30dB or more
gain control range is preferred. A wide gain control range sets
stringent noise requirement on building blocks and makes it
difficult for noise and linearity compromise. In this work, due
to the lack of PAD, we distribute gain control in DAC, low
pass filter (LPF) and PA stages.
As for the linearity, due to large output power range, it
may take long time in DPD training and expensive hardware
for implementing pre-distortion. In this design, we aim for
highly linear PA and transmitter without relying on DPD.
A. PA Design with Unified Matching Network
The complete PA diagram with a single matching network
is illustrated in Fig. 2. A linear class-AB PA (L-PA) is
designed for satisfying 1024QAM EVM requirement. To
mitigate memory effect, its bias circuitry was designed to
present low impedance over a frequency range well beyond
envelope bandwidth, and the bias voltage of common-source
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transistors is applied through the transformer center-tap of
preceding stage. PA is sliced into unit cells for gain control
(GC), effectively reducing current consumption at lower
output power levels. A tunable capacitor array is placed at the
input to maintain proper frequency response and help achieve
good linearity.
IMN
VPA
IMN
L-PA S-PA
GC VB
GC
LIP SIP
LIN
SIN
Fig. 2. Circuit diagram of PAs with unified matching network.
On the contrary, inverse class-D (class-D-1) topology [8]
is adopted in S-PA, where high efficiency is of primary goal.
The input pair is driven with rail-to-rail phase modulated
signals. The gain control is achieved through gating signals to
individual switching pairs. Regulating cascode gate bias
voltage VB can be used to achieve additional gain control
range. Please note that large voltage swing presents at output
when L-PA is on and it may induce device damage of S-PA
transistors. To mitigate overstress issue, VB is set to a high
voltage even in off-state.
The output power can be estimated using equations (1)
and (2) for L-PA and S-PA, respectively. RL represents
effective load impedance looking into matching network
(IMN). Vknee is the kneed voltage and 𝜃 is conduction angle
of L-PA, while Ron is the on resistance of S-PA.
( )
𝑃 = (𝜃 − sin(𝜃)) (1)
/
𝑃 =𝑅 (2)
( )
Based on experimental reliability measurement, VPA is
deemed safe to be 2.2V or below for the designed structure.
For the targeted power levels, RL is determined being about
10ohm. VPA is set to be 2.2V, 1.0V and 0.5V for operating as
WiFi, BT and BLE, respectively. The matching network is
implemented through an on-chip 2:1 transformer.
B. L-Path Baseband and Up-conversion Mixer
High resolution current steering DAC is employed for two
aspects: to yield good SNR needed for 1024-QAM and to
provide high dynamic range for assisting gain control. DAC
sampling clock runs up to 240MHz, and a high sampling rate
help alleviate image suppression requirement in the following
stages.
A current mode reconstruction filter is chosen to avoid
current to voltage conversion. Current mirror structure with
built-in low pass filtering is designed. This leads to a compact
area and improves signal-to-noise ratio (SNR) [9]. A twin-T
26
 notch is added between reference (input) and output stage for photograph. The transmitter occupies 0.7mm2 silicon area
additional DAC image suppression. The gain can be (0.2mm2 for PLL based phase modulator PLL and Tx core is
accurately controlled through transistor size ratio between about 0.5mm2).
MO and MR. The simplified schematic of reconstruction filter
and power mixer is shown in Fig. 3. A super-Gm consisting
of MC and OTA (A) at input stage provides a low load
impedance to the preceding DAC such that superior linearity C B2
can be achieved.
B1
VDD12
LIP VB,PA LIN
A
VDD12

LOP LON
MC

IIN VB,M
A
IOUT
Fig. 4. Die photograph (A: L-Path, B1/2: S-Path, C: IMN)

MR MO
Fig. 3. Current-mode baseband filter and power mixer (complementary
path of baseband filter and Q-channel are not shown).
A transformer is used to supply the power mixer and
interface with PA. The inductive tuning load allows large
voltage swing and can therefore eliminate the need of PAD.
A variable capacitor bank is placed at the mixed output for
proper frequency tuning and harmonic suppression. PA bias
voltage VB,PA is fed though the center-tap of secondary coil
of the transformer for alleviating memory effect. Mixer gate
bias VB,M is designed such that the quiescent operation point
of transistors MO tracks that of MR. The current mode
A. OFDM Measurement
When tested with 20MHz 802.11n MCS0 signals, the
transmitter can deliver up to 21.5dBm output power with 2dB
margin to spectrum emission mask (SEM). PA draws 285mA
current from 2.2V power supply and yields 22.5% drain
efficiency. The entire transmitter consumes 689mW and the
overall transmission power efficiency can be better than 20%.
Fig. 5 demonstrates EVM and PA efficiency versus output
power, and the measurement is with 40MHz 1024-QAM
802.11ax (MCS11) signals. Attributed to the slicing
mechanism implemented in PA, its current consumption
significantly decreases at lower output power levels.
-20.0 25.0

architecture ensures output current, IOUT, a faithful up-

conversion of input signal IIN. 20.0
-25.0
C. Phase Modulator

Efficiency (%)
15.0
Phase modulator in S-Path converts GFSK data into rail-
EVM (dB)

-30.0
to-rail driving signals to S-PA. The modulation function is
embedded inside a phase locked loop (PLL) based fractional- 10.0
N frequency synthesizer. Properly scaled digital bits are
applied to delta-sigma modulator, which generates control -35.0
5.0
word for modulus frequency dividers. There is also a
secondary path to enable direct frequency modulation onto
VCO through varactor voltage tuning. The delay between two -40.0 0.0
-15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0
modulation paths is aligned by design, and an option is
Pout (dBm)
reserved to superimpose two paths with calibrated gain
compensation. In this design, the same frequency synthesizer Fig. 5. EVM and PA efficiency versus output power
also provides LO signals in receiving mode.
The transmitter achieves over 30dB output power range
VCO runs at two times of operation frequency mainly to with an EVM floor at -39dB. The output power reaches
facilitate in-phase and quadrature LO generation. Close 16dBm with -35dB EVM without the need of DPD. The
attention has been paid in both design and layout floorplan to output spectrum with MCS11 signals is shown in Fig. 6.
mitigate VCO pulling and remodulation due from PA second
harmonic. Key building blocks including VCO are powered B. BT/BLE Measurement
through on-chip LDOs. The nonlinear path of transmitter is configured and
measured for BT basic rate and BLE mode. 15.8dBm output
IV. IMPLEMENTATION AND MEASUREMENT RESULTS power can be achieved for BT basic rate. PA yields 27%
The design was implemented with 22nm digital CMOS efficiency. The entire transmitter (including PLL and phase
technology with FC-CSP package. Shown in Fig. 4 is the die

27
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 modulator) consumes 151mW and represents 25% overall
power efficient.
Fig. 6. Output spectrum with 1024-QAM OFDM (MCS11) signals
With a lower power supply voltage, the design works as a
BLE transmitter. The measured BLE1M output power can be
up to 10.5dBm. PA drain efficiency is 28%. The total power
consumption is 53mW and the overall power efficiency is
better than 21%. The output spectrum is shown in Fig. 7. For
both cases, the transmitter yields more than 7dB margin to
spectral emission mask requirements.
(a) (b)
Fig. 7. Output spectrum of (a) BT basic rate at 15.8dBm and (b) BLE1M at
10.5dBm power
The modulation characteristics of BLE is measured with
11110000 and 10101010 patterns. Peak frequency drift over
450us is less than 4KHz and maximum frequency drift rate is
less than 2KHz (per 50us), as shown in Fig. 8.
Frequency drift <4KHz
Fig. 8. Measured BLE frequency deviation over time
Fig. 9. Spectrum and Constellation at 13dBm output power with EDR3
With EDR3 signals, the transmitter can deliver 13dBm
output power with 5.6% DEVM. The measured spectrum and
constellation are shown in Fig. 9. ACP3 presents >8dB
margin to emission mask.
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V. CONCLUSION
This paper presents a multi-mode high efficiency
transmitter architecture for IoT applications. The architecture
features a linear signal path and another path incorporating
switching-mode PA and phase modulator. Two paths share the
same matching network for a compact area. With a multi-level
buck converter, 802.11ax can be well supported and high
efficiency are achieved in BT/BLE modes.
Implemented in 22nm CMOS technology, the entire
transmitter occupies a silicon area of 0.7mm2. The measured
mask compliant output power is 21.5dBm in WiFi mode. With
40MHz 1024-QAM signals, the output power reaches 16dBm
with -35dB EVM. The output power is 15.8dBm and 10.5dBm
for BT base rate and BLE, respectively. For 3Mbps EDR
signal, the output power can be up to 13dBm. The achievable
transmission efficiency is better than 20% in all three
operation modes.
ACKNOWLEDGMENT
The authors would like to thank Danjun Shi, Chongguang
Wang, Hanbo Zhang, Yong Zhou, Yanjia Shi, Qiang Jiang,
Yuankai Tang, JC Zhang and Xuan Zhou for their support and
contributions to this work.
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