This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Non-isolated High Step-up DC-DC Converter with Passive
Switched-Inductor-Capacitor Network
Xiaoquan Zhu, Member, IEEE, Kaiwen Ye, Kang Liu and Bo Zhang, Senior Member, IEEE
Abstract—In this paper, a non-isolated dc-dc high
step-up converter with passive switched-inductor-
capacitor network is proposed, which is applicable for the
required high gain voltage low power applications, such as
battery-powered LED lighting systems and high-intensity
mobile discharge lamps. The proposed circuit can produce
higher gain voltage with small duty cycle, which decreases
the voltage stress and conduction power loss on the active
switches. In contrast to other non-isolated dc converters,
by using the same or analogous number of passive/active
components in circuit topology, the proposed topology
has lower voltage stresses across capacitors and diodes,
lower inductor current stresses. Therefore, the efficiency
and reliability of the circuit topology can be ameliorated.
The theoretical principle, parameter design guideline,
small-signal dynamic analysis, power loss analysis and
performance comparison with other dc-dc non-isolated
converters have been implemented. Finally, a 200 W
experimental setup is built and tested with an input dc
voltage of 36V–60V and an output voltage of 200V to
validate the aforementioned merits of the proposed circuit.
Index Terms—Boost factor, non-isolated dc-dc converter,
high gain voltage, switched-inductor-capacitor network.
I. INTRODUCTION
S INCE the renewable power resources, such as wind, solar
and fuel cells, are green and environmental protection, they
provide very effective solution for the traditional
fossil-energy crisis. Therefore, the exploitation and utilization
of renewable power sources have gained much more attention.
However, due to the renewable energy has low and variable
output voltage, it cannot meet the desired dc-link voltage level
demands for grid-connected inverters [1]. Hence, the two-stage
High
PV Step-up DC-AC
or DC-DC Inverter
Fuel Cell Converter
Stack
Fig. 1 Typical schematic diagram of the two-stage power-conversion
system.
Manuscript received June 13, 2021; revised September 7, 2021;
accepted November 1, 2021. This work was supported in part by the
Fundamental Research Funds for Central Universities under Grant
1003-90YAH19087 and 56XAA21057; in part by the Natural Science
Foundation of Jiangsu Province under Grant BK20181293; in part by the
Industrial Technology Development Program under Grant
JCKY2019605. (Corresponding author: Xiaoquan Zhu).
X. Zhu, K. Ye and K. Liu are with the College of Automation
Engineering, Nanjing University of Aeronautics and Astronautics,
Nanjing 210016, China (e-mail: ijruexq@nuaa.edu.cn,
ykw777@nuaa.edu.cn and liukang@nuaa.edu.cn).
B. Zhang is with the School of Electric Power, South China University
of Technology, Guangzhou 510640, China (e-mail: epbzhang@
scut.edu.cn).
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power conversion system is widely adopted, as presented in Fig.
1. A high-boost dc–dc converter is utilized in the first stage to
alternate a low input dc voltage into a constant high level dc
voltage. For this stage, a number of high boost dc converters
have been put forward and inspected to beget a high-gain
voltage in both isolated and non-isolated way [2].
For the isolated topologies, a high-frequency transformer
will be utilized in the converter to realize electrical isolation
between output and the dc input, which forms dc–ac–dc power
conversion system. By changing the turn ratio of the
transformer appropriately, this kind of converter can produce a
very high gain voltage [3]-[5]. But at the cost of high volume,
high weight and the issue of magnetic core saturation also
requires special attention. For the non-isolated topologies, by
using coupled inductors to substitute the conventional inductors,
coupled-inductor-based dc-dc converters have been raised
[6]-[8], and the output gain voltage can be flexible designed by
selecting appropriate turn ratio; however, the energy stored in
leakage inductance and power switches’ voltage spikes is
another mishap, which should be resolved by supernumerary
snubber circuits [9]-[10].
In order to realize high-gain voltage with high power density
and high efficiency, various noncoupled-inductor based dc-dc
converters have been brought forward and researched in recent
two decades. Cascaded [11], interleaved [12] and voltage-lift
[13] techniques have been utilized in noncoupled-inductor
based converters, which can obtain a high gain voltage, but
with a complex circuit configuration. In [14]-[15], voltage
multiplier cells are utilized to the converter circuit to subjoin its
output gain voltage. On the basis of the switched-capacitor (SC)
and switched-inductor (SL) technique, various high boost SL
converters [16]-[18], SC converters [19]-[21] and hybrid
SL/SC converters [22]-[23] have been developed and
investigated. In addition, by applying traditional SL/SC cells
Utility into active switch network, some multicell SL/SC-active
Grid
or
network converters are brought forward in [24], which can
Load output a high-gain voltage with low voltage stress across diodes
and power switches.
However, for the above mentioned various non-isolated
dc-dc boost converters, the operating duty ratio range is varied
over a wide range of 0 to 1. Then, a larger duty ratio will be
adopted to beget a required higher gain voltage, which will
result in a high conduction loss on diodes and switches. In this
case, impedance source network-based converters, such as
Z-source network [25] and switched-boost network [26], as an
emerging technology in energy conversion, are invented to
overcome these disadvantages, which reduces the duty cycle
operating range to (0, 0.5). By employing Z-source network to
substitute the traditional inductor, a series of improved
embedded Z-source dc-dc converters with discontinuous input
current are put forward in [27]. For the purpose of ameliorating
the input current profile, some dc-dc high boost quasi-ZS
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

converters were brought forward [28]-[30]. Analogously, by

Ts Ts
employing voltage multiplier, SL, or SC cells into qZS-network S1
DTs
S1
DTs
and the SB-network, some new high step-up quasi-ZS (1-D)Ts
D xT s

converters [31]-[33] and SB-dc converters [34]-[35] were 0 0

advanced, respectively. In addition, by assembling several iL1=iL2 iL1=iL2 VC1/L1 (VC1‒VC3)/L1

conventional qZS networks in different ways, a family of 0

VC1/L1 (VC1-VC3)/L1
0
hybrid dc-dc ZS-boost converters [36]-[37] were raised, which iL3=iL4 iL3=iL4 VC3/L3 (Vdc+VC3-2VC1)/L3

have further promoted boost capability of the output voltage, VC3/L3 (Vdc+VC3-2VC1)/L3
0 0
but at the cost of high voltage stress across switches and diodes.
uL3=uL4 uL3=uL4
A non-isolated dc-dc high step-up converter with passive uL1=uL2
VC3
uL1=uL2
VC3

switched-inductor-capacitor network, as presented in Fig. 2, is 0

(1-D)VC3
0
(1-D)VC3
DVC3 DVC3
brough forward in this paper. The main advantageous merits of Vdc+VC3-2VC1
Vdc+VC3-2VC1
the proposed circuit are as follows: low voltage stress across t0 t1 t2 t0 t1 t2 t3
diodes and MOSFETs; low inductor current stresses; high (a) (b)
boost gain voltage with small duty cycle, which can reduce the
Fig. 3 Key operating waveforms of the proposed circuit during: (a) CCM
power switches’ conduction loss. The theoretical principle mode and (b) DCM mode.
analysis in continuous conduction mode (CCM) and mode, capacitor C1 charges the inductor L1 through diode D1
discontinuous conduction mode (DCM) of the proposed circuit and switch S1, inductor L2 is charged by capacitor C2 via diode
is presented in Section II. Small-signal dynamic analysis and D2 and S1, capacitor C3 charges the inductor L3 through switch
parameter design guideline are presented in Section III and IV,
S1; inductor L4 is charged by capacitor C4 via the switch S1, and
respectively. Then, the performance comparison, power loss
capacitor C1 and C2 are connected in series to discharge the
analysis and efficiency contradistinction with other dc-dc high
energy to Co and RL through Do and S1. Based on Fig. 4(a), by
boost converters are revealed in Section V. Simulation and
experimental results are given in Section VI to validate the utilizing KCL and KVL, the following formulas can be derived
practicality of the converter. Conclusion part is drawn in u L1 on = VC1 u L 2− on = VC 2
 −
Section VII.  u L 3− on = VC 3 u L 4− on = VC 4 (1)

 Vo = V +
C1 VC 2

iC1− on = − iL1 − iDo iC 3− on = − iL 3


 (2)
iC 2− on = − iL 2 − iDo iC 4− on = −iL 4

2) State 2 [t1-t2, Fig. 4(b)]: Switch S1 is OFF, diodes Din, D3
and D4 are forward conducted and diodes D1, D2 and Do are
reverse-blocked. The time duration of this operating state is
(1-D)Ts. The input source Vdc, inductors L2 and L4 charges the
capacitor C1 through the diodes Din and D4. Capacitor C2 is
Fig. 2 Configuration of the proposed dc-dc converter.

II. STEADY-STATE ANALYSIS OF THE PROPOSED CIRCUIT

In this section, detailed steady-state analysis of the proposed
circuit is presented in both CCM and DCM operating modes.
The typical operating waveforms in CCM and DCM are
revealed in Fig 3 (a) and (b), respectively. To simplify the
circuit analysis, we assume that all active and passive devices in
the converter are ideal and lossless, and the inductance,
capacitance and load resistance are all linear and (a)
time-invariant.
A. CCM Steady-state Analysis
The proposed circuit has two operating modes in continuous
conduction mode (CCM). Corresponding equivalent circuit
diagrams during CCM are revealed in Fig. 4(a) and Fig. 4(b),
respectively.
1) State 1 [t0-t1, Fig. 4(a)]: Switch S1 is turned on, diodes Din,
D3 and D4 are reverse-blocked due to the reverse parallel
connection with the capacitor. Diodes D1, D2 and Do are
forward conducted. The time duration of this operating mode is
DTs, where D is the duty ratio, Ts is the switching period. In this (b)

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

D1 Do
employed. The corresponding operating key waveforms in
L1 DCM are presented in Fig. 3(b). There are three working states,
Din D3 as revealed in Fig. 4(a), Fig. 4(b) and Fig. 4(c), respectively.
C1 C3 L3 1) State 1 [t0-t1, Fig. 4(a)]: This working state is same as the
state 1 in CCM. From (1), the inductor current peak-to-peak
Vdc S1 Co RL Vo value is,
C2 C4 L4
 VC1  DTs V  DTs
iL1 = iL 2 = C 2
D4  L 1 L2
 (8)
i = VC 3  DTs VC 3  DTs
L2 D2
iL 4 =
 L 3 L3 L3
(c)
Fig. 4 Operating states of the proposed circuit in CCM and DCM: (a) 2) State 2 [t1-t2, Fig. 4(b)]: Equivalent schematic diagram is
State 1, (b) State 2, (c) State 3 in DCM.
revealed in Fig. 4(b). Inductor voltages can be computed by
charged by Vdc, inductors L1 and L3 through diodes Din and D3. employing (3). State 2 in DCM ends when the inductor currents
Vdc is connected in series with inductors L1, L2 and L4 to charge (iL1, iL2, iL3, iL4) are reduced to zero.
capacitor C3 through the diodes Din, D3 and D4. Capacitor C4 is 3) State 3 [t2-t3, Fig. 4(c)]: Switch S1 is still OFF, and
charged by Vdc, inductors L1, L2 and L3 through the diodes Din, inductor currents are reduced to zero. The inductor voltages in
D3 and D4. At the same time, the capacitor Co is connected in this state are zero. And the stored energy in capacitor Co is
parallel with RL, and discharge the energy to load. Analogously, discharged to load RL.
by utilizing KVL and KCL in Fig. 4(b), one can obtain On the basis of the presumption of lossless power circuit, the
u L1− off + u L 3− off = Vdc − VC 2 average inductor currents are derived as
 DxVo2 Vo Dx  I L1
u L 2− off + u L 4− off = Vdc − VC1 I L1 = I L 2 = − I L3 = I L 4 = (9)
 (3) ( D + Dx ) RVdc ( D + Dx ) R D + Dx
u L1− off + u L 2− off + u L 3− off = Vdc − VC 4 For the purpose of making sure that the proposed circuit
u
 L1− off + u L 2− off + u L 4− off = Vdc − VC 3 operates in CCM mode, the inductor currents should be
retained continuously during the whole switching period, thus:
 iC1− off =iin − iL1− off iC 3− off =iL1− off − iL 3− off
 (4)  I L1 − iL1 2  0 I L 2 − iL 2 2  0
iC 2− off =iin − iL 2− off iC 4− off =iL 2− off − iL 4− off  (10)
 I L 3 − iL 3 2  0 I L 4 − iL 4 2  0
On the basis of the volt-second balance characteristic of Substituting (5), (7), (8) into (10), the boundary condition
inductor, the inductor voltage average value during one between CCM and DCM can be derived as,
D (1 − 4 D + 2 D 2 )
switching cycle is zero. From (1) and (3), the steady-state  2L 2 L2
output voltage Vo and capacitor voltage can be derived as  1 = 
 (1 − D )2 V  RLTs RLTs 2
VC1 = VC 2 =  (11)
D (1 − 4 D + 2 D 2 )
dc
 1 − 4D + 2D2  2 L3 2 L4
  = 
 1− D 2 (1 − D )
2
VC 3 = VC 4 = Vdc (5)  RLTs RLTs
 1 − 4 D + 2D2

Due to the impedance network in the proposed circuit is
V = 2 (1 − D ) V
2
symmetric. Therefore, formula (11) can be simplified as:

( )
o dc
 1 − 4D + 2D2 D 1 − 4D + 2D2
2L
 (12)
2 (1 − D )
2
From (5), the CCM output gain voltage of the proposed RLTs
circuit can be obtained as,
Denoting K=2L/RLTs, Kcrit=D(1-4D+2D2)/2/(1-D)2, Fig. 5
2 (1 − D )
2
V reveals the picture of Kcrit as a function of D at the CCM/DCM
G= o = (6)
Vdc 1 − 4 D + 2 D 2 boundary condition. When K>Kcrit, the proposed circuit
On the basis of the capacitor’s ampere-second balance operates in CCM; when K<Kcrit, it operates in DCM.
principle, the average capacitor current in one switching period During DCM working state, the inductor current average
is equal to zero. Combining (2) and (4), the inductor current value can be calculated by,
D + Dx DTsVC1 D + Dx DTsVC 3
average formula can be obtained as I L1 = I L 2 =  I L3 = I L 4 =  (13)
2 L1 2 L3
 1
 I L1 = I L 2 = 1 − 4 D + 2 D 2 I o On the basis of the inductors’ volt-second balance property
 (7) in DCM, resolving (8) and (11), following equations can be
I = I = 1− D obtained,
Io
 L 3 L4
1 − 4D + 2D2 DV DVC 3
where Io is the average output load current, Io=Vo/RL=GVdc/RL. VC1 = x C 3 Dx = (14)
D + Dx 2VC1 − Vdc − VC 3
B. DCM Steady-state Analysis
The proposed circuit operates in DCM when light loads are

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of Emerging and Selected Topics in Power Electronics
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0.05 (16)
CCM where symbol “^” indicates the small-signal perturbations of
0.04
DCM the state variables’ equilibrium points. Resolving (16) with
udc(s)=0, and due to Vo=2VC1, the transfer function from control
Kcrit=2Lfs/R

0.03
duty cycle d(s) to capacitor voltage uC1(s) can be expressed as
0.02 uˆC1 ( s ) b5 s 5 + b4 s 4 + b3 s 3 + b2 s 2
Gvd ( s ) = = (17)
dˆ ( s ) a6 s + a5 s 5 + a4 s 4 + a3 s 3 + a2 s 2 + a1s + a0
6
0.01 uˆdc ( s )=0

where
( )
0
0 0.05 0.1 0.15 0.2 0.25 a6 = L2C 3Co , a4 = LC 2Co 7 − 10 D + 5D 2
Duty cycle, D 

Fig. 5. Boundary condition between CCM and DCM of the proposed
( )
2
a2 = CCo 1 − 4 D + 2 D 2 , a5 = a3 = a1 = a0 = 0
circuit. 
Due to VC1=VC2=Vo/2, substituting (13) into (8), expression

b5 = L2C 2Co  −2 I L 3 − I o  , b4 = LC 2CoVC 3 − L C I o
2 2
of Dx and DCM output gain voltage can be derived as
   D DRL
DGDCM + D 2GDCM 2
− 2GDCM 
 Dx =   


GDCM − 2
(15) 
2
b3 = LCCo  2 − D −  I o − 7 − 4 D + 2 D I L 3 
D
2


( )

 D ( D + Dx ) + 2 K
2
GDCM =

LC 2 − 2 D + D I o
2
( )
 2 KDx 
b2 = 2CCoVC 3 1 − 4 D + 2 D − (2
)
Based on (15), the DCM output gain voltage curve GDCM as  DRL

a function of duty cycle D for the proposed circuit is depicted in On the basis of the transfer function in (17), Bode diagram of
Fig. 6. One can find from this figure that the DCM output gain the proposed circuit is drawn in Fig. 7 with the following
voltage is higher than that of in CCM. And as K increases, the parameters Vdc=36V, L1=L2=240uH, L3=L4=400uH,
voltage gain decreases accordingly. When K≥0.04667, the C1=C2=C3=C4=100uF, Co=220uF, D=0.22, and the load
resistance RL=200Ω. From Fig. (7), it can be seen that the slope
proposed circuit operates in CCM mode.
25 inclination on the crossing frequency is about −20dB/dec,
which implies that the open-loop system’s stability can be
20 indemnified. For the purpose of achieving stable operation
Output Voltage Gain, G DCM

under load change or input voltage change, the PID voltage

15 loop control strategy, as displayed in Fig. 8, can be used for the
GDCM when K=0.01
proposed topology.
Bode Diagram
60
10 GDCM when K=0.02 50
40
Magnitude (dB)

30
20
5 GCCM when 10
K≥0.04667 0
-10
GDCM when K=0.03 -20
0 -30
0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 720
Duty cycle, D 540
Phase (deg)

Fig. 6. Relationship between the output DCM gain voltage and the 360

operating duty cycle D. 180

0
-180 2
10 103 104 105
III. SMALL-SIGNAL DYNAMIC ANALYSIS Frequency (rad/s)

Fig. 7. Bode diagram of the control-to-capacitor voltage transfer function

Due to the impedance network in the proposed circuit is Gvd(s) for the proposed circuit.
symmetric, we assume that all inductors have the same
inductance value, all capacitors have the same capacitance Vref D
∑ PID
S1
value, which aims to simplify the small-signal dynamic Limiter
analysis. The capacitor voltages and inductor currents are Vo
chosen as state variables, the Vdc input voltage is selected as the
Fig. 8. PID controller of the voltage loop control strategy for the
input variable. The state-space average formulas can be derived proposed circuit.
from Section-2. After Laplace transformation, by detaching ac
components, the small-signal transfer function of the proposed Based on the small-signal transfer function derived in (16),
circuit can be derived by resolving (16) with udc(s)=0, d(s)=0, and due to Vo=VCo, the
 sL1iˆL1 ( s ) = VC 3dˆ ( s ) + uˆC 1 ( s ) − (1 − D ) uˆC 3 ( s ) output impedance of the proposed topology can be express as
 
 sL3iˆL 3 ( s ) = ( 2VC 1 − Vdc ) dˆ ( s ) + uˆC 3 ( s ) + (1 − D ) uˆdc ( s ) − 2 (1 − D ) uˆC 1 ( s ) uCo ( s ) d2 s2
 Z out ( s ) = 
=
 sC1uˆC 1 ( s ) = − ( 2 I L 3 + I o D ) dˆ ( s ) − uˆCo ( s ) RL − iˆL1 ( s ) + 2 (1 − D ) iˆL 3 ( s ) i out ( s )  
c5 s5 + c4 s 4 + c3 s 3 + c2 s 2 + c1s1 + c0
udc ( s ) = 0,d ( s ) =0

 sC3uˆC 3 ( s ) = − I L1d ( s ) − iˆL 3 ( s ) + (1 − D ) iˆL1 ( s )
ˆ
(18)

 sCouˆCo ( s ) = I o d ( s ) D − DiL1 ( s ) − DiL 3 ( s )
ˆ ˆ ˆ where d 2 =(1- D)2 L13 L33Co2 (2 L1 + L3 ) 2

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of Emerging and Selected Topics in Power Electronics
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c5 = (1 − D ) RL L14 L43C1 C3 Co2 (2 L1 + L3 ) duCo x %V

 Co = Co C Co = I o (23)
c4 =0

dt (1 − D ) Ts
  ( )
c3 = (1 − D ) RL L13 L33Co2 (2 L1 + L3 ) (1 − D ) L3C1 + 4 L1C3 + L1C1 + L3C3 
2

To stint the ripple on the output capacitor voltage by using
 xC%, from (23), the Co capacitance should be,
 2 = ( − ) 3 3
+  − − 
(1 − D )
c D 1 D L L C
1 3 3 o C (2 L1 L )
3  2(1 D ) L1 L3

c1 = (−4 D5 + 20 D 4 − 36 D3 + 20 D 2 − D + 1) RL L13 L33Co2 (2 L1 + L3 ) Co = (24)
 xC % f s RL
c0 = L12 L33Co  f ( D ) L1 L3 − 2 D (1 − D)3 L23 + (8( D3 − 3D 2 + 3D − 1) + f ( D)) L12 
   C. Selection of the Active Switching Devices
 f ( D) = 2 D5 − 10 D 4 + 23D3 − 27 D 2 + 16 D − 4
 Normally, the parameter design of diodes and active power
switches can be chosen on the basis of their voltage and current
IV. PARAMETER DESIGN GUIDELINE stresses, respectively. Based on the steady-state theoretical
A. Inductance Selection analysis in Section 2, the voltage and current stresses of diodes
and switch S1 can be derived as,
On the basis of the theoretical principle analysis in Section 2,
 D
VD1 = VD 2 = 1 − 4 D + 2 D 2 Vdc
from (1), the inductor current ripples can be obtained as,
 VC1  DTs V  DTs 
iL1 = iL 2 = C 2  1− D
 L1 L2 VD 3 = VD 4 = Vdc (25)
 (19)
 1 − 4 D + 2D2
i = VC 3  DTs i = VC 4  DTs 
 L3 L4 1
L3 L4 VDo = VDin = VS1 = Vdc
 1 − 4D + 2D2
Assuming that an allowable inductor current fluctuation
range xL% is given in advance, the inductor current ripple is 
i = i = i = i = Io
ΔiL=xL%IL. Substituting the steady-state capacitor voltage and
 D1 D2 D3 D4
1 − 4D + 2D2
inductor current expressions into (19), the required inductance 
can be selected as follows,  2 (1 − D ) I

 L1 = L2 =
(
DRL 1 − 4 D + 2 D 2 ) iDin =
 1 − 4D + 2D 2 o
I iDo = o
D
(26)
 2 f s xL % 
 (20) 
( )
Io
 DRL 1 − 4 D + 2 D 2 iS1 =
 3

L = L4 =
2 (1 − D ) f s xL %
2  (
D 1 − 4D + 2D2 )
Therefore, for a specific load resistance RL, the duty ratio D
and the switching frequency fs, the inductance of L1, L2, L3 and V. CHARACTERISTIC CONTRADISTINCTION WITH OTHER
DC-DC NON-ISOLATED HIGH STEP-UP CONVERTERS
L4 will be determined by (20) directly.
B. Capacitance Selection A. Comparison of the number of components
The capacitors can be designed in accordance with the The utilized passive/active elements’ numbers in these dc-dc
capacitor voltage ripple. As presented in Fig. 4(a), from (2), one high boost converters are compared and tabulated in Table I.
can obtain, From this table, one can observe that the number of inductors,
capacitors, diodes and switches employed in the proposed
 ( − I L1 − I o D )  DTs − I  DTs
uC1 = uC 3 = L3 circuit is totally the same as that of the EB-ZSC [32], DA-qZSC
 C1 C3 [28] and EB-qZSC [33]. In contrast to the SL-ZSC [31], the
 (21)
u = ( − I L 2 − I o D )  DTs u = − I L 4  DTs
proposed topology utilizes two more capacitors, two diodes less,
and the same number of inductors. Therefore, it can be
 C2 C4
 C2 C4 concluded from Fig. 5 that by using the same total number of
If the permitted capacitor voltage fluctuation range is limited elements in the power circuit, the proposed topology can
by xC%, the capacitor voltage ripple can be expressed as achieve the highest output gain voltage under the same
ΔuC=xC%VC. Substituting (7) into (21), the capacitances C1, C2, operating duty cycle.
C3, C4 of the proposed circuit should be selected as: B. Comparison of output gain voltage
 2 (1 − D )(1 − 2 D ) According to (6), Fig. 9 depicts the output gain voltage
C1 = C2 =
 ( )
1 − 4 D + 2 D 2 f s xC % RL contradistinction between the proposed circuit and other dc-dc
 (22) non-isolated high step-up converter topologies (DA-qZSC[28],
2 D (1 − D )
2
 SL-ZSC[31], EB-ZSC[32] and EB-qZSC[33]). It can be
 3
C = C =

4
( )
1 − 4 D + 2 D 2 f s xC % RL observed from Fig. 9 that the output gain voltage of the
proposed circuit is higher than those of the other four
For the output capacitor Co, when S1 is switched off, output topologies during the whole operating duty ratio range.
diode Do will be reverse blocked. Then, the current flowing
through capacitor Co will be equal to the load current Io. The C. Comparison of voltage and current stresses
corresponding voltage-current relationship can be described as

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

Table I
Voltage and Current Stresses Contradistinction for These High Boost Converters

Proposed
Topologies SL-ZSC[31] DA-qZSC[28] EB-ZSC[32] EB-qZSC[33]
Converter
1+ D 1 2 (1 − D )
2
Output Voltage 1 1
(1 − 2 D )(1 − D )
2
Gain (G) 1 − 3D 1 − 4D + 2D2 1 − 4D + 2D2 1 − 4D + 2D2
Inductor 4 4 4 4 4

Capacitor 3 5 5 5 5

Diode 8 6 6 6 6

Switch 1 1 1 1 1
2
Capacitor DG (1–D) G
(1–D)G/(1+D) (1–D)2G D(1–D)G G/2
Voltage Stresses (1-2D)G
2DG/(1+D) (1–D)G D(2–D)G G/(2-2D)
(VC/Vdc) (1-D)(1-2D)G (1–3D+D2)G
G
Diode Voltage 2DG G G G G/(2-2D)
Stresses (1-2D)G (1–D)G/(1+D) DG DG G/2/(1-D)2
(VD/Vdc) D(3–2D)G
(1-D)(1-2D)G DG/(1+D) (1–D)G (1–D)G GD/2/(1-D)2
Voltage Stress
G G G G G/2/(1-D)2
of switches
Inductor Iin Iin Iin Iin/2/(1-D)
Iin/(1+D) (1-D)Iin
Current Stress (1-D)2Iin (1-D)Iin (1-D)Iin Iin/2/(1-D)/(1-D)
Current Stress
4Iin/(1+D) (4-5D+2D2)Iin (4-2D)Iin (4-2D)Iin Iin/2/D/(1-D)/(1-D)
of switches

14 DA-qZSC, SL-ZSC and EB-qZSC. The switching current

12
Proposed Converter
stress flow through MOSFETs is compared and plotted in Fig.
10(e). The proposed method has lower switching current stress
Output Voltage Gain, G

10
EB-qZSC[33]
than EB-ZSC and EB-qZSC, but slightly higher than that of the
8
SL-ZSC[31] DA-qZSC and SL-ZSC.
30 40
6
35 EB-ZSC[32]
EB-ZSC[32]
Total Capacitor Voltage stress

25 EB-ZSC [32]
Total Diode Voltage Stress

4 30
EB-qZSC[33]
20 EB-qZSC [33]
25
2
15 20 DA-qZSC[28]
DA-qZSC[28] DA-qZSC [28]
0 15 Proposed Converter
10
0 0.05 0.1 0.15 0.2 0.25 10
Duty Cycle, D 5
SL-ZSC [31] 5 SL-ZSC[31]
Proposed Converter
Fig. 9. Output gain comparison for these non-isolated dc-dc converters. 0 0
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Output Voltage Gain, G Output Voltage Gain, G
For these non-isolated dc-dc high step-up circuit topologies, (a) (b)
their corresponding current and voltage stress of each element 40 12
Switching Voltage Stress of MOSFETs

EB-ZSC[32]
is summarized in Table I. According to Table I, the entire 35 EB-ZSC [32]
Total Inductor Current Stress

10
30
capacitor voltage stress confrontation is depicted in Fig. 10(a). 25 EB-qZSC[33] 8
EB-qZSC[33]

As shown in this figure, the overall capacitor voltage stress of 20 SL-ZSC[31] 6 SL-ZSC[31]

the advanced converter is lower than that of the EB-ZSC [32], 15

DA-qZSC[28] 4
DA-qZSC[28]

10
but a little higher than those of the SL-ZSC [31], DA-qZSC [28] 5
Proposed
Converter 2
Proposed Converter
and EB-qZSC [33]. The total inductor current stress 0
1 2 3 4 5 6 7 8 9 10
0
1 2 3 4 5 6 7 8 9 10 11 12
contradistinction for these high boost circuit topologies is Output Voltage Gain, G Output Voltage Gain, G

(c) (d)
presented in Fig. 10(c). One can find that for producing the 45
EB-ZSC[32]
same output gain voltage G, the raised circuit has lower total 40
Total Switching Current Stress

35 SL-ZSC[31]
inductor current stress than those of the EB-ZSC, SL-ZSC and 30
EB-qZSC. The total diode voltage stress of the advanced 25 Proposed
Converter
method, as revealed in Fig. 10(b), is lower than those of the 20

other four topologies (SL-ZSC, EB-ZSC, DA-qZSC and EB- 15

DA-qZSC[28]
10
qZSC). Fig. 10(d) compares the voltage stress of power 5
EB-qZSC[33]

MOSFETs. One can find that for achieving same output gain 0
3 4 5 6 7 8 9 10 11 12
voltage, the proposed converter has the lowest voltage stress Output Voltage Gain, G

(e)
across the power MOSFETs than that of the EB-ZSC, Fig. 10. Current and voltage stresses contradistinction for these high

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of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

step-up circuit topologies. (a) Capacitor voltage stress contradistinction, From Fig. 11(a), it can be seen that the total inductors'
(b) Diode voltage stress contradistinction, (c) Comparison of inductor volume of the proposed converter is lower than EB-ZSC,
current stress, (d) Contradistinction of switching voltage stress, (e)
Switching current stress comparison.
EB-qZSC and SL-ZSC, while it is only a little higher than
DA-qZSC. Meanwhile, it can be observed from Fig. 11(b) the
D. Volume size comparison of passive components total capacitors' volume of the proposed converter is higher
Generally, the volume and cost of a converter is determined than the DA-qZSC, but lower than those of the SL-ZSC,
by the size of its passive components. Since the size and weight EB-ZSC and EB-qZSC.
of inductors and capacitors are directly proportional to their E. Power loss analysis and efficiency comparison
numbers and the amount of energy they stored in the converter.
Therefore, the total volume of inductors is proportional to For the advanced converter, the overall power loss is
[L×IL2×(inductors' number)], total volume of capacitors is composed of inductor loss, diode loss, capacitor loss and power
proportional to [C×VC2×(capacitors' number)]. MOSFET loss. And they will be calculated detailly as follows.
For the proposed converter, the total inductors' and 1) Inductor Loss: The power loss of inductor is composed of
capacitors' volume can be expressed as core loss and winding copper loss. The core loss is very trivial

Ltotal-5 =
(
2 DRL 1 − 4 D + 2 D 2 )I 2
+
(
2 DRL 1 − 4 D + 2 D 2 )I 2
and can be neglected when contrasted with copper loss. The
winding copper loss mainly relies on its flowing current and the
2 (1 − D ) xL % f S
L1 2 L3
2 xL % f S
(27) parasitic resistance. From (7), the approximative inductor
DG53Vdc 2 currents rms value can be derived as:
=
(1 − D ) xL % f s RL
2
 Io
(1 − 2 D ) G5  V 2 + DG5  V 2  I L1( RMS) = I L 2( RMS) =
Ctotal-5 = ( ) ( )  1 − 4D + 2D2
(1 − D ) xV % f S RL C1 xV % f S RL C 2  (29)
(28) I (1 − D ) I o
=
( 2D 2
)
− 2 D + 1 G53Vdc2  L3( RMS) = I L 4( RMS) = 1 − 4 D + 2 D 2
2 (1 − D ) xV % f s RL
2

Then, the entire inductor power loss can be calculated by

where G5 is the output voltage gain of the proposed converter,
G5=2(1-D)2/(1-4D+2D2). ( ) ( ) (
PrL−loss = 2 I L21 RMS rL + 2 I L23 RMS rL = 4 − 4 D + 2 D 2 I L21( RMS)rL (30) )
Therefore, based on (27)-(28), by choosing the same 2) MOSFET Loss: Normally, the MOSFET power loss is
parameters of Vdc=36V, fs=50kHz, RL=200Ω, permitted composed of switching power loss and conduction loss during
fluctuation range of inductor current and capacitor voltage ON and OFF states. On the basis of Fig. 4(a), the current
xL%=30% and xV%=2% for these five high step-up impedance flowing through S1 is
source dc-dc converters, the relationship between the total  Io
( 0, DTs )
inductors'/capacitors' volume and the output voltage gain G
have been plotted and compared in Fig. 11.


iS1 = 
(
D 1 − 4 D + 2D2 )  I S1( RMS ) =
DI o
(31)
10 0

( DTs , Ts ) (
D 1 − 4D + 2D2 )
9 EB-ZSC[32] 
Total Inductor Volume Comparison

8
EB-qZSC[33] Based on (31), the conduction power loss and switching loss
7
of S1 is
( )
6 SL-ZSC[31]
ton + toff Vdc I o ton + toff f s
5 Pswitching = f sVS 1iS 1 = (32)
( )
Proposed Coverter 2
4 2 2D 1 − 4D + 2D2
3
rDS I o2
2
DA-qZSC[28] Pcond = I S21( RMS) rDS = (33)
( )
2
1 D 1 − 4D + 2D2
0
1 2 3 4 5 6 7 8 9 10 where ton and toff are the ON/OFF delay times of S1, fs is the
Buck-Boost Factor, G
(a) switching frequency, rDS is the parasitic resistance of S1.
4 3) Diode loss: According to the theoretical steady-state
EB-ZSC[32]
analysis in Section-2, diode currents’ RMS value and average
Total Capacitor Volume Comparison

3.5
EB-qZSC[33] value can be derived as
3
 I D1,2 AVG = DI L1 I D1,2( RMS) = DI L1
2.5 SL-ZSC[31]
 ( )
I
 D 3,4( AVG ) = (1 − D ) I L1 I D 3,4( RMS) = 1 − DI L1
2 Proposed Coverter
 (34)
 I Din( AVG ) = 2 (1 − D ) I L 3 I Din( RMS) = 2 1 − DI L 3
1.5
DA-qZSC[28]
1

 I Do( AVG ) = I o I Do( RMS) = D  I o D
0.5

0
1 2 3 4 5 6 7 8 9 10 Then, the power loss caused by forward voltage drop VF can
Buck-Boost Factor, G
be obtained
(b)
Fig. 11 Volume size comparison of passive components. (a) Total
inductors' volume comparison, (b) Total capacitors' volume comparison.

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(
PVF − loss = 2 I D1( AVG ) + 2 I D 3( AVG ) + I Din ( AVG ) + I Do ( AVG ) VF ) (35) Internal Parasitic Parameters of Passive/Active Elements
Table II

( )
= 4 − 4 D + 2 D 2 VF I L1 + VF I o
Parameters Values
The total ohmic power loss caused by the diode parasitic
Parasitic resistance of inductors 0.12Ω
resistance rD is
KS300125A(142nH/N2)
PrD − loss =  2 I D2 1( RMS) + I Din  Core of inductors
( RMS) + 2 I D 3( RMS) + I Do ( RMS)  rD
2 2 2

(36) ESR of capacitors 100mΩ
=  2 + 4 (1 − D )  I L21 rD + rD I o2 D
3
  Diodes (RURG3060CC) 600V, 30A, VF(max)=1.5V
4) Capacitor Loss: According to Fig. 4(a) and (b), capacitor MOSFET S1 (FCH040N65S3) 650V, 65A, rDS(max)=0.04Ω
currents during ON and OFF states can be expressed as
 − (1 − 2 D ) 
( 0, DTs ) inductor power loss contradistinction is shown in Fig. 12(a).
 I L 3 ( 0, DTs ) − I L3
D  One can find from this figure that the proposed circuit has a
iC1,2 = iC 3,4 =  (37)
D lower inductor loss than EB-ZSC, SL-ZSC and EB-qZSC, but
 1 − 2D I  I ( DT , Ts )
( ) L1 ( DT , Ts )  (1 − D ) L 3 slightly higher than the DA-qZSC. Fig. 12(b) presents the
MOSFET power loss contradistinction. One can observe that
1 − D
 I o ( 0, DTs ) the proposed method has lower MOSFET power loss than that
iCo =  D (38) of the EB-ZSC and EB-qZSC, but higher than the SL-ZSC and
− I ( DT , Ts ) DA-qZSC. The contradistinction of capacitor loss and diode
 o
loss are presented in Fig. 12(c) and (d), respectively. It can be
Based on (34)-(35), the approximate capacitor current RMS found from Fig. 12(c) that the proposed circuit has lower diode
value can be derived as loss than those of the EB-ZSC, EB-qZSC and SL-ZSC, but
1− D 1− D higher than that of the DA-qZSC. It can be observed from Fig.
I C1,2( RMS ) = (1 − 2D ) I L1 I Co( RMS ) = Io (39) 12(d) that the capacitor loss of the advanced circuit is lower
D D
than the EB-qZSC and SL-ZSC, but slightly higher than that of
D
I L3 (40) IC 3,4( RMS ) = the EB-ZSC and DA-qZSC. The loss distribution profile of the
1− D proposed circuit topology is depicted in Fig. 12(e). One can
Then, the entire capacitor loss caused by the equivalent find that for producing higher gain voltage G, the main power
series resistance (ESR) rC is losses derive from inductors, MOSFETs and capacitors. Hence,
PrC − loss =  2 I C21( RMS) + 2 I C2 3( RMS) + I Do
2 
( RMS)  rC
on basis of the aforementioned power loss analysis, the
 calculated efficiencies for these dc-dc high step-up circuit
2 − 2D 2 1− D 2
(41)
=
D
(
I L1 rC 1 − 4 D + 5 D 2 + )
D o
I rC topologies are plotted and compared in Fig. 12(f). One can find
from this figure that the proposed circuit only has a lower
On the basis of the above power loss calculation and the efficiency than DA-qZSC [28], but higher than those of the
Table II parasitical parameters of elements, the power loss EB-ZSC [32], SL-ZSC [31] and EB-qZSC [33].
analysis results of SL-ZSC [31], EB-ZSC [32], DA-qZSC [28]
and EB-qZSC [33] are plotted and contrasted in Fig. 12. The
0.7 0.6 0.1
EB-ZSC[32]
0.6 EB-ZSC[32] 0.5 EB-ZSC[32]
MOSFET Loss Comparison
Inductor Loss Comparison

0.08 EB-qZSC[33]
Diode Loss Comparison

0.5
EB-qZSC[33] 0.4 SL-ZSC[31]
0.4 EB-qZSC[33] 0.06
SL-ZSC[31] 0.3
0.3
0.04
Proposed Converter 0.2 Proposed Converter
0.2
DA-qZSC[28] 0.02
0.1 0.1 Proposed
DA-qZSC[28] SL-ZSC[31] Converter DA-qZSC[28]
0 0 0
2 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10
Output Voltage Gain, G Output Voltage Gain, G Output Voltage Gain, G
(a) (b) (c)
0.5 0.8 1
DA-qZSC[28]
EB-qZSC[33] 0.7
0.9
Capacitor Loss Comparison

Inductor
Loss Distribution Percentage

0.4
Efficiency Comparison

0.6
SL-ZSC[31] Capacitor
0.8
0.5
0.3 Proposed
Converter 0.4 0.7
Proposed Converter
MOSFET
0.2 0.3
EB-ZSC[32] 0.6 SL-ZSC[31]
0.2 EB-ZSC[32]
0.1 Diode 0.5
0.1 EB-qZSC[33]
DA-qZSC[28]
0 0 0.4
3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10
Output Voltage Gain, G Output Voltage Gain, G Output Voltage Gain, G
(d) (e) (f)
Fig. 12. Power loss analysis and efficiency contradistinction. (a) Comparison of inductor loss. (b) MOSFET loss contradistinction. (c) Diode loss
contradistinction. (d) Comparison of capacitor loss. (e) Loss distribution profile of the proposed circuit. (f) Efficiency contradistinction.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

is 200V. MOSFET S1 type is FCH040N65S3 (650V, 65A,

VI. SIMULATION AND EXPERIMENTAL VERIFICATIONS rDSon= 40mΩ), and the diodes are RURG3060CC (600V, 30A,
A. Simulation results VF(max)= 1.5V). The 2SC0108T driver in the 2BB0108T basic
board is utilized to drive MOSFET S1.
To validate the properties of the proposed circuit, Matlab
simulation was implemented with the following parameters:
switching frequency fs=50kHz, capacitors C1=C2=C3=C4
=100uF, capacitor Co=220uF, output voltage Vo=200V, and
output power Po=200W.
iDin(A) VD1=VD2(V)
15 40
10
5 20
0 0
iL1=iL2(A) VD3=VD4(V)
8 150
6 100
50
4
iL3=iL4(A)
0
VDin(V)
Fig. 15. Experimental setup of the proposed circuit under test.
200
6
4 100 Fig. 16 reveals the experimental results when Vdc=36V,
2
140
0
200
VDo(V) D=0.22, fs=50kHz, RL=200Ω, L1=L2=240uH and L3=L4=
120
100
VC3=VC4(V)
VC1=VC2(V)
100 400uH. From Fig. 16(a), the inductor currents are increased and
80 0
220
Vo(V)
200
VDS(V) decreased linearly in one switching period, the proposed circuit
200
180
100
0
operates in CCM mode, and the output voltage Vo is about
0.4999 0.4999 0.5 0.4999 0.4999 0.5
t(s) t(s) 196V. As presented in Fig.16(b), the measured switching
(a) (b) voltage stress of S1 is about VDS=164V, the capacitor voltages
Fig. 13. Simulation results of the proposed circuit when Vdc=36V, VC1(=VC2) and VC3(=VC4) are pumped up to 98V and 119V,
D=0.22. which are slightly lower than that of the calculated values
iDin(A) VD1=VD2(V)
10 30
5
20
10
(101V and 129V) due to the parasitical parameters in
0
iL1=iL2(A)
0
150
VD3=VD4(V) active/passive elements. The diode voltage stresses (VD1, VD2,
4
3
2
100
50 VD3 and VD4) are revealed in Fig. 16(d), and the measured diode
1 0
4
iL3=iL4(A)
150
VDin(V) voltage stress of VD1(=VD2) is about 36V, VD3(=VD4) is about
3 100
2
1
50
0
128V. Fig. 16(c) presents the diode voltage stresses of VDin, VDo
140
120
VC3=VC4(V) 150
VDo(V)
and the input diode current stress iDin. It can be observed that
100
100
80
VC1=VC2(V) 50
0
when Din is forward conducted, Do is reverse-blocked, and the
Vo(V) VDS(V)
220 150
100
voltage stress VDin=VDo, is about 164V, which fits well with
200
180
0.4999 0.4999 0.5
50
0
0.4999 0.4999 0.5
simulation results.
t(s) t(s)

(a) (b)
Fig. 14. Simulation results of the proposed circuit when Vdc=60V, iL1:4A/div
D=0.156.
Fig. 13 and Fig. 14 present the simulation results when
Vdc=36V, D=0.22, L1=L2=240uH, L3=L4=400uH and Vdc=60V, iL3:4A/div
D=0.156, L1=L2=330uH, L3=L4=450uH, respectively. In Fig.
13(a) and Fig. 14(a), from top to bottom, the simulation Vo:100V/div Time:10us/div
waveforms are input current, inductor currents, capacitor
voltages and output voltage. The inductor current increases (a)
linearly when the switch S1 is turned on, and decreases linearly
when it is turned off. The proposed converter operates in CCM VC1:100V/div
mode. From Fig. 13(a) and Fig. 14(a), the steady-state capacitor
voltage VC1(=VC2) are boosted to 100V, VC3(=VC4) are promoted VC3:100V/div
to 129V and 120V. The output voltage of 200 V is the sum of
the capacitor voltage VC1 and VC2. Fig. 13(b) and Fig. 14(b)
VS1:200V/div
present the voltage stresses across diodes and switch S1. From Time:10us/div
Fig. 13(b), the diode voltage stresses are VD1=VD2=36.5V,
VD3=VD4=129.5V, VDin= VDo=166V and switching voltage (b)
stress VDS1=166V. In Fig. 14(b), the simulated switching
voltage stresses are VD1=VD2=22V, VD3=VD4=120V,
VDin=VDo=VDS1= 140V, which are in good accordance with
iDin:10A/div
theoretical values.
B. Experimental results VDin:200V/div
Measurements recorded on the 200W experimental
prototype, constructed in laboratory and shown in Fig. 15, are VDo:200V/div Time:10us/div
revealed in this section. Parameters of the experimental setup
(c)
are the same as parameters used in the simulation. The input
voltage Vdc is changed from 36V to 60V, and the output voltage

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

VD1:50V/div iDin:5A/div

iS1:10A/div Time:10us/div VDin:150V/div

Time:10us/div
VD3:80V/div
VDo:150V/div
(d)
(b)
Fig. 16. Experimental results of the proposed circuit when Vdc=36V,
D=0.22, fs=50kHz and RL=200Ω. (a) Inductor current iLI, iL3 and output
voltage Vo; (b) Capacitor voltage VC1, VC3 and switching voltage stress VC1:50V/div
VS1; (c) Diode current stress iDin and diode voltage stress VDin, VDo; (d)
Switching current stress iS1 and diode voltage stress VD1, VD3.
VC3:50V/div
Fig. 17 shows the corresponding experimental results
when Vdc=60V, D=0.156, fs=50kHz, RL=200Ω, L1=L2= 330uH
and L3=L4=450uH. It can be seen from Fig. 17(a) that the
inductor currents are increased and decreased linearly during VS1:150V/div Time:10us/div
one switching period, and the output voltage is about 196V. In
(c)
Fig. 17(b), the waveforms from top to bottom are input diode
current stress, diode voltage stress VDo and VDin. And the
measured voltage stress value of VDo (=VDin) is about 140V. The
capacitor voltages and switching voltage stress VDS are VD1:25V/div
measured and presented in Fig. 17(c). From this figure, one can
find that the experimental capacitor voltages VC1(=VC2),
iS1:5A/div Time:10us/div
VC3(=VC4) are pumped up to 98V and 116V, respectively. Fig.
17(d) reveals the diode voltage stress (VD1, VD2, VD3, VD4) and
switching current stress iS1, and the measured voltage stress of VD3:80V/div
VD1(=VD2) is about 20V, VD3(=VD4) is about 120V, which (d)
matches the theoretical steady-state analysis very well. Fig. 17. Experimental results of the proposed circuit when Vdc=60V,
For the purpose of assessing the dynamic response D=0.156, fs=50kHz and RL=200Ω. (a) Inductor current iL1, iL3 and output
voltage Vo; (b) Diode current stress iDin and diode voltage stress VDin, VDo;
characteristic of the advanced circuit, a PI controller, on the (c) Capacitor voltage VC1, VC3 and switching voltage stress VS1; (d)
basis of the small-signal modeling dynamic analysis is devised. Switching current stress iS1and diode voltage stress VD1, VD3.
From the transfer function (17) in Section III, it can be found Bode Diagram

that there are one complex zero and one real zero lies in the 60
Gm = 20.5 dB (at 441 Hz) , Pm = 90.5 deg (at 9.78 Hz)

right half plane which makes this system as a non-minimum 40

20
Margin (dB)

phase system. A PI controller structure as shown in (42) is used 0

-20

for compensation. And Feedback gain is taken as unity. -40

1 + ( s Z )
-60
-80

Gc ( s ) =
-100
(42) 720

s I 540
Phase (deg)

360
Control design tool ‘SISOTOOL’ which is provided in 180
Open-loop frequency response

Compensated close-loop frequency response

MATLAB is applied for controller design. It can be observed 0

-180 0
from the open-loop frequency response in Fig. 18 that first peak 10 101 102
Frequency (Hz)
103 104

of Gvd(s) occur at 403 Hz or 2533 rad/s, which is a pole
frequency. After this frequency, all the RHP and LHP zero
frequencies, and other pole frequencies occur. Therefore, it
would be desirable to let the first peak well below 0dB to
decrease the effects of RHP zeros and other poles. The zero
frequency ‘ωZ’ of (42) is chosen to be same as first peak, i.e., ωZ
=2533 rad/s. By using the MATLAB, it can be found that
iL1:2A/div
iL3:2A/div
Vo:100V/div
Time:10us/div
(a)
Fig. 18. Bode diagram of the open-loop and compensated close-loop
frequency response.
the transfer function’s DC gain is 83.33. In addition, ωI can be
derived as 0.737rad/s by some calculations. For the proposed
circuit, the proper controller is designed and the Gc(s) can be
obtained as follows:
1 + ( s 2533)
Gc ( s ) = (43)
s 0.737
According to (43), the compensated closed-loop bode plot is
drawn in Fig. 18 and it is clear that the phase margin is about
90.5deg and the gain margin is 20.5dB. The Gm (gain margin)
and Pm (phase margin) are calculated in MATLAB software by
using “margin” function. These two margins are large enough
to make the proposed converter operates stability. Based on the
above designed PI controller, Fig. 19 shows the dynamic

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
close-loop output current io and voltage Vo experimental results
under the load transient variation between half load and full
load. One can observe that with appropriate devise of PI
controller, the proposed circuit’s output voltage will be stable
and insensitive to load step change.
Vo: 100V/div
io: 0.5A/div
Time:200ms/div
Fig. 19. Experimental dynamic results with load transient variation
between half load and full load.
The experimental efficiency of the proposed converter under
Vdc=36V and Vdc=60V with different output power is measured
and draught in Fig. 20. One can find from this figure that the
maximum experimental efficiency is about 94.8%. And the
efficiency was higher with the increase of the input voltage.
This is because the conduction loss on devices is low when
higher input and small duty ratio is employed, which will be
profitable to ameliorate the system efficiency.
96
95
Efficiency,ƞ (%)
94
93
92
Vdc=60V
91 Vdc=36V
90
100 120 140 160 180
Output Power (W)
Fig. 20. Measured experimental efficiency versus different output
powers of the proposed circuit.
VII. CONCLUSION
A non-isolated dc-dc high step-up converter with passive
switched-inductor-capacitor network is brought forward in this
paper. The main advantageous merits of the proposed circuit
are as follows: common ground between input and output, high
gain voltage with small duty cycle, simple structure and easy to
control. In addition, the proposed circuit has low voltage stress
across diodes and MOSFET, and low inductor current stress,
which are favourable to ameliorate the system cost and
efficiency. Theoretical steady-state principle, small-signal
dynamic analysis and parameter design guideline are also
revealed. The overall characteristic comparison, power loss
analysis and efficiency contradistinction with other dc-dc
non-isolated converters are addressed. Ultimately, both
simulation and experimental results are shown to confirm the
validity of the theoretical analysis. Therefore, one can conclude
that the proposed topology would be suitable for low power
high step-up implantations, such as battery-powered LED
lighting systems, medical X-ray equipment systems, TV-CRTs
and automobile high-intensity discharge lamps, where dc/dc
converter with high voltage conversion ratio is also required.
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REFERENCES
[1] M. Forouzesh, Y. P. Siwakoti, S. A. Gorji, F. Blaabjerg, and B. Lehman,
"Step-Up DC-DC Converters: A Comprehensive Review of
Voltage-Boosting Techniques, Topologies, and Applications," IEEE
Trans. Power Electron, vol. 32, no. 12, pp. 9143-9178, 2017.
[2] H. Liu, H. Hu, H. Wu, Y. Xing, and I. Batarseh, “Overview of high step
up coupled-inductor boost converters,” IEEE J. Emerg. Sel. Topics Power
Electron., vol. 4, no. 2, pp. 689–704, Jun. 2016.
[3] B. Gu, J. Dominic, J.-S. Lai, Z. Zhao, and C. Liu, “High boost ratio hybrid
transformer DC–DC converter for photovoltaic module applications,”
IEEE Trans. Power Electron., vol. 28, no. 4, pp. 2048–2058, Apr. 2013.
[4] A.Maroufkhani, D. KazemiKia, and K. Abbaszadeh, “A new
single-switch soft-switched high-step up DC-DC converter based on
magnetic coupling,” in Proc. 11th Power Electron. Drive Syst. Technol.
Conf., 2020, pp. 1–6.
[5] R. Hu, J. Zeng, J. Liu, Z. Guo, and N. Yang, “An ultrahigh Step-up
quadratic boost converter base on coupled-inductor,” IEEE Trans. Power
Electron., vol. 35, no. 12, pp. 13200–13209, Dec. 2020.
[6] S. Hasanpour, M. Forouzesh, Y. P. Siwakoti and F. Blaabjerg, “A Novel
Full Soft-Switching High-Gain DC/DC Converter Based on
Three-Winding Coupled-Inductor”, IEEE Trans. Power Electron., vol. 36,
no. 11, pp. 12656–12669, Nov. 2021.
[7] M. Rezaie, V. Abbasi, “Ultrahigh Step-Up DC-DC Converter Composed
of Two Stages Boost Converter, Coupled Inductor and Multiplier Cell”,
IEEE Trans. Ind. Electron., early access, doi:
10.1109/TIE.2021.3091916.
[8] J. Ding, S. Zhao, S. Gao and H. Yin, “A Single-Switch High Step-Up
DC-DC Converter Based on Three-Winding Coupled Inductor and Pump
Capacitor Unit”, IEEE Trans. Power Electron., early access, doi:
10.1109/TPEL.2021.3113255.
[9] J.-H. Lee, T.-J. Liang, and J.-F. Chen, “Isolated coupled-inductor
integrated DC–DC converter with non-dissipative snubber for solar
energy applications,” IEEE Trans. Ind. Electron., vol. 61, no. 7, pp.
3337–3348, Jul. 2014.
[10] K. I. Hwu and Y. T. Yau, “High step-up converter based on coupling
inductor and bootstrap capacitors with active clamping,” IEEE Trans.
Power Electron., vol. 29, no. 6, pp. 2655–2660, Jun. 2014.
200 220
[11] P. Upadhyay and R. Kumar, “A high gain cascaded boost converter with
reduced voltage stress for PV application,” Sol. Energy, vol. 183, pp.
829–841, 2019.
[12] X. Hu, P. Ma, J. Wang, and G. Tan, “A hybrid cascaded DC–DC boost
converter with ripple reduction and large conversion ratio,” IEEE J.
Emerg. Sel. Topics Power Electron., vol. 8, no. 1, pp. 761–770, Mar.
2020.
[13] T. Rahimi, L. Ding, H. Gholizadeh, R. Shahriva and R. Faraji, “An Ultra
High Step-up DC-DC Converter Based on the Boost, Luo, and Voltage
Doubler structure: Mathematical Expression, Simulation, and
Experimental”, IEEE Access, early access, doi: 10.1109/ACCESS.2021.
3115259.
[14] A. M. S. S. Andrade, E. Mattos, L. Schuch, H. L. Hey, and M. L. da Silva
Martins, “Synthesis and comparative analysis of very high step-up dc-dc
converters adopting coupled-inductor and voltage multiplier cells,” IEEE
Trans. Power Electron., vol. 33, no. 7, pp. 5880–5897, Jul. 2018.
[15] M. Guepfrih, G. Waltrich and T. Lazzarin, “High Step-Up DC-DC
Converter Using Built-in Transformer Voltage Multiplier Cell and Dual
Boost Concepts”, IEEE J. Emerg. Sel. Topics Power Electron., early
access, doi: 10.1109/JESTPE.2021.3063060.
[16] E. Babaei, H. M. Maheri, M. Sabahi, and S. H. Hosseini, “Extendable
nonisolated high gain DC-DC converter based on active-passive inductor
cells,” IEEE Trans. Ind. Electron., vol. 65, no. 12, pp. 9478–9487, Dec.
2018.
[17] S. Lee and H. Do, “Quadratic Boost DC–DC Converter with High
Voltage Gain and Reduced Voltage Stresses,” IEEE Trans. Power
Electron., vol. 34, no. 3, pp. 2397-2404, Mar. 2019.
[18] B. Krishna, V. Karthikeyan, “Active Switched-Inductor Network
Step-Up DC–DC Converter with Wide Range of Voltage-Gain at the
Lower Range of Duty Cycles”, IEEE J. Emerg. Sel. Topics Power
Electron., vol. 2, no. 4, pp. 431–441, Oct. 2021.
[19] T. Jalilzadeh, N. Rostami, E. Babaei, and M. Maalandish, “Non-isolated
topology for high step-up DC-DC converters,” IEEE J. Emerg. Sel.
Topics Power Electron, pp. 1–1, 2018, doi:
10.1109/JESTPE.2018.2849096.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3125403, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

[20] M. Rezaie, V. Abbasi, and T. Kerekes, “High step-up DC–DC converter Kaiwen Ye was born in Guangxi, China, in
composed of quadratic boost converter and switched capacitor”, IET 1997. He received the B.S. degrees in electrical
Power Electron., vol. 13, no. 17, pp. 4008-4018, Dec. 2020.
[21] S. Rostami, V. Abbasi and T. Kerekes, “Switched-capacitor based
engineering from the Nanjing University of
Z-source DC–DC converter”, IET Power Electron., vol. 12, no. 13, pp. Posts and Telecommunications (NJUPT),
3582-3589, Aug. 2019. Nanjing, China, in 2020. He is currently
[22] M. A. Salvador, T. B. Lazzarin, and R. F. Coelho, “High step-up DC-DC pursuing the M.S. degree in electrical
converter with active switched-inductor and passive switched-capacitor engineering with the Nanjing University of
networks,” IEEE Trans. Ind. Electron., vol. 65, no. 7, pp. 5644–5654, Jul.
Aeronautics and Astronautics (NUAA), Nanjing,
2018.
[23] J. M. de Andrade, R. F. Coelho, and T. B. Lazzarin, “High step-up dc–dc China.
converter based on modified active switched-inductor and His current research interests include power converters in renewable
switched-capacitor cells,” IET Power Electron., vol. 13, no. 14, pp. 3127– energy power generation systems.
3137, 2020.
[24] Y. Tang, T. Wang, and D. Fu, “Multicell switched-inductor/ Kang Liu was born in Hubei, China, in 1998. He
switched-capacitor combined active-network converters,” IEEE Trans. received the B.S. degree in electrical engineering
Power Electron., vol. 30, no. 4, pp. 2063–2072, Apr. 2015.
from Shenyang Jianzhu University, Shenyang,
[25] F. Z. Peng, “Z-source inverter,” IEEE Trans. Ind. Appl., vol. 39, no. 2, pp.
504–510, Mar./Apr. 2003. China, in 2020. He is working toward the M.S.
[26] A. Ravindranath, S. K. Mishra, and A. Joshi, “Analysis and PWM control degree in power electronics from Nanjing
of switched boost inverter,” IEEE Trans. Ind. Electron., vol. 60, no. 12, University of Aeronautics and Astronautics
pp. 5593–5602, Dec. 2013. (NUAA), Nanjing, China, since 2020.
[27] G. Zhang, Z. Wu, S. Yu, H. Trinh and Y. Zhang, “Four Novel Embedded His current research interests include power
Z-Source DC–DC Converters”, IEEE Trans. Power Electron., vol. 37, no. converters and renewable energy systems.
1, pp. 607–616, Jan. 2022.
[28] C. J. Gajanayake, F. L. Luo, H. B. Gooi, P. L. So, and L. K. Siow, Bo Zhang (M’03–SM’15) was born in
“Extended-boost Z-source inverters,” IEEE Trans. Power Electron., vol.
25, no. 10, pp. 2642–2652, Oct. 2010. Shanghai, China, in 1962. He received the B.S.
[29] H. Shen, B. Zhang, D. Qiu, and L. Zhou, “A Common Grounded Z-source degree in electrical engineering from Zhejiang
DC-DC Converter with High Voltage Gain,” IEEE Trans. Ind. Electron., University, Hangzhou, China, in 1982, the M.S.
vol. 63, no. 5, pp. 2925–2935, May 2016. degree in power electronics from Southwest
[30] M. H. Esmaeili, E. Babaei, M. Sabahi, “High Step-Up Quasi-Z Source Jiaotong University, Chengdu, China, in 1988,
DC–DC Converter,” IEEE Trans. Power Electron., vol. 33, no. 12, pp.
10563–10571, Dec. 2018. and the Ph.D. degree in power electronics from
[31] M. Zhu, K. Yu, and F. L. Luo, “Switched-inductor Z-source inverter,” Nanjing University of Aeronautics and
IEEE Trans. Power Electron., vol. 25, no. 8, pp. 2150–2158, Aug. 2010. Astronautics, Nanjing, China, in 1994.
[32] H. Fathi and H. Madadi, “Enhanced-boost z-source inverters with He is currently a Professor with the School of Electric Power, South
switched z-impedance,” IEEE Trans. Ind. Electron., vol. 63, no. 2, pp. China University of Technology, Guangzhou, China. He has authored
691–703, Feb. 2016.
[33] V. Jagan, J. Kotturu, and S. Das, “Enhanced-boost quasi-z-source
or coauthored six books in IEEE-Wiley and Springer, more than 450
inverters with two switched impedance network,” IEEE Trans. Ind. technical papers and holds 100 patents.
Electron., vol. 64, no. 9, pp. 6885–6897, Sep. 2017. His current research interests include nonlinear analysis, modeling
[34] Y. Gu, Y. Chen, B. Zhang, D. Qiu and F. Xie, “High Step-Up DC–DC and control of power electronic converters, and wireless power
Converter with Active Switched LC-Network for Photovoltaic Systems”, transfer applications.
IEEE Trans. Energy Conversion., vol. 34, no. 1, pp. 321–329, Mar. 2019.
[35] M. K. Nguyen, T. D. Duong, Y. C. Lim, “Switched-Capacitor-Based
Dual-Switch High-Boost DC–DC Converter,” IEEE Trans. Power
Electron., vol. 33, no. 5, pp. 4181–4189, May. 2018.
[36] H. Shen, B. Zhang, D. Qiu, “Hybrid Z-source Boost DC–DC Converters,”
IEEE Trans. Ind. Electron., vol. 64, no. 1, pp. 310–319, Jan. 2016.
[37] G. Zhang, H. Chen, S. Yu, and C. K. Tse, “Impedance strengthening and
weakening networks for power converter analysis and design,” IEEE
Trans. Power Electron., vol. 36, no. 9, pp. 9717–9721, Sep. 2021.

Xiaoquan Zhu was born in Anhui, China, in

1990. He received the B.S. degree in School of
Information and Control engineering from China
University of Mining and Technology, Xuzhou,
China, in 2014, and the Ph.D. degree in power
electronics at the School of Electric Power
Engineering, South China University of
Technology, Guangzhou, China, in 2019. He is
currently a lecturer with the College of
Automation Engineering, Nanjing University of Aeronautics and
Astronautics, Nanjing, China.
His current research interests include renewable energy power
generation systems and wireless power transfer applications.

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