See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/303027814

Electric Vehicle Charging Station With an Energy Storage Stage for Split-DC
Bus Voltage Balancing

Article  in  IEEE Transactions on Power Electronics · January 2016

DOI: 10.1109/TPEL.2016.2568039

CITATIONS READS
112 3,014

2 authors:

Sebastian Rivera Bin Wu

Delft University of Technology Arizona Center for Reproductive Endocrinology and Infertility
43 PUBLICATIONS   1,331 CITATIONS    379 PUBLICATIONS   22,332 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

PHEV Charging Station for Urban Energy Systems View project

Proyecto FONDEF IDeA en Dos Etapas ID22I10226 (2022-2024). Sistema Integrado de alta eficiencia para la captura y destrucción de contaminantes de aire de interior
(UniTAir). View project

All content following this page was uploaded by Sebastian Rivera on 14 October 2018.

The user has requested enhancement of the downloaded file.

2376
Electric Vehicle Charging Station With an Energy
Storage Stage for Split-DC Bus Voltage Balancing
Sebastian Rivera, Member, IEEE, and Bin Wu, Fellow, IEEE
Abstract—This paper proposes a novel balancing approach for
an electric vehicle bipolar dc charging station at the megawatt
level, enabled by a grid-tied neutral-point-clamped converter. The
study uses the presence of an energy storage stage with access to
both of the dc buses to perform the complementary balance. It
proposes a generic balancing structure that can achieve balance
regardless the kind of energy storage system (ESS) employed. This
is aiming to reduce the hardware requirements of the system and
maximize the usage of the ESS, whose main function is to per-
form the energy management related tasks. To meet this purpose,
a three-level dc–dc interface is employed, allowing to compensate
the dc currents with a single ESS. Furthermore, in order to pre-
vent the appearance of even-order harmonics in the input current
during asymmetrical operation, an alternative switching sequence
for the central converter is proposed. Results indicate that, without
altering dramatically the charging process of the ESS, it is possible
to cover the whole load scenario without the need of a balancing
circuit. This allows the use of off-the-shelf products both for the
rectifier and the fast chargers. In this paper, simulation and exper-
imental results are presented to validate the proposed balancing
strategy.
Index Terms—Bipolar dc bus, electric vehicles (EVs), energy
storage stage, fast charger, power balance management, three-level
dc–dc converter.
I. INTRODUCTION
LUG-IN electric vehicles (EVs), considering under this
P category to both plug-in hybrid electric and battery EVs,
have emerged as the most probable successor for conventional
internal combustion engine vehicles. During these last years the
sales of these vehicles have been constantly increasing and it
is expected to remain in this trend for the upcoming years [1],
[2]. Despite of the increasing EV fleet, these vehicles still have
to solve some shortcomings before becoming a real alternative
to transportation. The long recharging process of the batter-
ies, limited mileage capacity (typically below 200 km) and the
lack of public fast charging infrastructure are the main barriers
to its widespread usage [3]–[5]. However, to allow a large-
scale penetration of this technology changes are required also
from the grid point of view, as the electricity demand will grow
accordingly [6]. Nowadays, there is no real threat to the utility
Manuscript received August 24, 2015; revised January 4, 2016 and April
1, 2016; accepted May 3, 2016. Date of publication May 12, 2016; date of
current version December 9, 2016. This work was supported by Toronto Hydro
(THESL) through project TH1302 at the Centre for Urban Energy, Ryerson
University. Recommended for publication by associate editor R. Zane.
S. Rivera is with the Department of Electrical & Computer Engineering,
University of Toronto, Toronto, ON M5S, Canada (e-mail: s.rivera.i@ieee.org).
B. Wu is with the Department of Electrical and Computer Engineering, Ryer-
son University, Toronto, ON M5B 2K3, Canada (e-mail: bwu@ee.ryerson.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2016.2568039
0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017
grid, as still the automotive industry is mainly sourced by the
gasoline supply chain, but this will gradually shift to a larger
electricity consumption with transportation purposes, and if it is
not addressed properly, the actual electric system will be unable
to satisfy this demand [2], [7].
In order to address the impacts of a large-scale adoption of
these vehicles in the utility systems, several studies have been
carried out [8]–[12], mostly based on the conventional slow
charging process of the batteries. This is mainly because con-
ventional charging is expected to remain as the preferred charg-
ing method [7], and also the fast charging process of the EV
batteries is still not a widespread practice among the owners,
due to the lack of facilities and misconceptions regarding the im-
pact of this process to the battery pack. However, fast charging
methods are still essential for a large-scale adoption of EVs, as
it will provide more flexibility to the drivers, occasional longer
trips addressing range anxiety [13]–[16]. Additionally, in or-
der to reduce power consumption from the utility grid during
peak consumption hours, the presence of energy storage systems
(ESSs) in these stations is gaining attention [5].
An alternative to enable fast charging is in the form of fast
charging stations, which refers to the concept of having high-
power fast chargers installed off-board, similar to gas stations
located in public places. The structure of these charging stations
can either be with an ac bus, where each charging unit is fed by
its independent ac–dc stage, or each unit connected to a common
dc bus enabled by a single ac–dc stage with higher power ratings
[5], [17]. Currently, fast charging is only enabled by standalone
units, each one with its independent rectifier stage [18]–[20]
using the ac-bus concept.
However, considering the dc nature of the loads, the com-
mon dc-bus configuration appears as the viable solution, and
also presents advantages in terms of cost, efficiency, and size,
as fewer power conversion stages are needed [5], [21], [22].
Moreover, this structure facilitates the integration of distributed
generators or ESSs.
The central converter stage plays a fundamental role in this
charging architecture, and is desirable to provide several fea-
tures as low distortion operation, high power capability, fully
adjustable power factor, reduce the size of the input filters,
while featuring a reduced number in both active and passive
components. Among the alternatives, conventional two-level
voltage source converter might arise, however, it has a limited
capacity to fulfill power ratings, power quality and efficiency re-
quirements due to semiconductors voltage/currents limits [23].
Other works propose the use of a 12-pulse diode bridge rectifier,
improving its harmonic performance through the use of an active
filter stage [5]. However, the lack of power factor control and
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING
Fig. 1. Proposed charging station architecture with balancing ESS.
its unidirectional power flow capability reduces the potential of
the charging station.
A different dc-bus concept is proposed and validated in [17].
The structure is based in the use of a central neutral-point-
clamped (NPC) converter enabling a bipolar dc bus. The use
of this split dc bus provides flexibility to the connection of the
loads, has higher voltage and power handling capabilities and re-
duced step-down effort of the dc–dc stages. However, given the
adoption of the bipolar structure and the intended application,
the balance control becomes essential. In [17], this was done
by adding an additional circuit to the system, which enhances
the balancing capabilities of the grid-tied converter. The result
led to balanced dc voltages even under severe unbalanced load
conditions. Taking a different approach, this paper proposes a
novel balancing method that uses the presence of the existing
ESS, regardless of its type, to perform the complementary bal-
ancing actions. The idea is to relocate the power consumption
of the ESS in order to keep the central converter operating in its
balanced zone. This is achieved by the use of a three-level dc–dc
interface. As it will be demonstrated, the only requirement of
the approach is to meet the minimal balancing power. However,
it is important to mention that the presence of this stage is for
managing the energy consumption of the charging station, and
its operation will be used toward the prevention of drifts in the
dc voltages. It will be shown that the presence of this stationary
load in the system can be used to complement the balancing
capabilities of the central converter. This will lead to the elim-
ination of the additional NPC leg, thus reducing the cost of the
system. Moreover, the presence of this stage will allow the use
of off-the-shelf products for both, the central converter, and the
fast charging units. This use of standardized components leads
to lower hardware costs, improved system robustness in addition
to cost-effective implementation and maintenances [24].
In the following sections, the inclusion of an energy storage
stage in the system will be discussed. This additional stage
will perform the tasks of energy buffer and also perform the
complementary balancing of the dc voltages. In order to do so, a
dc–dc stage with access to both of the dc buses must be included,
to avoid having two batteries in the system, as shown in Fig. 1. To
meet this purpose, a three-level dc–dc stage will be featured. A
control scheme is developed and proposed, covering the partial
2377
Fig. 2. Circuit diagram for the three-level dc–dc stage for the ESS.
TABLE I
THREE-LEVEL DC–DC SWITCHING STATES
States Switching Output Neutral
Voltage Current
v0 [OO] 0 iz k = 0
v1 P [PO] Vd 1 iz k < 0
v1 N [ON] Vd 2 iz k > 0
v2 [PN] 2V d iz k = 0
and full balancing tasks. The overall performance of the system
will be validated both in simulation and experimentally.
II. THREE-LEVEL DC–DC STAGE FOR ESS
As stated earlier, in order to perform the balancing com-
plement to the grid-tied converter, the ESS must have access to
both dc buses. Considering this requirement, a three-level dc–dc
converter will be used as the dc–dc stage. This choice is further
justified by the reduced voltage stress on the switching devices,
allowing the use of conventional low-voltage-rated switches,
improved output current waveform, and improved efficiency
in comparison to conventional two-level-based topologies [25].
Finally, for this particular application, it will only require the
inclusion of a single energy storage stage, enabling the com-
pensation of the currents in both of the dc buses, as it will be
demonstrated in the following sections.
The power circuit of the selected topology is presented in
Fig. 2, where it can be seen that it has three input terminals that
can be directly connected to the bipolar charging station. The
converter is composed of four switching devices along with their
corresponding freewheeling diodes, the input filter capacitors
Cd1 and Cd2 , and an output inductor Lo and capacitor Co for
filtering purposes.
Considering its structure, the basic requirement that Vd1 =
Vd2 = Vd , and the valid combinations of its switching signals,
the converter generates four voltage states, which are resumed
in Table I. Each state results in a different equivalent circuit, as
presented in Fig. 3. These states are depicted as follows: when
the switches Sk 1 and Sk 4 are turned ON, the output voltage vo
is equal to the total input voltage 2Vd ; then when Sk 1 and Sk 3
are ON, vo becomes Vd ; the same output voltage is generated
when the switches that are ON are Sk 2 and Sk 4 ; finally, when the
inner switches Sk 2 and Sk 3 are turned ON, the output voltage is
2378 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 3. Four switching states and their equivalent circuits. (a) v 0 . (b) v 1 P .
(c) v 1 N . (d) v 2 .

equal to zero. Please note that the switching states v1P and v1N
generate opposite neutral-point currents, revealing the balancing
capabilities of the converter. For the remainder of the paper,
these states will be denominated mid states.

A. Operation Principle
From the circuit diagram in Fig. 2, the operation of the outer
switches Sk 1 and Sk 4 must be complementary to the inner
switches Sk 2 and Sk 3 , respectively, in order to avoid short cir-
cuiting the input voltage sources. This means that the operation
of the converter is regulated through two independent gating
signals g1 and g4 . The generation of these signals is usually
done by the use of pulse width modulation modulators with
phase-shifted carriers [25], [26]. However, taking into account
the generated switching sequence, it can also be synthesized by
a single-phase space vector modulation (SVM) approach. The
sequence will vary whether d ≤ 0.5 and d > 0.5. This will be
covered in detail in the following sections.
1) Small Duty Cycle: To start the analysis, the average value
of the output voltage is given by
 Ts
1
Vo = vo (τ )dτ (1)
Ts 0
this is the voltage that is being applied to the terminals of the
Fig. 4. Five segment switching sequence for SVM. (a) Small duty cycle
ESS. Then, by assuming that this voltage results in d ≤ 0.5, the d ≤ 0.5. (b) Large duty cycle d > 0.5.
required reference that synthesizes it is defined as:
1 The previous result reflects that during normal balanced op-
Vo = (tp v1P + tn v1N + to v0 ) (2)
Ts eration, the duty cycles for the outer switches are equal to d, as
where tp , tn , and to represent the dwell times of each state. the voltages Vd1 and Vd2 are balanced. Then, in the presence of
Whereas, the duty cycle d is defined as usual, by the ratio different dc voltages, the duty cycles dp and dn will be redis-
between the output and input voltages, according to tributed accordingly, in order to retrieve the balance condition.
This results in the five segment sequence for the SVM principle
Vo shown in Fig. 4(a).
d= . (3)
2Vd 2) Large duty cycle: Now, if the output voltage is larger
Now, considering the output voltages of Table I and replacing than Vd , the sequence varies as follows. In this case, the output
(2) into (3) leads to the following expression: voltage is synthesized by
dp Vd1 + dn Vd2 1
d= (4) Vo = (tp v1P + tn v1N + to v2 ) (6)
2Vd Ts
tk
dk = , where k = (p, o, n). (5) furthermore, regardless the relationship between Vd1 and Vd2 ,
Ts
the duty cycle for v2 is equal to
Please note that the duty cycles dp , do , and dn have been
introduced. do = 2d − 1. (7)
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING
Fig. 5. Critical load ratio for the NPC using SVM.
Finally, replacing (7) into (6) and clearing the total duty cycle
leads to
dp Vd1 + dn Vd2
d=1− . (8)
2Vd
The previous operation mode is illustrated in Fig. 4(b). An
important remark from the operating conditions displayed in
Fig. 4, is the confirmation that the redundancies of the state
v1 generates opposite currents circulating through the neutral
point iz k . When the positive redundancy is employed, a negative
average current flows through the neutral point, while a positive
average value for iz k is imposed when v1N is used. This concept
will be used to develop the balancing scheme employed in this
paper.
III. VOLTAGE BALANCING TECHNIQUE
As established in [17], in order to achieve dc voltages bal-
ance, the asymmetrical operation of the bipolar dc bus requires
a minimal power ratio between the dc buses, which is deter-
mined by the grid-side modulation stage. The motivation of this
paper is to use the ESS to perform the balancing tasks when the
system is driven out of its balanced zone, which is displayed
in Fig. 5. However, the fundamental difference with the afore-
mentioned approach is that the minimal load condition is no
longer emulated, as the ESS remains connected to the system
permanently. Instead, this approach allows to redistribute the
ESS power consumption in order to satisfy this minimal power
ratio , by concentrating it to the bus with lighter load. The
complete analysis is given in the following sections.
A. Small Duty Cycle
For the first case, it is necessary to revisit the example pre-
sented in Fig. 4(a), and assume there is no load connected to the
upper bus, while the lower one is operating under rated condi-
tion. The work in [17] demonstrated that in order to keep the
dc voltages from drifting, the following condition must be met
under any scenario
min{Pd1 , Pd2 } ≥  max{Pd1 , Pd2 } (9)
where, Pd1 and Pd2 are the power consumed at the upper and
lower dc bus, respectively. Now, as stated earlier, the imbalance
will be compensated by redistributing the usage of the mid
2379
states. This will allow to select which bus is providing power
to the ESS. Given that the redistribution is done in such a way
that the positive bar current ipk must be equal to Id2 . From
Fig. 4(a), it can be deducted that this current is related with the
output current io according to
ipk = dp io . (10)
Additionally, assume that in order to meet the minimal load
condition, the output current is such as it requires to exclusively
use the positive redundancy of v1 . This leads to dp = 2d, and
bearing in mind the previous analysis, the minimal value for io
that allows to meet the balancing condition is defined as
Id2
io = . (11)
2d
This is an interesting result, as it demonstrates that in order to
guarantee a balanced operation of a system rated at Pb , it will
only require an ESS with a power equivalent to Pb /(2 + ).
Moreover, it is worth mentioning that despite the redistribution
that the modulator is performing, for this duty cycle range the
power delivered to the ESS remains unaltered.
In the case the imbalance is located in the lower dc bus, the
procedure is analogous, as the ESS requires to drain at least a
current defined by
Id1
io = (12)
2d
while employing exclusively the mid-state v1N .
B. Large Duty Cycle
Despite the balancing principle is the same for different
modulation index ranges, the generated compensation current
changes, as it will be demonstrated. Using the example provided
by Fig. 4(b), and again assuming the imbalance location is the
upper bus, the required value for ipk to achieve the dc voltage
balance is still set by (9), hence must be equal to Id2 . The rela-
tionship between this current and io remains modeled by (10),
and since the positive redundancy is being exclusively used, the
required output current is now defined as
Id2
io = . (13)
2(1 − d)
It is demonstrated then, that for large duty cycles, the mini-
mal ESS that is able to keep the system balanced under any load
scenario is given by dPb /(2 − 2d). In other words, in this duty
cycle range, the ESS required to maintain the system balanced
has higher power ratings. In case of having the imbalance lo-
cated in the lower bus, the formulas must change accordingly,
assuming that only v1N is being used.
IV. PROPOSED CONTROL SCHEME
Given that the ESS remains as a stationary load to the sys-
tem, it can drain power from any of the buses arbitrarily. This
means that its usage can be maximized, as its charging pro-
cess can be used to compensate the imbalances in the system.
Consequently, there is no need to modify the overall structure
of the grid-side controller presented in Fig. 6, which performs
2380
Fig. 6. VOC block diagram for the central NPC converter.
the regulation of the central NPC converter. However, in or-
der to overcome the generation of even-order harmonics during
unbalanced operation, a change is introduced in the switching
sequence employed.
A. Modified Sequence During Unbalanced Operation
Considering the results obtained in [17], the main drawback of
the control scheme was the presence of even-order harmonics in
the line current during asymmetrical load operation, because the
half-wave symmetry was missed. This is not desirable for grid-
connected systems as the grid code sets stringent limits for these
particular components, thus it has to be solved. Therefore, the
SVM switching sequence for the central NPC will be modified
during these instants in order to retrieve the half-wave symmetry
and guarantee line currents without even-order harmonics.
Is important to note that the dwell times for positive and
negative small vectors are redistributed according the dc voltage
deviations, using a PI controller to maintain the balance. To do
so, the controller actuation Δs is fed to the SVM modulator to
adjust the dwell times according to
ta ta
taP = (1 − Δs ), taN = (1 + Δs ). (14)
2 2
Considering the voltage references of the scenario given by
1 any way, generating the required duty cycle value d to regulate
vref = (ta v1 + tb v2 + tc v7 ) (15)
Ts
1
vref = (ta v4 + tb v5 + tc v10 ) (16)
Ts
and in the presence of an imbalance at the dc side that results in
Δs = −1/3. This will lead to ta P = 2ta N , and the resulting se-
quences are shown in Fig. 7. It becomes clear that the balancing
mechanism has altered the switching sequence, causing a lack
of half-wave symmetry in the line-to-line voltages. This yields
to the appearance of even-order harmonics on the line currents.
As the dwell-times redistribution is necessary to achieve bal-
ance on the dc voltages, a modification on the switching se-
quence is proposed to maintain the symmetry, and it will only be
used when the dc loads are different. This modification is simply
to swap the position of the negative and positive vectors in one
of the sequences, in order to retrieve the half-wave symmetry.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017
Fig. 7. SVM switching sequences during unbalanced operation. (a) Switching
sequence for region I-2a. (b) Switching sequence for region IV-2a. (c) Modified
sequence for region IV-2a.
In the studied case, the type B sequence is modified by swapping
v4P and v4N . It’s important to note that the condition of changing
only two switches per segment is missed due the swapping of the
small vectors. This leads to the switching sequence presented in
Fig. 7(c) for the region IV-2a. Fig. 7 shows that the symmetry
in the line-to-line voltages has been retrieved, however, this is
done at the expenses of increasing the number of switchings per
sampling period.
B. ESS Controller
Now, for the regulation of the ESS, the following operation
principle is proposed: the ESS controller will not be modified in
its voltage following its prescribed charging profile; then, de-
pending on the location of the imbalance, the dc–dc stage will
redistribute the usage of the mid states, in such a way that it
will drain the minimal current from the less congested bus. This
redistribution is entirely related with the usage of the small vec-
tors of the central stage controller, thus the same actuation Δs
can be used for this purpose. In addition, in order to minimize
the required ESS power ratings, the ESS voltage is selected to
be lower than Vd , leading to d ≤ 0.5.
The required controller for the ESS is the one presented in
Fig. 8, and it confirms that the controller for the ESS is the
conventional cascaded loop that depending on its SOC operates
in constant current or constant voltage modes. This structure
generates the required d, and the modulator stage performs the
redistribution of the states, using the information provided by
the mid-point controller. This modification is applied to the duty
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2381

Fig. 8. Proposed controller for the balancing ESS.

TABLE II
SIMULATION AND EXPERIMENTAL PARAMETERS

Parameter Symbol Value

Grid Voltage Amplitude Vg 1 p.u.

Grid Frequency fg 1 p.u. Fig. 9. Dynamic performance of the dc currents. (a) Neutral-point current iz k
Input Filter Inductance Lg 0.1 p.u. and its average value Iz k . (b) Bus 1 current Id 1 . (c) Bus 2 current Id 2 .
Input Filter Resistance Rg 0.02 p.u.
dc Link Capacitance Cd 4.5 p.u.
dc Link Voltage 2V d 2.2117 p.u.
Output Filter Inductance Lo 0.18 p.u.
Output Filter Capacitance Co 1.8 p.u.
ESS Rated Power P ss 0.1402 p.u.
ESS Capacitance C ss 1.1 × 10 5 p.u.
Amplitude Modulation Index m 0.6433
Frequency Modulation Index mf 36
Critical Load Ratio ˆ 0.2823
Simulation Base Voltage VB 4160/960 V
Simulation Base Power PB 1.38 MW
Experimental Base Voltage VB 208 V
Experimental Base Power PB 3 kW
Base Frequency fB 60 Hz

cycles dp and dn according to

dp = d(1 + Δs ) (17) Fig. 10. Dynamic performance of the VOC signals. (a) DC bus voltages V d 1
and V d 2 . (b) Grid current ig a . (c) Grid voltage v g a .
dn = d(1 − Δs ). (18)

V. SIMULATION RESULTS
Considering the proposed compensation technique to keep
the dc-link voltages balanced, the dynamic performance of the
system is validated under several load impacts, simulating the
random arrival of vehicles for recharge. In addition, the pro-
posed switching sequence correction is performed in order to
keep the ac-side currents without even-order harmonics. The
simulation parameters are presented in Table II. A 1.38-MW
charging station is simulated using MATLAB/Simulink.
A. Dynamic Performance
The study of the dynamic performance in the presence of
severe load impacts is the first stage of validation. As men-
tioned earlier, this is to simulate the volatile loads that the EVs
represent in the system due to their random arrival, different
battery technologies, charging speeds, initial SOCs and so on.
Fig. 9 exhibits the dynamic evolution of the dc currents in the
system. It is possible to see that before t = 0.05 s, the system
is operating with symmetrical dc loads, as Id1 = Id2 , hence,
there is no need to generate any current compensation with the
balancing ESS. As there is no need for redistributing the usage
of the mid states, the average value of iz k is zero, while the ESS
continues its charging process. Then, at the instant when the first
load impact takes place, the current Id2 goes to zero, and in order
to keep the voltages from drifting, the system forces the power
demand to be exclusively from the lower bus. This is confirmed
by the positive average value of iz k . Furthermore, Id1 remains
unaltered, thus demonstrating the independent operation of the
dc buses.
Later on, the asymmetrical operation is reversed at t =
0.13̄ s, by disconnecting the load in bus 1 and reconnecting
the rated load to bus 2. It becomes clear how the polarity of the
current in the neutral point has changed, as only the positive
redundancy of the mid state is being used.
Finally, when the system returns to balanced operation at
t = 0.216̄ s, there is no need for compensation actions from
the ESS, so the distribution of the mid states is done equally,
resulting in zero average current flowing through the midpoint.
A remarkable fact from the proposed method is the reduced
current stress in the output dc choke, as the ESS power rating is
merely 14% of the rated power of the station.
The proper regulation performed at the dc side, allows to keep
the voltages perfectly balanced throughout the entire simulation.
This situation is confirmed by Fig. 10(a) which shows how the
voltage of the dc capacitors remains tracking their reference.
It is possible to confirm that the proposed balancing technique
allows to overcome the limitations of the conventional NPC.
2382 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 11. Steady-state analysis of the converter voltages. (i) Line-to-line voltage Fig. 12. Steady-state analysis of the input signals. (i) Grid voltage v g a .
v a b . (ii) Phase voltage v a z . (iii) FFT for v a z . (a) Case I, balanced operation. (ii) Grid current ig a . (iii) FFT for ig a . (a) Case I, balanced operation. (b)
(b) Case II, unbalanced operation in bus 2. Case II, unbalanced operation in bus 2.

As the balancing technique allows to keep the dc voltage

balance, the currents at the input side exhibit a sinusoidal wave-
form during any scenario, as shown in the waveform of ig a in
Fig. 10(b). Finally, the unity power factor operation remains
unaltered during the load impacts, as the currents are kept in
phase with the grid voltage vg a plotted in Fig. 10(c).

B. Steady-State Analysis
Continuing with the validation of the proposed balancing
scheme, the steady-state waveforms of the converter voltages
are discussed. Fig. 11 presents these waveforms for the balanced
and unbalanced cases.
The behavior of the system for symmetrical operation can be
seen in Fig. 11(a), where it is possible to see there are no cor-
rections being applied to either of the voltage signals, as there
is no difference between the dc loads. The generated voltages
presents half-wave symmetry, leading to a spectral distribution
that has no even-order harmonics as shown in the fast Fourier
transform (FFT) for vaz . Then, under the presence of an imbal-
Fig. 13. Experimental setup. (a) Photograph. (b) Block diagram.
ance, a dc drift is injected to the phase voltage with balancing
purposes, which results in a positive dc drift due the lack of
load in the lower bus, as presented in Fig. 11(b)ii. The modifica- cycles of the converter phase voltages, which is confirmed by
tion of the switching sequence for the asymmetrical operation the presence of even-order components in Fig. 11(b)iii.
can be also appreciated, as vaz exhibits six extra switchings per Just as in the previous method, the dc bias injected to vaz is
fundamental cycle. not reflected toward the line-to-line voltages, as the three phases
The presence of this dc drift is confirmed by the spectrum of are modified equally. This is confirmed by Fig. 11(a)i and (b)i.
vaz in Fig. 11(b)iii. In addition, the dc voltage injection has led To complete the analysis, the input signals are presented in
to a lack of symmetry between the positive and negative half Fig. 12 for steady-state regimen. The input current ig a exhibits
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING
Fig. 14. Dynamic performance, Case I. (a) DC currents. ChM Neutral-point
current average value Iz k (4 A/div). Ch2 Neutral-point current iz k (5 A/div).
Ch3 Bus 1 load current Id 1 (5 A/div). Ch4 Bus 2 load current Id 2 (5 A/div).
(b) VOC signals. Ch1 dc bus 1 voltage V d 1 (100 V/div). Ch2 dc bus 2 voltage
V d 2 (100 V/div). Ch3 Grid current ig a (14.8 A/div). Ch4 Grid voltage v g a
(200 V/div). Time scale 30 ms/div.
a sinusoidal nature for both balanced and unbalanced cases,
with the corresponding increase in its ripple in the unbalanced
operation. However, the effectiveness of the modified switching
frequency is confirmed, as the currents have maintained the
half-wave symmetry. This is further confirmed by its harmonic
content, presented by Fig. 12(b)iii, as it does not contain energy
concentrated in even-order components.
VI. EXPERIMENTAL VALIDATION
The final step to demonstrate the effectiveness and validate
the proposed balancing approach is through experimental ver-
ification. In order to do so, the NPC prototype exhibited in
Fig. 13(a) is employed.
The experimental platform is composed by an isolation trans-
former, an inductive input filter, and the central NPC converter
in the ac side, while the dc side has the IGBT-based three-level
dc–dc stage feeding an ultra capacitor ESS, and the resistive
loads for each bus, both of them connected through a solid-state
relay in order to force the asymmetrical operation. The control
platform used is an eZdsp (TMS320F28335) from Spectrum
Digital, which is performing the main calculations and control
actions, along with an Altera Cyclone FPGA (EP1C6T144C8)
2383
Fig. 15. Dynamic performance, Case II. (a) DC currents. ChM Neutral-point
current average value Iz k (4 A/div). Ch2 Neutral-point current iz k (5 A/div).
Ch3 Bus 1 load current Id 1 (5 A/div). Ch4 Bus 2 load current Id 2 (5 A/div).
(b) VOC signals. Ch1 dc bus 1 voltage V d 1 (100 V/div). Ch2 dc bus 2 voltage
V d 2 (100 V/div). Ch3 Grid current ig a (14.8 A/div). Ch4 Grid voltage v g a
(200 V/div). Time scale 30 ms/div.
to manage peripherals and protections. In this case, the SVM
algorithm is programmed to have an equivalent switching fre-
quency of 1080 Hz per device. Using the parameters presented
in Table II, the control scheme is applied to the converter.
To validate the approach, the same dynamic test of the sim-
ulations is performed. The ESS employed in the experimental
platform is a 845.64 Wh ultra capacitor stage Css , with a rated
voltage of 64.8 V. This stage is composed by the series connec-
tion of four Maxwell ultra capacitor modules (BMOD0058 E016
B02), each one with a capacitance of 58 F and rated for 16.2 V.
The experimental setup diagram is presented in Fig. 13(b).
A. Dynamic Performance
The obtained results are displayed on Fig. 14. It is possible to
observe a close similarity with the simulation results obtained
earlier. Fig. 14(a) puts on display the behavior of the dc currents
during the whole test. It’s important to remind that the ESS is
performing its charging tasks during the whole scenario. As the
system starts in balanced operation, there is no current com-
pensation required from the ESS stage, therefore, it is draining
power equally from both dc buses, as it can be seen by the
average neutral-point current Iz k , which is zero. Later on, as
2384
Fig. 16. Dynamic performance of the ESS. Ch1 ESS input current io (5 A/div). Ch2 ESS input voltage v o (200 V/div). Time scale 30 ms/div. (a) Case I.
(b) Case II.
soon as the load from the lower dc bus is disconnected (Id2 is
set to zero), it changes to a positive value in order to keep the
dc voltages from drifting. Consequently, when the imbalance is
reversed (Id1 is now zero), it will change its direction in order
to reach the minimal load condition. Finally, when the system
returns to balanced regiment, the current compensation is no
longer required and Iz k returns to zero.
As a continuation of the analysis, the evolution of the quan-
tities related with the grid-tied regulation are presented in
Fig. 14(b). Once again, it can be seen how the severe asymmetri-
cal operation is overcome by forcing the minimal load condition
at the dc side. The dc bus voltages show an improved dynamic
response, returning quickly to their reference. This leads to a
balanced operation during the whole test allowing to maintain
a proper regulation of the input current ig a , which exhibits a
highly sinusoidal waveform, and does not distort excessively
maintaining its phase disposition with the grid voltage, hence,
keeping the unity power factor operation.
In order to further validate this balancing approach a different
dynamic test is performed. This time, the system will be assumed
without any EV load connected to either bus, while the ESS is
performing its charging process. Then, the maximum imbalance
is forced in the negative bus. This is followed by the system
returning to the no EV state, and finally, the maximum imbalance
is forced toward the positive bus. This is done in order to have
a more realistic scenario, and at the same time force the worst
case operation, which is when one of the buses is fully loaded
and the remaining one has no load connected. Any other power
difference between the power consumptions on the buses is a
less challenging balancing scenario.
Fig. 15 presents the evolution of the relevant quantities during
the second test. The dc currents exhibited in Fig. 15(a) allows
to confirm the effectiveness of the method, and the converter
redistributes the power consumption of the ESS toward the bus
that has the lighter load condition. Following this idea, the av-
erage value of iz k is positive to compensate imbalances in the
upper dc bus, meanwhile a negative average value will do the
same for imbalances located in the lower dc bus.
The quantities related with the grid-connected converter, pre-
sented in Fig. 15(b), confirms the validity of the balancing
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017
Fig. 17. Dynamic performance of the ESS. Ch1 ESS input current io
(5 A/div). Ch2 ESS input voltage v o (200 V/div). (c) Ch3 Ultra Capacitor
Voltage V o (10 V/div). Time scale 6 s/div.
assistance, as the dc voltages remain balanced regardless the
load condition. It is important to recall that the ESS is charging
during the whole time, explaining why the ac currents are not
zero during the instants when no EVs are demanding power
from the station. An important detail in this figure is the graph-
ical confirmation of the reduced requirement on the ESS power
rating to achieve balance. It can be seen that is roughly one-sixth
of the total power.
Please note that despite the ESS interface is able to redis-
tribute its power consumption and provide the complementary
balancing capability, its main function and raison d’être is still
charge or discharge the energy buffer according to the energy
management strategy. To highlight this issue, Fig. 16 provides
the evolution of the current injected to the ESS io and the volt-
age generated by the dc–dc stage vo during the aforementioned
tests. It becomes clear that these outputs remain almost unaltered
during the whole dynamic test, with the exception of a slight in-
crease in the current ripple during the unbalanced instants. The
reason for this increased ripple is the exclusive use of one of
the redundancies of the mid state, as it will lead to a reduction
of the apparent switching frequency (the switching sequence
has only three segments in this case). This results demonstrate
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING
Fig. 18. Steady-state analysis of the converter voltages. Ch1 phase voltage
v a z (200 V/div). Ch2 line-to-line voltage v a b (500 V/div). ChM FFT for v a z
(20 V/div, Span 10 kHz, Center 4.8 kHz). (a) Balanced operation. (b) Unbalanced
operation in bus 2. Time scale 3.4 ms/div.
that is possible to integrate the operation of the ESS with the
complementary balancing required by the grid-tied converter.
Finally, aiming to display the charging process of the ultra
capacitor, Fig. 17 presents its voltage Vo along with the output
signals of the dc–dc stage io and vo during a 60 s window. In the
figure, it is possible to confirm the ESS is charging and it is not
disturbed dramatically by the forced imbalance of the different
scenarios. Given the considerable difference between the time
constants of the ESS charging and the electrical variables, this
voltage is not shown during the dynamic scenarios as it virtually
does not experience any noticeable changes during that time
window.
B. Steady-State Analysis
Finally the results in steady state are analyzed in order to
complete the validation of the balancing approach, which are
displayed on Figs. 18 and 19. As it could be expected, the con-
verter voltages during the symmetrical operation from Fig. 18(a)
do not present major differences with conventional operation of
the NPC, as the modification of the switching sequence only
takes place during the unbalanced operation. This is confirmed
by the waveforms in Fig. 18(b), as the effort to maintain the
symmetry of the line to line voltages is reflected in extra switch-
ings in the negative half cycle of vaz . Then, vab retrieves the
2385
Fig. 19. Steady-state analysis of the input signals. Ch3 grid current ig a
(10 A/div). Ch4 grid voltage v g a (200 V/div). ChM FFT for ig a (100 mA/div,
Span 10 kHz, Center 4.8 kHz). (a) Balanced operation. (b) Unbalanced operation
in bus 2. Time scale 3.4 ms/div.
half-wave symmetry as expected, leading to an input current
with no energy concentrated in even-order harmonics.
The effectiveness of the modified switching sequence can be
observed in Fig. 19(b), as even in the presence of asymmet-
rical dc loads, ig a has maintained its sinusoidal behavior and
retrieves its half-wave symmetry, which can be confirmed by
the exclusive presence of odd-order harmonics in its spectrum.
It’s important to keep in account that the balancing actions
performed by the central converter results in a reduction of
the apparent switching frequency on the line-to-line voltages,
as it can be appreciated in the cases of Fig. 18, which ex-
plains the shifting of input current dominant harmonics to lower
frequencies.
VII. CONCLUSION
A different complementary balancing approach has been de-
veloped and successfully validated, which takes advantages
from the optional stages that the distributed dc bus architec-
ture allows. In this case, the presence of an energy storage
stage, interfaced with a three-level dc–dc converter, allows the
elimination of the balancing leg and provide the supplementary
balancing ability required. This leads to a reduction in the over-
all cost of the charging architecture, as the requirements for the
rectifier stage has been reduced, allowing to use off-the-shelf
equipment.
2386
Is important to highlight that despite the ESS converter is pro-
viding the additional balancing ability, this does not alter dra-
matically its operation, allowing to keep its main function which
is the charging and discharging of the energy buffer according
to the selected energy management strategy. Furthermore, given
the features of the three-level dc–dc converter, the minimal load
condition does not impose a heavy restriction on the ESS siz-
ing, which means that its ratings are still set by the selected
energy management approach. Experimental results using an
ultracapacitor stage have been carried out for the validation of
the method, but the concept can be extended to different kinds
of ESSs.
Similar to the balancing method presented in [17], the pro-
posed solution allows to keep high-quality input signals, even
under the presence of severe imbalances at the dc side. In addi-
tion, the alternate switching sequence allows to perform the
complementary balancing while keeping the current free of
even-order harmonics.
REFERENCES
[1] D. Block, J. Harrison, and P. Brooker, “Electric vehicle sales for 2014 and
future projections,” Elect. Veh. Transp. Center, Tech., Washington, DC,
USA, Rep. FSEC-CR-1998-15, Mar. 2015.
[2] International Energy Agency. Hybrid and electric vehicles annual report.
2015. [Online]. Available: http://www.ieahev.org, accessed on May. 2015.
[3] D. Aggeler, F. Canales, H. Zelaya-De La Parra, A. Coccia, N. Butcher, and
O. Apeldoorn, “Ultra-fast DC-charge infrastructures for EV-mobility and
future smart grids,” in Proc. IEEE PES Innov. Smart Grid Technol. Eur.,
Gothenburg, Sweden, Oct. 2010, pp. 1–8.
[4] M. Yilmaz and P. Krein, “Review of battery charger topologies, charging
power levels, and infrastructure for plug-in electric and hybrid vehicles,”
IEEE Trans. Power Electron., vol. 28, no. 5, pp. 2151–2169, May 2013.
[5] S. Bai and S. Lukic, “Unified active filter and energy storage system for an
MW electric vehicle charging station,” IEEE Trans. Power Electron., vol.
28, no. 12, pp. 5793–5803, Dec. 2013.
[6] L. Dickerman and J. Harrison, “A new car, a new grid,” IEEE Power Energy
Mag., vol. 8, no. 2, pp. 55–61, Mar./Apr. 2010.
[7] V. Silva and C. Kieny, “Impacts of EV on power systems and minimal
control solutions to mitigate these,” Essen, Germany: RWE Deutschland
AG, May 2011, [Online]. Available: http://www.g4v.eu/downloads.html.
[8] J. T. Salihi, “Energy requirements for electric cars and their impact on
electric power generation and distribution systems,” IEEE Trans. Ind. Appl.,
vol. IA-9, no. 5, pp. 516–532, Sep. 1973.
[9] J. Gomez and M. Morcos, “Impact of EV battery chargers on the power
quality of distribution systems,” IEEE Trans. Power Del., vol. 18, no. 3, pp.
975–981, Jul. 2003.
[10] K. Qian, C. Zhou, M. Allan, and Y. Yuan, “Modeling of load demand due
to EV battery charging in distribution systems,” IEEE Trans. Power Syst.,
vol. 26, no. 2, pp. 802–810, May 2011.
[11] J. Sexauer, K. McBee, and K. Bloch, “Applications of probability
model to analyze the effects of electric vehicle chargers on distribution
transformers,” IEEE Trans. Power Syst., vol. 28, no. 2, pp. 847–854,
May 2013.
[12] P. Fan, B. Sainbayar, and S. Ren, “Operation analysis of fast charging
stations with energy demand control of electric vehicles,” IEEE Trans.
Smart Grid, vol. 6, no. 4, pp. 1819–1826, Jul. 2015.
[13] N. Machiels, N. Leemput, F. Geth, J. Van Roy, J. Buscher, and
J. Driesen, “Design criteria for electric vehicle fast charge infrastructure
based on flemish mobility behavior,” IEEE Trans. Smart Grid, vol. 5, no. 1,
pp. 320–327, Jan. 2014.
[14] J. Tant, F. Geth, D. Six, P. Tant, and J. Driesen, “Multiobjective battery
storage to improve pv integration in residential distribution grids,” IEEE
Trans. Sustainable Energy, vol. 4, no. 1, pp. 182–191, Jan. 2013.
[15] International Energy Agency, “Hybrid and electric vehicles annual report,”
2011. [Online]. Available: http://www.ieahev.org, accessed on Mar. 2015.
[16] S. Bae and A. Kwasinski, “Spatial and temporal model of electric vehicle
charging demand,” IEEE Trans. Smart Grid, vol. 3, no. 1, pp. 394–403,
Mar. 2012.
View publication stats
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017
[17] S. Rivera, B. Wu, S. Kouro, V. Yaramasu, and J. Wang, “Electric vehicle
charging station using a neutral point clamped converter with bipolar DC
bus,” IEEE Trans. Ind. Electron., vol. 62, no. 4, pp. 1999–2009, Apr. 2015.
[18] ABB. (Mar. 2015). [Online]. Available: http://new.abb.com/ev-charging.
[19] Blink. (Mar. 2015). [Online]. Available: http://www.blinknetwork.com/
chargers-commercial-dc-fast.
[20] Schneider-Electric. (Mar. 2015). [Online]. Available: http://www.
schneider-electric.com/.
[21] A. Sannino, G. Postiglione, and M. Bollen, “Feasibility of a DC net-
work for commercial facilities,” IEEE Trans. Ind. Appl., vol. 39, no. 5,
pp. 1499–1507, Sep./Oct. 2003.
[22] Y. Ito, Y. Zhongqing, and H. Akagi, “DC micro-grid based distribution
power generation system,” in Proc. IEEE Int. Power Electron. Motion Con-
trol Conf., Xian, China, Aug. 2004, vol. 3, pp. 1740–1745.
[23] J. Rodriguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, “Multilevel voltage-
source-converter topologies for industrial medium-voltage drives,” IEEE
Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007.
[24] S. Bai and S. Lukic, “New method to achieve ac harmonic elimination and
energy storage integration for 12-pulse diode rectifiers,” IEEE Trans. Ind.
Electron., vol. 60, no. 7, pp. 2547–2554, Jul. 2013.
[25] P. Grbović, P. Delarue, P. Le Moigne, and P. Bartholomeus, “A bidirec-
tional three-level dc-dc converter for the ultracapacitor applications,” IEEE
Trans. Ind. Electron., vol. 57, no. 10, pp. 3415–3430, Oct. 2010.
[26] L. Tan, B. Wu, S. Rivera, and V. Yaramasu, “Comprehensive dc power
balance management in high-power three-level dc-dc converter for elec-
tric vehicle fast charging,” IEEE Trans. Power Electron., vol. 31, no. 1,
pp. 89–100, Jan. 2016.
Sebastian Rivera (S’10–M’16) was born in Val-
paraiso, Chile, in 1986. He received the B.Sc. and
M.Sc. degrees in electronics engineering from Uni-
versidad Tecnica Federico Santa Maria, Valparaı́so,
Chile, in 2007 and 2011, respectively, and the Ph.D.
degree in electrical and computer engineering from
Ryerson University, Toronto, ON, Canada, in 2015.
He recently joined the University of Toronto, as a
Postdoctoral Fellow at the Laboratory for Advanced
Power Conversion and Systems Analysis. His re-
search interests include high-power multilevel con-
verters, renewable energy conversion systems, and electric vehicles.
Dr. Rivera received the Emerging Leaders in the Americas Program Schol-
arship from the Canadian Bureau for International Education in 2010, the Ph.D.
Scholarship from the Chilean National Commission for Scientific and Techno-
logical Research in 2011, and the 2014 Graduate Research Excellence Award
from Ryerson University.
Bin Wu (S’89–M’92–SM’99–F’08) received the
M.A.Sc. and Ph.D. degrees in electrical and com-
puter engineering from the University of Toronto,
ON, Canada, in 1989 and 1993, respectively.
In 1993, he joined Ryerson University, Toronto,
where he is currently a Professor and Senior
NSERC/Rockwell Automation Industrial Research
Chair in Power Electronics and Electric Drives. He
has published more than 350 technical papers, au-
thored/coauthored two Wiley-IEEE Press books, and
holds more than 30 issued/pending patents in the area
of power conversion, medium-voltage drives, and renewable energy systems.
Dr. Wu received the Gold Medal of the Governor General of Canada in 1993,
Premier’s Research Excellence Award in 2001, NSERC Synergy Award for
Innovation in 2002, Ryerson Distinguished Scholar Award in 2003, YSGS Out-
standing Contribution to Graduate Education Award, and Professional Engineers
Ontario Engineering Excellence Medal in 2014. He is a fellow of Engineering
Institute of Canada and Canadian Academy of Engineering.