DCIT

203
DIGITAL AND LOGIC SYSTEM DESIGN
SESSION 10 – CLASSIFICATION OF FSM/FSA

Lecturer: Dwumfour Abdullai Aziz

Email: adwumfour@ug.edu.gh
Mobile: 0260541219

UNIVERSITY OF GHANA
College of Education
College of Education
School
School ofofContinuing
Continuingandand Distance
Distance Education
Education
2022/2023
2014/2015 – 2016/2017
 CLASSIFICATIONS OF FINITE
STATE AUTOMATA

Dwumfour Abdullai Aziz Slide 2

 SESSION OVERVIEW

The session exposes student to the various

classification of FSM. It will focus on the model and
design principles of FSM with output. It will further
highlight on the use of Moore and Mealy Models of
computation. The design of synchronous sequential
circuit will be explored.

Dwumfour Abdullai Aziz Slide 3

 LEARNING OUTCOME
At the end of the session, the student should be able to:
q Understand the various classifications of FSM
q Understand the FSM with output
q Understand the Moore and Mealy Models of Computation
q Design Clock sequential circuit using Moore and Mealy
Models.
q Understand state reduction technique in designing
sequential circuit using FSM

Dwumfour Abdullai Aziz Slide 4

 SESSION OUTLINE

The key topics to be covered in the session include

q Classification of Finite State Machine with
Output
q Moore Model of computation
q Mealy Model of computation
q Design of Clock Sequential Circuit using
Mealy/ Moore Models

Dwumfour Abdullai Aziz Slide 5

 READING LIST

S. Salivahanan & S. Arivazhagan (2018), Digital Circuits and Design.

Dwumfour Abdullai Aziz Slide 6

FINITE STATE MACHINE

Dwumfour Abdullai Aziz Slide 7

 FINITE AUTOMATA WITH OUTPUT

❑ Finite State Automata may have outputs corresponding to

each transition.
❑ Synchronous Sequential circuits are developed based on
two types of models
• Mealy model/ Mealy state machine
• Moore mode/Moor state machine
❑ The difference lies in the way the output of the complete
circuit is generated

Dwumfour Abdullai Aziz Slide 8

 FINITE AUTOMATA WITH OUTPUT

❑ FSM with output is described by 6 tuples

(Q,q0,∑,O,δ,λ)
Q is finite set of states
q0 is the initial state

∑ is the input alphabet

O is the output alphabet

δ is transition function which maps Q×∑ → Q

‘λ’ is the output function which maps Q×∑→ O

Dwumfour Abdullai Aziz Slide 9
 Moore Computational Model

❑ A Moore machine is defined as a machine in theory of

computation whose output values are determined only by its
current state.
❑ In Moore machine, the output is associated with each state rather
than with the transitions.
❑ Moore machine is described by the 6 tuples above(Q,q0,∑,O,δ,λ)
– Q is finite set of states
– q0 is the initial state
– ∑ is the input alphabet

– O is the output alphabet

– δ is transition function which maps Q×∑ → Q

– ‘λ’ is the output function which maps Q→ OSlide 10

 Moore Model
Q={s0,s1,s2,s3}
q0= s0
∑={0,1}
O={0,1}
δ:{s0,1}->s1
{s0,0}->s0
{s1,1}->s2
{s1,0}->s0
{s3,1}->s3
{s2,0}->s0
{s3,1}->s3
{s3,0}->s0
λ:Q→O
s0->0 , s1->0
s2->0 , s3->1
Dwumfour Abdullai Aziz Slide 11
 Moore Model

• In the Moore Model , a combinational logic block

maps the inputs and the current state into the
necessary flip-flop inputs to store the appropriate
next state.
• The outputs are computed by a combinational logic
block whose only inputs are the flip-flops' state
outputs.
• The outputs change synchronously with the state
transition and the clock edge.

Dwumfour Abdullai Aziz Slide 12

Moore Model

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Moore Machine

Dwumfour Abdullai Aziz Slide 14

Clocked Sequential Circuit of Moore Machine

Dwumfour Abdullai Aziz Slide 15

 Moore Model: Features

Moore machines are characterized by;

❑ The Output depends only on current state.
❑ More number of states are required.

❑ There is less hardware requirement for circuit

implementation.

❑ They react slower to inputs(One clock cycle later).

❑ Synchronous output and state generation.
❑ Output is associated with the states.
Dwumfour Abdullai Aziz Slide 16
 Mealy Computational Model

❑ A mealy machine is defined as a machine in theory of computation

whose output values are determined by both its current state and
current inputs.
❑ In mealy machine, the output is given along the edge with input
symbol
❑ Mealy machine is described by the 6 tuples above(Q,q0,∑,O,δ,λ)
– Q is finite set of states
– q0 is the initial state
– ∑ is the input alphabet

– O is the output alphabet

– δ is transition function which maps δ: Q×∑ → Q

– ‘λ’ is the output function which maps λ : Q ×∑ → O

 Mealy Model
Q={s0,s1,s2}
q0= s0
∑={0,1}
O={0,1}
δ:{s0,1}->s1
{s0,0}->s2
{s1,1}->s1
{s1,0}->s2
{s2,1}->s1
{s2,0}->s2
λ:Q×∑ → O
{s0,1}->0, {s0,0}->0
{s1,1}->1,{s1,0}->1
{s2,1}->0, {s2,0}->0

Dwumfour Abdullai Aziz Slide 18

Mealy machine

Dwumfour Abdullai Aziz Slide 19

Clocked Sequential circuit of Mealy Machine

Dwumfour Abdullai Aziz Slide 20

Clocked Sequential Circuit of Mealy Machine

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Summary of Moore vs Mealy state diagram

❑ In Moore machines, the output is associated with the states

❑ In Mealy machines the output is associated with the
transitions
❑ Moore machines have more states than equivalent Mealy
machine
❑ Mealy machines (generally) have less states. Mealy
machines change their output based on their current
input and present state, rather than just the present state.
❑ However, less states doesn't always mean simpler to
implement.

Dwumfour Abdullai Aziz Slide 22

 Summary of Moore vs Mealy state diagram
❑ Moore machines may be safer to use, because they
change states on the clock edge
❑ Mealy machines are faster, because the state is
dependent on the input. Thus, the state can change
asynchronously. This comes down to predictability vs
raw speed.
❑ When it comes down to it, it's difficult to draw hard
lines where one machine would always be better than
the other.

Dwumfour Abdullai Aziz Slide 23

 Which Machine is best???
Moore vs Mealy
❑ It really comes down to the specific task at hand. Does one
want to have a synchronous or asynchronous machine? Is
speed paramount? Will there be potential unstable
(bouncing) signals? Are both the inputs and present state
readily available? The answer to each of these questions
determines the type of machine that would work best.
❑ It's worth mentioning that for a hardware implementation,
Mealy machines require less hardware in their circuits, but
when working with an HDL and RTL scenario, the actual
amount of discrete hardware may not be terribly important

Dwumfour Abdullai Aziz Slide 24

Design of Synchronous Sequential Circuit

Step 1 :The behavior of circuit is given through the State

diagram or timing diagram
Step 2: Obtain the state table from the state diagram
Step 3: Perform state reduction if possible
Step 4:Perform state assignment
Step 5: Determine number of flip flops and assign letters
Step 6: Decide on the type of flip flop to use
Step 7: Derive circuit excitation table from state table
Step 8: Obtain Boolean expression for flip flop input and circuit
output
Step 9: Implement circuit diagram
Dwumfour Abdullai Aziz Slide 25
Design a Clock Sequential circuit
for the state diagram below
Step 1: state diagram is given
0/0
1/1 0/1
00 10

0/0
1/0

01 11
1/0 0/0
1/0

Dwumfour Abdullai Aziz Slide 26

 Step 2: Obtain the state table
PRESENT STATE NEXT STATE OUTPUT (Z)
X=0 X=1 X=0 X=1
QA QB Q+A Q+B Q+A Q+B

0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 1
1 1 1 0 1 1 0 0

Dwumfour Abdullai Aziz Slide 27

 Step 3: perform state reduction
• No state reduction is required since no redundant state
occurs.

Step 4: perform state assignment if required

A=00 The states are already assigned binary values
from the state diagram hence no need for state
B=01
assignment
C=10
D=11
Dwumfour Abdullai Aziz Slide 28
Step 5: Determine number of flip flops and assign letters
to them

Two (2) flip flops are required since there are four(4) states.
The flip flops are;
Flip flop A -> QA is the state of flip flop A
Flip flop B -> QB is the state of flip flop B

Step 6: decide the type of flip flop to be used

We shall use the D flip flop

Dwumfour Abdullai Aziz Slide 29

 Step 7: derive the circuit excitation table
from state table
PRESENT STATE INPUT NEXT STATE FLIP FLOP INPUT OUTP
UT
QA QB X Q+A Q+B DA DB Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
1 0 0 1 0 1 0 1
1 0 1 0 0 0 0 1
1 1 0 1 0 1 0 0
1 1 1 1 1 1 1 0
Remember the excitation table for D flip flop

Dwumfour Abdullai Aziz Slide 30

 Step 8: Obtain the Boolean expression for
flip flop input

PRESENT STATE INPUT NEXT STATE FLIP FLOP INPUT OUTPUT

QA QB X Q+A Q+B DA DB Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
1 0 0 1 0 1 0 1
1 0 1 0 0 0 0 1
1 1 0 1 0 1 0 0
1 1 1 1 1 1 1 0

Logical Expression for DA , DB and Z in terms of QA, QB and X

Dwumfour Abdullai Aziz Slide 31
 Step 8: Obtain the Boolean expression
for flip flop input
Kmap for DA Kmap for DB
QBX 00 01 11 10 QBX
QA QA 00 01 11 10
0 0 0 0 1 0 0 1 1 1
1 1 0 1 1 0 0 1 0
1

DA=QAQB + QBX + QAX’ DB=QA’X + QA’QB + QBX

Z=???

Step 9: Construct the clock sequential logic circuit diagram for the equations

Dwumfour Abdullai Aziz Slide 32

 State Reduction

❑ Any design process must consider the problem of

minimizing the cost of the final circuit.

❑ The two commonly used cost reductions include;

• Reducing number of flip-flops
• Reducing number of gates.
❑ Since m flip-flops produce 2m states, a reduction in the
number of states may (or may not) result in a reduction in
the number of flip-flops
Dwumfour Abdullai Aziz Slide 33
 State Reduction Cnt’d

❑ It is therefore desirable to know when two or more

states are equivalent in all aspects.
❑ The process of eliminating the equivalent or
redundant states from a state table/diagram is known
as state reduction.
❑ reducing the number of states in a state table must
keep the external input–output requirements
unchanged.

Dwumfour Abdullai Aziz Slide 34

 State Reduction Cnt’d

=F

Perform state reduction on the state table above

Dwumfour Abdullai Aziz Slide 35

 State Reduction Cnt’d

=E

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State Reduction Cnt’d

Dwumfour Abdullai Aziz Slide 37

Perform state reduction

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 Perform state reduction

=g

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 Perform state reduction

=f =g

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Perform state reduction

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Perform State Reduction

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 Perform state reduction

This state diagram satisfies the original input–output

Specifications
it also produce the required output Sequence
for any given input sequence.

Dwumfour Abdullai Aziz Slide 43

Dwumfour Abdullai Aziz Slide 44