(2) 6a om my ow ay @ 3) G0) st) United States Patent Abraham et al. POTTING METHOD. Applicant: Goodrich Actuation Systems Limited, Solihull (GB) Inventors: David Abraham, Weston on Tent (GB): Stuart Waller, Gloucester (GB) Assignee: GOODRICH ACTUATION SYSTEMS LIMITED, Soliull (GB) Notice: Subject to any disclaimer, the tem ofthis pateat is extended or adjusted under 35 USC. 184(b) by 0 days. Appl. Now 16/016,751 Biled: Jum. 25, 2018 ‘ioe Publication Data US 201910069416 Al Feb. 28, 2019 Foreign Application Priority Data Aug. 28, 2017 (EP) i7issia7 Incl, HOsk 300 (2006.01) HOSK 328 (2005.01) HOSK 1/14 (2005.01) HOSK 5106 (2006.01), B29C 39/10 (2008.01) 200 3938 (2006.01) «2 201. 31/34 829K 105100 us. ch cre (2006.01) (2006.01) MOSK 3728 (2013.01); B29C 39/10 (2013.01); B29C 30788 (2013.01); Hask 1/144 2013.01); HOSK S765 (2013.01); B29K 2105/0061 (2013.01); B29L 2031/3481 (2013.01); HSK 2301/0133 (2013.01), 05K 'US011206739B2 US 11,206,739 B2 Dec. 21, 2021 (10) Patent No.: (4s) Date of Patent: 1/0162 (2013.01); HSK 2201/042 (2013.01); HOSK 2203/1327 (2013.01), 05K 2203/1361 (2013.01) (58) Fleld of Classitication Search cre HOSK 3/28; HOSK 1/144 105K 5/065; iHSK 201/042; HOSK 2209/132; B29C 30/10; B29C 39/38; 29K 2105/0061 R291. 2081/3481 ‘See application file for complete search histor. 66) References Cited US. PATENT DOCUMENTS. 6.127038 A 102000 MeCulloush Sas. Re "12013 Fath 8592256 B2* 102013 Onigawn HHosk 30011 “S108 ooe7s70 B2* 72015 Wang Hosk 10256 Dae1ase BE 42016 Keith eal Sjsisi3 Bo $2017 Dunlap ta 20040262749 AL* 122004 Matayaias Je. HOU 28/3121 20060214153 AL* 972006. Therawn owt 21563 25740 20060220260 AL 102006 Takahashi (Continved) (OTHER PUBLICATIONS "Extenda European Soasch Report fo atmational Application No 71881477 data Jan, 2018, 7 pages. Primary Examiner —Pote T Lee (14) Attorney, Agent, or Firm — Cantor Colburn LLP on ABSTRACT Amethod of poting e.g. a stack of printed circuit boards, the ‘method comprising applying a first potting material to selected rogions ofthe eieuit to be ported and then applying 1 sevond, different, potting material over the circuit 10 be potted ims, 1 Drawing ShectUS 11,206,739 B2 Page 2 66) References Cited USS. PATENT DOCUMENTS. 200610226525 AI* 102006 Osyga OIL 23/3128 dss 20070128576 AL 62007 dogorsises AL 62014 aodons9s0s Al* 82014 OIL 2076898 260714 2oisionaaso7 air 122018, HOLL Sho 257790 201610225603 AL* $2016 ‘Toemino iL 2429 doieoress4o Als 122016 ‘ajar, HOIL2950 aorwor942ay AL* 10.2018 Walambe” "Hot 280682 * cited by examinerU.S. Patent Dec. 21, 2021 US 11,206,739 B2US 11,206,739 B2 1 POTTING METHOD FOREIGN PRIORITY ‘This application claims prorty to European Patent Appli- cation No. 171881477 filed Aug. 28, 2017, the entre ‘contents of which is incomporated herein by reference. ‘TECHNICAL FIELD. The present disclosure is concerned with methods of Potting components suci as pebs, paticularly peb stacks, ‘and is particularly wseful for vomponents used in extreme ‘environments such as eavironments where the components ‘can be subject 10 extreme temperatures, shock, vibration ‘andlor exteme pressure BACKGROUND It is known for eg. electronic cious and components to ‘encase the eireuitscomponents, also known as “poting’ 10 provide a protective casing around the circuit to protect the lagileeleetronies from damage. This is particularly impor- tant where the electronics are used in harsh environments where they may be subjected to extremes of temperature of pressure or lo shocks or high vibrations. An example of such ‘an environment isin the aerospace industry ‘Where a system requires several electronic ciruits, its ‘often preferable to form the various eiuits on printed ‘ircuit boards (pebs) which are aranged in a stack of pets, to save space. In aireraf, for example, space for eletronies say be at premium. tis common practice for such stacks to be potted with 2 polymeric material to enhance the overall structural rigidity ‘and to protect against shock, vibrations etc and also to at a5 ‘a medium to dissipate heat generated from powered electric ‘components. Depending on the volume of potting and the ‘maximunv/minimum exposure temperatures, expansion or ‘contraction of the potting material ean induce significant ‘tresses which could result ia damage to the circuit board oF the interconnecting mechanical and electrical joints. "Existing poling compounds have a high density and have a high rate of expansion when heated, and a high rate of ‘contraction when eooled, At extreme temperatures, there= ore, the potting can stress the ciewit components andor Joins The present disclosure is to ¢ method of improving potting to avoid these problems. SUMMARY, According to the present disclosure there is provided a method of poting comprising applying a ist potting com- pound to selected regions ofthe eeu o be potted and then ‘applying a second, differen, potting compound over the cient to be potted, “The fist porting compound is preferably less dense than the second and can be applied to areas ofthe cireuit or peb stack more prone to damage or more fragile eg to the areas ‘of mechanical or eletrial interconnecting joints. This com- pound is selected to apply Tess sires to these areas when heated or cooled. The first compound is tisually & compound that has a Tower rate of expansion andor contraction when heatedeooled, “The second compound can then bea conventional potting ‘componnd applied over the whole circuit 19 be encased including over the frst compound. The second potting ean 2 be applied over atop surface ofthe eicuit part of which has ‘eu porte in the first potting material or, indeed, over other surfaces ‘The method ofthis disclosure therefore olfers a deuree of | design optimisation by using a hybrid of different potting compounds t allow specific rezions t be potted with ‘materials that, when ctred, offer the necessary stnictiral figidity but provide vibration damping in the case of increased rigidity. Regions of structural posting can be controlled by pre-potting with materials that induce Tess snes, therefore reducing the overal stresses induced on the interconnecting mechanical and electrical bonding joins This is achieved by having multiple potting and curing stages to enable the hybrid potting to be built up in layers referred embodiments will now be described, by way of ‘example only, with reference to the drawing. BRIEF DESCRIPTION OF THE DRAWING FIG. 1 isa schematic view of how the potting method of this diselosure can be used, DETAILED DESCRIPTION FIG. 1 shows an example peb stack 100 to be potted. In the example, the stack comprises three pebs 12,3 and intereonnections 10, 11, 12, which may be wires, welds, bonds or other mechanical or electrical interconnections ‘between, to and from the pcbs. Of course any othor devices, ‘components o etcutey units ean bo poted according to the sethod Tn the example, there isa desire fo rece stresses on the lower twa pebs 1,2 and on the interconnections 10, 11, 12 whilst ensuring that the stack has he required rigidity The potting method ofthis disclosure involves pre-poting selected regions ofthe stack 100-here the lower two pbs 1.2 and interconnections 10, 1, 12, using a fist potting material 200 selected to provide some damping © these regions, The fist potting material is preferably less dense than conventional potting material and may be e. a gel type material. The potting of the selocted regions is per formed in a known manner and the fist potting material is cuted ‘The stack 100 is preferably provided in a housing S00 and the first potting materials, in examples such as that shown, poured oF dispensed into the housing fst 10 pot the seleted paris ofthe uit. This s then cured, After curing the housing {s topped up with a second potting material. The second potting stage is pecformed by applying poting of the second, ffrent potting material 300 over the top eb 3 and over the fist potting material 200 to provide dered greater rigcity atthe top ofthe unit whieh is more subject to impaet te. The sovond povting material is preferably denser than the frst And may be e.g. « conventional silicone elastomer material. ‘This is applied in any known manner and is cured, FIG. 1s jost one example, The method ofthis disclosure allows any selected regions to be pre-potted. The stresses indeed on the citeuit will be accommodated by the first potting material rather than the stresses being applied Gireetly 1 the selocted regions e.g. individual pebds or interconnections, ‘Depending on the unit, and whether there is clearance in the housing 800, the second potting 300 could also extend around the sides and even the bottom of the unit in the housing. "As an example, the inventor has experimented with Dov ‘Coming™ FE3200 potting forthe fst potting material andUS 11,206,739 B2 3 Sylaard™ 1700 forthe second potting material, but these are Just ovo of many possible examples “The potting method ofthis disclosure can find application in & wide range of industries where potting of eiruity is recestary, and where vibration damping is desinble “The invention claimed is 1, Amethod of poting a cireuit unit comprising a stack of ‘wo oF more printed cireuit bonds, the method comprising: stacking the two or more printed circuit hoards connected ‘by interconnections to ‘assemble the eireuit unit performing frst pong stage by applying a first potting ‘material to pot selected regions of the circuit unit following assembly of the circuit unit through the stacking, wherein the selected regions inclade one oF ‘more priate cireuit boas of a lower part ofthe slack ‘or one or more interconnections of the lower part of the Sack; and performing a second potting stage by applying a second, dlillerent potting material over the circuit unit and over the first potting material, wherein the first potting ‘material has a lower density than the second potting ‘material, 4 2. The method of elsimn 1 further comprising curing the fit potting material before the second poting ste and caring the second pting materi after the second poting 3 The method of claim 1, wherein the frst poting satel is a gel-ype material and the second potting thatera an elastomer ater “44 pote eet unit comprising: 4 iui unit comprising a stack of to oF more printed ‘iret boars connest by intwoanetions: 8 fist posting material applied to pot selected regions of the Greil unt alles tte wo or more printed ciel boards are stacked assemble the cet unit wherein the selected epions include one oF more pind crit bonds of Tower part of the stack o one oF more interconnections ofthe lower pat ofthe stack and a second, different porting material applied over the iret it and over the fist poting mater wherein the fist pong material has lower density than the second potting materia 5. The poled civil unit of claim 4, wherein the fist potting meterial isa gel-ype material an the second poting ater an elastomer atrial