UNDERSTANDING

THE MIPI DSI, CSI-2

AND D-PHY
INTERFACES
John Phillippe
Systems Hardware
JUNE 2022

PUBLIC
NXP, THE NXP LOGO AND NXP SECURE CONNECTIONS FOR A SMARTER W ORLD ARE TRADEMARKS OF NXP B.V.
ALL OTHER PRODUCT OR SERVICE NAMES ARE THE PROPERTY OF THEIR RES PECTIVE OW NERS. © 2022 NXP B.V.
AGENDA
• MIPI Organization Overview
• MIPI DSI, CSI-2 & D-PHY Overview
• DSI Explained
• D-PHY Explained
• DSI System Example
• CSI-2 Explained
• CSI-2 System Example

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W H AT I S M I P I ? ! ? !

• Mobile Industry Processor Interface -

MIPI
• Founded in 2003 by Arm®, Nokia, ST,
and Texas Instruments. Within a year
Intel, Motorola, Samsung and Philips
joined.
• Currently over 300 members.
• Creates hardware and software
interface standards to simplify the
integration of various components.

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M I P I I N T E R FA C E S F O R D I S P L AY AN D C A M E R A

• Camera Serial Interface [rev] 2 (CSI-2)

−Specifies the data transfer protocol and
basic image sensor control between CSI-2 DSI
camera and SoC
D-PHY D-PHY
• Display Serial Interface (DSI)
−Specifies the data transfer protocol from
an SoC to a display
• Both can use the D-PHY specification for D-PHY D-PHY
electrical transmission – but not
mandatory (alternative PHY’s – C-PHY, CSI-2 DSI

A-PHY, etc.…)
CPU GPU

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M I P I D S I / C S I - 2 / D - P H Y M I S C O N C E P T I O N S / C L A R I F I C AT I O N S

What it is: What it is NOT:

• Point to point fixed interface. • Not designed for hot plug interfaces like
• Intended for production embedded HDMI or USB.
electronics i.e. cell-phone, tablet, • Not “plug and play” – requires
automotive dashboard, etc… configuration at both TX and RX side.
• Lowers pin counts and increases • Not designed for long distances (25-
bandwidth and functionality over legacy 30cm max).
imaging bus standards. • Not designed to support multiple
devices on a single bus (i.e. SPI, I2C).

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D S I : D I G I TA L D I S P L AY B AS I C S – I M A G E F R A M E

• Raster Scan – The image is subdivided into horizontal scan lines

and these lines are subdivided into pixels. By systematically
drawing a scanline pixel by pixel from left to right and then
drawing each scanline from top to bottom an image is displayed.
• Roots of this architecture from original CRT displays from 1930’s.
Blanking area needed for electron beam reset.
• This displayed image is often referred to as a Frame.
• (X,Y) Pixel coordinate data is NOT transmitted.
• Pixels are located relative to their time from the vertical and
horizontal sync signals.
• The display process repeats itself for the next frame, and the next
frame, etc… The film/video world define this timing interval at
which a new frame is displayed is as Frames per Second
(FPS). The computer display world generally use Refresh Rate
(Hertz).

• Image data is transferred in this same fashion both inside the

SoC (through the imaging pipelines) and over various display
links (DSI, HDMI, etc.)
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 D S I : D I G I TA L D I S P L AY B AS I C S – F R A M E S Y N C I N G

Complete Image Frame Including Blanking Pixel Data relative to Sync Signals

• HSYNC – Horizontal Sync – signals line start • VSYNC – Vertical Sync – signals Frame Start
• HBP – Horizontal Back Porch • VBP – Vertical Back Porch
• HFP – Horizontal Front Porch • VFP – Vertical Front Porch 6
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D S I : D I G I TA L D I S P L AY B AS I C S – H D T V E X AM P L E

• 1080P30 HDTV Standard defines 1920 horizontal

“active” pixels and 1080 “active” lines and a frame rate
of 30FPS.
− 1920 x 1080 = 2,073,600 active pixels.
− “Horizontal Blanking” specifies:
▪ HSYNC width of 44 pixels
▪ HBP of 148 pixels
▪ HFP of 88 pixels
− Total line width = 1920 + 44 + 148 + 88 = 2200 pixels.
− “Vertical Blanking” specifies:
▪ VSYNC width = 5 lines
▪ VBP = 36 lines
▪ VFP = 4 lines
− Total frame height = 1080 + 5 + 36 + 4 = 1125 vertical lines.
• A full HD TV frame = 2200 x 1125 = 2,475,000 pixels

Pixel Clock (PCLK) = (Pixels per Frame) * (FPS) = 2,475,000 pixels * 30 FPS = 74.25MHz
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D S I - PAR A L L E L T O S E R I A L

• Display pipeline consists of:

− Pixel Clock
− Vsync/Hsync/Data Enable (DE)
− Data bus width = max supported pixel depth
• DSI takes this parallel data bus and serializes all pixel data, commands, and
events into byte length packets. RGB Interface
• Short packets (4 bytes) are used for Command Mode commands, pixel
format definition and timing critical events like Hsync and Vsync edges.
• Long packets are used to transmit large blocks of pixel or other data. Every
Long packet starts with a four byte packet header and ends with a two byte
packet footer. Payload length ranges between 0 to 216 - 1 bytes long. A Long
packet ranges between 6 to 65,541 bytes.

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D S I – V I D E O M O D E PAC K E T I Z AT I O N

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 D S I : D I G I TA L D I S P L AY B AS I C S – P I X E L F O R M AT S & B I T D E P T H

• RGB – 3 separate integers (of varying bit depths) for the values of Red, Green, Blue.
• RAW – 1 integer (of varying bit depth) for the light intensity of a single pixel.
• Color space transform (ITU-R BT.709 standard) defines RGB to Y’CbCr for HDTV.
• Y’CbCr – Y′ is the luma component and CB and CR are the blue-difference and red-difference
chroma components. Chroma Subsampling allows for 30-50% bandwidth reduction over RGB.
• YUV – Effectively the same as Y’CbCr but used with older analog formats.

Pixel Format bpp Notes

• Critical to know the pixel
24-bit RGB 8-8-8 24 8-bit integer each for the Red, Green and Blue values.
16-bit RGB 5-6-5 16 5-bit integer for the Red and Blue values, and 6-bit integer for Green.
depth or the Bits Per
12-bit YCbCr 4:2:0 12 8-bit integers for Y’, Cb and Cr. Cb & Cr sampled every 3 pixels. Pixel (bpp) for chosen
16-bit YCbCr 4:2:2 16 8-bit integers for Y’, Cb and Cr. Cb & Cr sampled every 2 pixels. format.
RAW8 8 8-bit integer for a single pixel
RAW10 10 10-bit integer for a single pixel.
YUV422 8-bit 16 Same as Y’CbCr 4:2:2

Note: Table shows only a subset of MIPI supported formats

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D - P H Y L AN E S & S TAT E S

Transmitter Receiver
• Source synchronous physical layer which the CSI-2 and DSI Dn + Dn +
protocols both use for physical and electrical communication. Dn - Dn -

• Dedicated Clock lane and configurable number (1-4) of data lanes. D0 + D0 +

D0 - D0 -
• Dual Data Rate (DDR) Clock scheme used for HS mode.
Clock+ Clock+
• During normal operation lanes are either in Control (LP) or High- Clock- Clock-
Speed mode. They’ll constantly switch back and forth between
modes to save power.
• Six different “lane states”.

Line Voltage Levels High-Speed Low-Power

State Code
Dp-Line Dn-Line Burst Mode Control Mode Escape Mode
HS-0 HS Low HS High Differential-0 N/A 1 N/A 1
HS-1 HS High HS Low Differential-1 N/A 1 N/A 1
LP-00 LP Low LP Low N/A Bridge Space
LP-01 LP Low LP High N/A HS-Request Mark-0
LP-10 LP High LP Low N/A LP-Request Mark-1
LP-11 LP High LP High N/A Stop N/A 2

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D - P H Y L AN E I O AR C H I T E C T U R E

• Low Power (LP) mode uses traditional single ended CMOS IO buffers.
• High Speed (HS) mode uses LVDS circuitry
− 50 Ohm traces
− 100 Ohm termination resistor (disabled during LP mode)
• Single Lane IO Block Diagram Below:

TX RX
LP-TX LP-RX

LP-RX LP-TX
P Parameter Description Min Typ Max Units
HS-TX R HS-RX LP Output High 1.1 1.2 1.3 V
LP Input low level threshold (Vil) 550 mV
N
HS Common Mode Voltage 150 200 250 mV
LP-TX LP-RX
HS TX Differential Voltage 140 200 270 mV
LP-RX LP-TX HS Output High Voltage 360 mV

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D - P H Y T R AN S I T I O N F R O M L P T O H S M O D E

Host (TX) Side Client (RX) Side

LP-01 for time TLPX Observes transition from LP-11 to LP-01
LP-00 for time THS/CLK-PREPARE Observes transition from LP-01 to LP-00. Enables Termination

Switch from LP to HS driver Enable HS RX and wait THS/CLK-SETTLE

Drives HS-0 for THS/CLK-ZERO
Drives HS clock for TCLK-PRE
Data Lane drives SoT sequence (00011101)

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D - P H Y T R AN S I T I O N F R O M H S T O L P M O D E

• At the end of a High-Speed Data Burst, lane(s) leave

HS mode and enter the Stop State by means of an
End-of-Transmission (EoT) procedure.
• The clock lane can optionally switch back to a Low
Power State. Staying in HS Mode is known as
continuous clock mode.
• Continuous clock mode allows for higher data rates
since the timing overhead of exiting and re-entering
HS-mode on the clock lane is eliminated

Clock Lane Transition Procedure

TX Side
HS Clock continues for
TCLK-POST
Clock drives HS-0 for TCLK-
TRAIL
Switch from HS to LP and
drive LP-11 for THS-EXIT
RX Side
Detects absence of clock within
a time TCLK-MISS
Detects transition LP-11,
disables HS termination and
enters stop state.
Data Lane Transition Procedure
TX Side RX Side
Data drives opposite bit immediately
after last data packet for THS-TRAIL
Switch from HS to LP and drive LP- Detects transition to LP-11,
11 for THS-EXIT disables HS termination.
Neglects bits of last period during
THS-SKIP
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D S I : i . M X R T 11 7 0 E X A M P L E

i.MX RT1170 EVK + 5.5” LCD Display DSI parameters for RM68200

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 D - P H Y T R AN S I T I O N F R O M L P T O H S M O D E – i. M X R T 11 7 0 E X A M P L E

RM68200 MIPI Parameters

CLKP-CLKN
parameter Min Max

TCLK-TERM-EN 38ns
DATA0P
TCLK-PREPARE 38ns 95ns

TD-TERM-EN 40ns
THS-PREPARE +
157.6ns
DATA0N THS-ZERO

Parameter Description TX/RX Value

TCLK-PREPARE Time that the transmitter drives the Clock Lane LP-00 state. Set longer than RX time to enable termination – defined as TCLK-TERM-EN in RX datasheet. TX 41.67ns

TCLK-ZERO Time that the transmitter drives the HS-0 state prior to starting the Clock. TCLK-ZERO + TCLK-PREPARE > 300ns TX 262ns

TCLK-PRE Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. TX 80ns

THS-PREPARE Time that the transmitter drives the Data Lane LP-00 Line state. Set longer than RX time to enable termination – defined as TD-TERM-EN in RX datasheet TX 41.67ns

THS-SETTLE Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of T HS-PREPARE. THS-SETTLE needs to be > RX
than THS-PREPARE but < THS-PREPARE + THS-ZERO
THS-ZERO Time that the transmitter drives the HS-0 state prior to transmitting the SoT sequence. TX 12ns

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 D - P H Y T R AN S I T I O N F R O M H S T O L P M O D E – i. M X R T 11 7 0 E X A M P L E

Parameter Description Spec. Min/Max Actual

70ns
THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst Min: 65ns
84ns
TEOT Transmitted time interval from the start of THS-TRAIL or TCLK-TRAIL, to the start of the LP-11 state following a HS burst. Max: 120ns
101ns
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. Min: 100ns
Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. 148ns
TCLK-POST Interval is defined as the period from the end of T HS-TRAIL to the beginning of TCLK-TRAIL. Min: 125ns

TCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. Min: 60ns 70ns

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D S I : C L O C K S AN D B AN D W I D T H B A L A N C I N G
• BW_OUT (D-PHY) >= BW_IN (Pixel Bus)
• BW_IN = Pixel Clock * Pixel Depth
• BW_OUT = HS Bit Clock * Num. of Data Lanes
• HS Bit Clock >= Pixel Clock * Pixel Depth / Num. of Data
Lanes
• HS Bit CLK = (PCLK * bpp / # data lanes) * (DSI
Overhead) = (58.66667 * 24 / 2) * (9/8) = 792MHz

BW
BW IN OUT
• Pixel Clock: Incoming display data clock.
• HS Bit Clock: Used to generate the HS MIPI clock. Equal to
the HS bit rate of the data lanes.
• Byte Clock: Is 1/8th the data rate of the HS Bit Clock
• Escape Clock: Used for LP mode control and data
transmission. (12MHz - 20MHz)
• D-PHY HS mode speed range: 80 – 1500Mbps per lane for
NXP devices.
MIPI DSI Clock Lane scope plot using differential
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probe. (Note DDR rate = 792MHz / 2 = 396MHz)
C A M E R A S E R I AL I N T E R FA C E V E R S I O N 2 ( C S I - 2 )

• Think of it like DSI but with an additional I2C link Camera SoC

which allows for more advanced command and D-PHY TX D-PHY RX

control capabilities of a camera module. Dn + Dn + DATAn[7:0]

PIXEL_CLK
Dn - Dn -
− For example the SOC might want to adjust camera exposure while PIXEL_CLK
camera is streaming data which the D-PHY “Bus Turn Around” D0 + D0 + CSI-2 VSYNC
feature can’t be utilized for. D0 - D0 -
DATA0[7:0]
RX
HSYNC
• CSI-2 transmitter turns the pixel data, VSYNC and Clock+ Clock+
BYTE_CLK DATA[W:0]
HSYNC pulses into a series of byte-sized packets to Clock- Clock-
be sent over the physical D-PHY interface while
SCL SCL
maintaining the critical timing parameters relationship SDA SDA
to each other.
• The receiver rebuilds the video datastream – Vsync, • BYTE_CLOCK: generated automatically by the D-
Hsync, pixel data bus. PHY and is always 1/8 the speed of the HS bit
clock.
• Supports different pixel formats (e.g. RAW6-14) • PIXEL_CLK: generated by the SOC and needs to
• Allows for image data (exposure, histograms, etc..) to be set so that image bandwidth exiting the CSI-2
block is greater than or equal to the image
be sent in VFP/VBP area. bandwidth entering the block.

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C S I - 2 : F R A M E F O R M AT

• Similar in concept to DSI

frames but different terminology
• Line blanking = Horizontal
Blanking
• Frame Blanking = Vertical
Blanking
• Support for embedded data –
used for image sensor
information (gain, exposure
time, etc…)

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C S I - 2 E X AM P L E : i. M X R T 11 7 0 + O V 5 6 4 0

• Need to configure both the CSI-2 RX clocks

and the camera clocks.
• RX has only one tunable parameter: THS-SETTLE
• 1280 x 720 resolution at 30FPS
• OV5640 Hsync is 612 pixels which gives an
HTOT = 1892. OV5640 5.5” LCD displaying OV5640
• OV5640 Vsync is 2 lines and the Vfp + Vbp = Camera camera input
18. Therefore the VTOT = 720 + 18 + 2 = 740 Module
lines.
• OV5640 Pixel Clock = 1892 * 740 * 30 =
42MHz
• The RGB565 format requires 16bpp so the
bandwidth = 42MHz * 16 bpp = 672Mbps
• This system uses a 2-lane MIPI interface so the
data rate per lane is = 672 Mbps / 2 = 336Mbps
• The MIPI D-PHY HS Bit Clock therefore needs
to be: 336Mbps / 2 = 168MHz
OV5640 D-PHY Clock = 168MHz

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 D - P H Y D ATA T R AN S F E R

• The Stop State is the default state from which everything starts from or reverts back to.
• The transition between LP and HS mode incurs some “time overhead” which must be accounted
for during the initial setup.

Clock shown 1 whole line of

as differential image data LP Mode
“blanking
time””

Data P/N shown HS Mode –

pixel data
Singled-ended

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C S I - 2 : D ATA I N T E R L E AV I N G / V I R T U A L C H A N N E L

• Packet Types:
• Data Type
• Virtual Channel
Identifier
• Both can be mixed to
create a tree of
interleaved data and
a theoretical max of
16 images per
interface.

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C S I - 2 : I M A G E S E N S O R B AS I C S

• An image sensor contains an array of

Slide
photosensitive elements – pixels. The OV5640 has

needed?
a pixel array of 2624 columns by 1964 rows for a
total of 5,153,536 pixels. Active columns are 16 –
2607 and active lines are lines 14 - 1957 giving a
maximum useable image array of 2592 x 1944 =

•
5,038,848 active pixels.
TBD based
An ADC samples the voltage of each pixel and
outputs a digital value. This unprocessed digital
value is what is known as a RAW format. The
upon time
OV5640 has a 10-bit ADC and therefore outputs in
a native “RAW10” format.
• Image data is transferred just like raster displays –
a stream of pixel data left to right, top to bottom and
with no (X,Y) coordinate data. Active
Image
Area
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