PROJECT REPORT

Group: Lê Ngọc An 2252007

Phạm Tấn Phong 2252614
Phạm Tấn Khoa 2252359
Lê Nguyễn Minh Duẫn 2252108

Group:

07/05/2023
Hồ Chí Minh City
I. Theory:
 Conceptually, FIFO stands for First In First Out. It is used to refer to the
order of reading and writing data in and out of the FIFO. The data that is written in
first will be read out first.
In logic design as well as hardware design, FIFO is very commonly used:
- Need to store a relatively larger amount of data than single registers. This
amount of data is usually not too large in size.
- Need to temporarily store a certain amount of data for synchronization
between two clock domains with different clocks.
- It is necessary to save a certain amount of data as the unit of a certain
calculation process.
At that time, people often used FIFO.

II. FIFO's logic:

If software thinking is used, FIFO is a set of N components, each of which
has a width of M. Each FlipFlop has M bits, which is equal to an amount of N. The
FIFO has a capacity of A = N x M bits, or A = N x M /8 bytes.
Pointers or addresses are used to identify elements so that they may be
accessed through the FIFO.
- The write address is used for FIFO recording.
- The read address is used by the FIFO reading component.
FIFO is a FlipFlop array, hence it has the ability to store values.
Theoretically, we can access any FIFO element using the read address if the FIFO
is fully written.
The data in the FIFO won't change if nothing is written to it. Therefore, the
FIFO's value can only be changed via writing. The "write_enable" signal will thus
be used to control writing.
FIFO does not employ reset signals, like memory in general. The initial
values must be written to the FIFO in order to set the starting value.

III. Code:
 write_enable:
-1’b0: Depending on the value of wr_pointer, certain nth FIFO data will
retain their value.
-1’b1: Depending on the value of wr_pointer, specific nth FIFO data will be
updated with the value of data_in.
We can now see that this is how writing to FIFO is done.
As a result, the whole code for a basic FIFO:
/*
module fifo (clock, write_enable, wr_pointer, rd_pointer, data_in,
data_out);
input clock;
input write_enable;
input [3:0] wr_pointer;
input [3:0] rd_pointer;
input [7:0] data_in;
output [7:0] data_out;
wire clock;
wire write_enable;
wire [3:0] wr_pointer;
wire [3:0] rd_pointer;
wire [7:0] data_in;
wire [7:0] data_out;
// internal signals
reg [7:0] FIFO [15:0];
always @ ( posedge clock ) begin
if ( write_enable == 1'b1 )
FIFO[wr_pointer] <= data_in;
end
assign data_out = FIFO[rd_pointer];
endmodule
*/
Schematic of the FIFO block
- WE1 (Write_Enable)
- RA (Read Address)
- WA (Write Address)
- WD (Write Data)
- RO (Read Output)
IV. Testbench:
/*
module simple_fifo_test();
reg clock;
reg write_enable;
reg [3:0] wr_pointer;
reg [3:0] rd_pointer;
reg [7:0] data_in;
wire [7:0] data_out;
reg [4:0] i;

fifo answer (
.clock (clock),
.write_enable ( write_enable ),
.wr_pointer(wr_pointer),
.rd_pointer(rd_pointer),
.data_in (data_in),
.data_out (data_out)
);

always begin
#5; clock = ! clock;
end

initial begin
clock = 1'b0;
write_enable = 1'b0;
wr_pointer = 4'h0;
rd_pointer = 4'h0;
data_in = 8'h00;
 i =0;
end

initial begin
#25;
for ( i = 0; i < 16; i = i + 1 ) begin
@ ( posedge clock );
write_enable = 1'b1;
wr_pointer = i;
rd_pointer = i-1;
data_in = $random();
end

@ ( posedge clock );
write_enable = 1'b0;
#25;
end

endmodule
*/
Testbench features:
- Create a clock.
- Produce signals for recording-process control.
- The input value, data_in, is chosen at random.

- Check the FIFO value on the test bench.

- The read pointer has not been altered by the testbench mentioned above,
therefore you can alter the read pointer to read the FIFO.
Testbench waveform

V. Applications:
• Connection of Peripherals to Processors:
Modern processors are often considerably faster than peripherals that are
connected to them. FIFOs can be used so that the processing speed of a processor
need not be reduced when it exchanges data with a peripheral. If the peripheral is
sometimes faster than the processor, a FIFO can again be used to resolve the
problem. Different variations of circuitry are possible, depending on the particular
problem.
 A FIFO can be used in the same way to optimize data transfer from a
processor or RAM to a peripheral.
As a practical example of the connection of a fast peripheral to a processor,
consider the compression of a digitized video signal with the TMS320C30 signal
processor. The video signal is digitized by an A/D converter (ADC), then the
picture information contained in the video signal is compressed by the signal
processor. In addition to picture information, a video signal (see Figure 28)
includes pulses for horizontal and vertical synchronization, as well as the porch.
But only the pure picture information is of interest for further processing by the
TMS320C30 signal processor.

The data rate of the digitized picture information is too high for direct
acceptance by the TMS320C30. But, because the picture information accounts for
only part of the video signal, the time of one scanning line is quite sufficient for
receiving the data. If a FIFO is used to buffer the data, the computing time that is
gained can even be made use of to compress the data.
The circuit shown in Figure 29 first digitizes the video signal with the aid of the
ADC. The clock generator produces the timing for the ADC from the video signal.
The cycle generator transfers the clock signal to the FIFO only for digitized picture
data, not for data originating from the porch or synchronization. Once there are
enough data buffered in the FIFO, the HALF FULL flag starts data transfer by
means of the direct memory access (DMA) controller.
• Block Transfer of Data:
Data are often split into blocks and transmitted on data lines. Computer

networks and digital telephone-switching installations are examples of this

application. If such a conversion into blocks has to be made at very high speed, it
is possible only with appropriate hardware, not through software.
A simple solution to this hardware problem is the use of FIFOs (see Figure
30). A FIFO with a HALF FULL flag should be selected.
Furthermore, memory depth should correspond to twice the size of a block.
As soon as the HALF FULL flag is set, the send controller starts sending the data
block. The send controller consists, in this case, of a counter and some gates and is
very easy to implement with just one PAL. The writing of data into the FIFO can
be carried on continuously and is independent of the transfer of data blocks.

• Programmable Delay:
With FIFOs, it is possible to implement a programmable, digital delay line
with minimum effort. Because of the programmable AF/AE (ALMOST
FULL/ALMOST EMPTY) flag of the SN74ACT7881, only one inverter in
addition to the FIFO is necessary (see Figure 31).
First, program the AF/AE flag according to the required delay of n clock
cycles to the value n – 2. To obtain a 64-bit delay line, program AF/AE to 62.
When data words are written to the FIFO, it constantly fills. When the number of

stored data words corresponds to the programmed value, the AF/AE flag changes
two clock cycles later to low level. The delay of two clock cycles results from the
integrated, multilevel synchronization of the AF/AE flag. This flag then starts, with
the aid of the inverter, reading data words on the output of the FIFO. Subsequently,
the FIFO works like a shift register of fixed length. The timing of the signals in this
programmable digital delay is illustrated in Figure 32.

• Collecting Data Before an Event:

Some applications require data that appear before an event to be collected.

This can be solved with the aid of a circular memory whose data intake is stopped
by the event. A FIFO makes an excellent basis for a device to fulfill this function.
The device shown in Figure 33 is an extension of the programmable delay in
Figure 31. The timing of the signals in the circuit is illustrated in Figure 34.
• Collecting Data Before and After an Event:
By extension of the device in Figure 33, data words can be collected both
before and after the occurrence of an event (see Figure 35); 1024 data words are
always collected. With the aid of the programmable AF/AE flag, it is possible to
specify the number of data words that are collected before and after the event.