Course Code: 19EEEN1034 Course Title: Hardware Description Language

Course Category: Professional Elective Course Level: Mastery

L:T:P(Hours/Week): Credits: 3 Total Contact Hours:45 Max Marks:100

3: 0: 0
Pre-requisites

 Digital Electronics

Course Objectives
The course is intended to:
1. Explain the Verilog Overview and Hierarchical Modeling Concepts
2. Explain the Basic concepts and Modules & Ports
3. Discuss Gate Level and Data flow Modeling
4. Explain Behavioral Modeling
5. Enlighten on overview of VHDL
Unit I Verilog Overview and Hierarchical Modeling Concepts 10 Hours

Evolution of Computer-Aided Digital Design- Emergence of HDLs- Typical Design

Flow- Importance of HDLs-Popularity of HDL- Trends in HDLs. Top-down and
bottom-up design methodology -Modules –Instances- Components of a
simulation- Design block, Stimulus block
Unit II Basic concepts, Modules & Ports 8 Hours

Basic Concepts: Lexical conventions-data types- system tasks- compiler directives.

Modules and Ports Module: Definition- port declaration- connecting ports-hierarchical
name referencing.
Unit III Gate Level and Data flow Modeling 10 Hours

Gate-Level Modeling: Modeling using basic Verilog gate primitive- description of and/or
and buf/not type gates- rise, fall and turn-off delays- min, max, and typical delays.
Dataflow Modeling: Continuous assignments-delay specification-expressions-

Passed in Board of Studies meeting Approved in Academic Council meeting

BOS Convener BOS Chairman

operators-operands-operator types.

Unit IV Behavioral Modeling 7 Hours

Structured procedures-initial and always- blocking and non-blocking statements - delay

control- generate statement - event control - conditional statements - Multiway
branching – loops - sequential and parallel blocks

Unit V Tasks ,Functions and Modeling Techniques 10 Hours

Differences between tasks and functions, declaration, invocation, automatic tasks and

Functions, Procedural continuous assignments, overriding parameters, conditional

compilation andExecution, useful system tasks.

Course Outcomes Cognitive

At the end of this course, students will be able to: Level

CO1: Explain the Verilog Overview and Hierarchical Modeling Concepts Understand

CO2: Implement the Basic concepts in simple circuits Apply

CO3: Examine Gate Level and Data flow Modeling Apply

CO4: Execute Behavioral Modeling in verilog Apply

CO5: Describe on modeling techniques Understand

Text Book(s):

T1. Samir Palnitkar, ―Verilog HDL: A Guide to Digital Design and Synthesis‖, Pearson
Education, 2nd Edition 2003

T2. Kevin Skahill, ―VHDL for Programmable Logic‖, PHI/Pearson education, 2006.

Reference Book(s):

R1. Donald E. Thomas, Philip R. Moorby, ―The Verilog Hardware Description

Language‖, Springer Science,Business Media, LLC,1996

R2. Michael D. Ciletti, ―Advanced Digital Design with the Verilog HDL‖ Pearson
(Prentice Hall), 2nd Edition.2011
Passed in Board of Studies meeting Approved in Academic Council meeting

BOS Convener BOS Chairman