Design Considerations for Power Efficient
Continuous-time Delta-Sigma Converters
Shanthi Pavan
Indian Institute of Technology, Madras
Abstract—Continuous-time Delta-Sigma Modulators
(CTΔΣMs ) are a compelling choice for the design of
high resolution analog-to-digital converters. Many delta-
sigma architectures have been published (and continue to
be invented). This leaves the designer with a bewildering
array of choices, many of which seem to pull in opposite
directions. Further, it is often difficult to make a clear
comparison of various architectures, as they have been
designed for dissimilar specifications, by different design
groups, and in different technology nodes. This paper
examines various design alternatives for the design of power
efficient single-loop continuous-time delta sigma converters.
I. I NTRODUCTION
Continuous-time ΔΣ modulation is a robust and
attractive technique that uses oversampling and negative
feedback to achieve high resolution analog-to-digital con-
version [1]. The block diagram of a CTΔΣM is shown
in Fig. 1. The input u is processed by a continuous-time
loop filter, before being sampled by a coarse ADC. The
output of the ADC is converted into a waveform using a
DAC, which is fed back to the loop filter.
u L0,ct (s)
%(' v
L1,ct (s)
v(t)
(%'
Fig. 1. Block diagram of a CTΔΣM.
A CTΔΣM has several advantages over its discrete-
time counterpart. If the loop filter is time invariant, a
CTΔΣM features the remarkable property of implicit
anti-aliasing. Further, the active circuitry in the loop
filter is more power efficient than the corresponding
discrete-time realization, since settling is not necessary.
Finally, a CTΔΣM presents a resistive input impedance.
This makes them easy to drive, and simplifies system
design. Due to all the appealing aspects mentioned above,
CTΔΣMs are now routinely used in many signal chains,
ranging from sensor interfaces to wireless transceivers.
Many delta-sigma architectures have been published
(and continue to be invented) [2]. Most authors show
experimental results proving the virtues of their design
techniques. This leaves the designer with a bewildering
array of choices, many of which seem to pull in opposite
directions. For example, should one choose a single-bit
978-1-5090-1830-7/16/$31.00 2016
c IEEE
quantizer and operate with a high oversampling ratio
(OSR), or a multi-bit quantizer and use a smaller OSR
instead? Is the successive approximation register (SAR)
architecture a good choice to use for the coarse ADC?
Is a switched-capacitor DAC appropriate to mitigate the
effects of clock jitter? It is also often difficult to make
a clear comparison of various architectures, as they have
been designed for dissimilar specifications, by different
design groups, and in different technology nodes.
The aim of this tutorial paper is to help the reader
navigate through the dizzying maze of design choices.
The rest of this paper, which focuses on single-loop
designs, is organized as follows. Section II describes
various trade-offs in the design of the ADC and DAC,
which form the coarse quantizer of the loop. Clock jitter
and loop filter linearity considerations are discussed in
Section III. In Section IV, we compare three CTΔΣMs
from the literature. All these audio modulators attempt to
achieve similar SNDR using different architectures, and
are designed in the same flavor of technology, by the
same research group. Thus, a good “apples-to-apples”
comparison is possible. Section V gives the conclusions.
II. Q UANTIZER N ONIDEALITIES
A. ADC Design
The ADC in a one-bit modulator is simple to
implement, as it consists of a single comparator. Since
the ADC compares the loop-filter output with zero, a
reference ladder is not necessary. Clock generation and
distribution circuitry is simple, and consumes relatively
less power. More importantly, comparator offset is of no
consequence. This means that small devices can be used
in the comparator, reducing its power dissipation, and
that of the clock generation circuit.
In a multibit design, the ADC is commonly im-
plemented using a flash architecture so as to minimize
delay in the loop. As a result, the hardware complexity
of the ADC increases exponentially with the number
of bits resolved. Though the sampling rate needed to
achieve a desired SQNR in a multibit modulator is
lower, the increased number of comparators more than
compensates for the reduction in operating frequency. For
example, using a 4-bit quantizer instead of a 1-bit one
in a third order CTΔΣM enables the sampling rate to
be reduced by a factor of about 2. This means that if
the same comparator was used in both the single-bit and
multi-bit designs, the ADC in the latter would consume
369

Fig. 2. In-band SNDR of a third order, 15-level CTΔΣM in the
presence of random offset in the comparator thresholds.
about 8x more power though operating at half the rate.
Unfortunately, it also turns out that the comparators used
in the multibit case need to be “better” – the reason is
comparator offset, as described below.
The shape of the quantizer’s transfer curve is modi-
fied by offsets in the comparators that comprise the flash
ADC. As a result, the in-band quantization noise and
the maximum stable amplitude change. Fig. 2 shows the
simulated in-band SNDR of a third order modulator with
varying levels of comparator offset. The quantizer has 15
levels, OSR = 64 and the NTF is maximally flat with
an out-of-band gain of 2.5. The input is a -6 dBFS tone
in the signal band. Comparator offsets are assumed to
be Gaussian distributed, with σoff denoting the standard
deviation of offset normalized to the nominal step size.
200 Monte Carlo simulations are performed for each
value of σoff . It is apparent that the SNDR can degrade
significantly (by about 20 dB) when σoff is large. It is
necessary, therefore, to ensure that comparator offsets are
kept small. Fig. 2 indicates that σoff = 0.05 is a good
value to target in our example.
 asynchronous SAR ADCs in the loop.
ˆ
ˆ
(when compared to feedback DAC nonidealities), worst
case comparator offsets do have to be restricted to a
fraction of the nominal step size. One way of achieving
this is to use comparators with large devices – this is not
a power efficient solution. An alternative is to use offset
correction. This increases design complexity.
A multibit loop also complicates the design of the
loop filter due to the following. The input range of the
ADC in a multi-bit loop is often chosen to be as large as
possible to relax offset requirements on the comparators
of the flash ADC. This means that the swing at the
output of the loop-filter has to be large, which makes the
design of the integrator driving the flash ADC difficult.
Combined with the fact that a multi-bit ADC presents
a larger load to the loop-filter, the design of the loop
filter can become particularly challenging. The single-bit
CTΔΣM scores over its multi-bit cousin on this count.
After all, the 1-bit ADC only determines the sign of
the loop-filter’s output, which means that the latter can
be conveniently scaled without affecting the modulator’s
output.
All things considered, therefore, it appears as if
the design of the ADC in a multibit modulator is much
more involved, consumes a larger area and dissipates
more power.
SAR-Based Quantizers: Many recent works (see
[3] for example) have advocated the use of a succes-
sive approximation register (SAR) ADC in place of
the typical flash converter. What advantages does this
approach have? A traditional SAR ADC uses only one
comparator and resolves one bit per decision cycle. Its
power dissipation, therefore, increases linearly with the
number of bits resolved. A synchronous SAR design
needs its sampling clock frequency to be several times
that of the modulator. This has motivated the use of
The offset of the comparator does not influence
performance, as it is equivalent to an offset in its input.
17%H&*7

The SAR ADC’s decision thresholds are determined

ˆ by device matching in its internal capacitive DAC. 1%
ˆ
matching can be easily achieved on chip, and this is
more than adequate to achieve the 4-5 bit resolution
ˆ
needed from the SAR ADC. Since comparator offset is
ˆ not problematic anymore, the input to the ADC can be
     
σ 2SVQEPM^IHXS7XIT7M^I
SJJ
Fig. 3. MSA of the CTΔΣM with varying σoff .
Fig. 3 shows the MSA of the CTΔΣM as a function
of comparator offset. We see that this is also affected,
though not quite as much as the in-band SNDR.
A commonly touted advantage of a multi-bit design
is that a more aggressive NTF can be used, resulting in
better in-band noise shaping. The simulation results and
discussion above show that a large part of this benefit
could be lost if comparators with sufficiently low offset
are not used. While flash ADC errors are less critical
370 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
scaled – just like in a single-bit modulator. A SAR ADC,
therefore, addresses two key problems associated with a
flash converter.
Unfortunately, however, the use of a SAR ADC
poses its own set of difficulties. The first is the problem
associated with sampling the loop filter output on to
the capacitors of the SAR ADC. This is particularly
challenging for the loop filter, which needs to charge
the ADC’s input capacitance within a fraction of the
modulator’s clock period. Further, the binary output of
the SAR ADC needs to be converted into a thermometer
code to drive the feedback DAC. This adds extra delay
into the loop.
clk adc
eadc
Multi-bit with a SAR ADC or a Single-bit CTΔΣM?
u(t) L(s) %(' v[n]

Given the above arguments in favour of using a SAR

ADC, it is natural to wonder how a multi-bit CTΔΣM
using a SAR ADC in the loop fares in comparison
with a single-bit CTΔΣM. For better insight into this, (%'
consider an N th order, single-bit modulator that achieves
edac
a certain in-band SQNR while sampling at fs . Let us now clk dac
replace the ADC with a 2-bit SAR converter operating
at fs /2. Since the number of ADC levels has increased
to four, the quantizer step size is smaller. The OSR, Fig. 4. Modeling jitter induced errors in a CTΔΣM .
however, is reduced by a factor of two. This lowers the
modulator’s resolution by (N + 0.5) bits. It is thus seen
that the reduction in SQNR due to a smaller OSR greatly III. C LOCK J ITTER AND L OOP F ILTER L INEARITY
overwhelms the increase due to a smaller quantizer step.
It thus seems that the advantages of using a single-bit Clock jitter can be a significant source of SNR
quantizer are hard to beat. degradation in a CTΔΣM . The effect of jitter on the
modulator loop can be modeled by errors at the input
and output of the ADC and DAC respectively [4], [5]
B. DAC Design as shown in Fig. 4. It is immediately apparent that eadc
is shaped by the modulator’s NTF, just like quantization
noise, and has virtually no effect on the in-band spectrum
The performance of a negative feedback loop is a
of the CTΔΣM .
strong function of its feedback block, and a CTΔΣM
is no exception to this rule. The fidelity of the DAC, The story is different, however, with the error in-
therefore, has a tremendous bearing on its in-band per- duced by jitter at the DAC output. As seen in Fig. 4,
formance. Distortion in the DAC is of two types – static edac adds to the input to the modulator and degrades the
and dynamic. The former is caused by element mismatch modulator’s in-band SNR.
in the DAC. The latter is dependent on implementation We first consider the case of an NRZ DAC, as
details. Assuming an NRZ DAC, dynamic distortion is shown in Fig. 5. Without jitter, its output waveform has
due to inter-symbol-interference (ISI) caused by unequal transitions that occur at multiples of Ts . The difference
rise and fall times of the DAC pulse. between the ideal and jittery output waveforms is shown
A commonly heard refrain is that “the two level in the lower part of the figure – it consists of a sum
DAC needed in a single-bit modulator is inherently of slivers, whose width and height at nTs are given by
linear”. This is largely true, though it neglects dynamic Δt[n] and height (v[n] − v[n − 1]) respectively. We see
distortion introduced by the DAC, which limits linearity
at high speeds/resolution. (%'MRTYXGSHI 26>(%'SYXTYX
Element mismatch in the feedback DAC of a v[n] ;MXLNMXXIV -HIEP
multi-bit CTΔΣM can dramatically degrade the in-band
SNDR. This has spawned a variety of methods that
address the problem – ranging from analog calibration
to dynamic element matching (DEM). Most of these
techniques address only static mismatch. DEM, in partic- (a)
ular, is a hugely popular technique that shapes mismatch
edac (t)
noise out of the signal band. This, however, introduces
additional delay in the feedback loop and increases
power dissipation. Further, DEM algorithms designed Δt[n](v[n] − v[n − 1])
without dynamic mismatch in mind, in combination with
DAC designs that do not carefully address this issue,
typically worsen CTΔΣM performance. While recent (%' (%'
DEM algorithms address dynamic distortion, it appears (b) (c)
edac eeq,dac
as if the design complexity is increased. clk dac clk dac

In summary, dynamic distortion is a problem with

single-bit and multi-bit modulators, and needs to be Fig. 5. (a) DAC input sequence, and output waveforms with and
addressed anyway. From the implementation viewpoint, without clock jitter. (b) Error waveform (c) Equivalent model, accurate
therefore, a single-bit DAC seems a lot more attractive. at low frequencies.

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 371
 that jitter in a particular clock edge introduces an error
u 0SST*MPXIV v
at that edge only if the modulator output changes in that v1 (t)
-
cycle. Further, the noise is dependent on the height of
*-6(%'
the transitions in the output waveform. Using a multi-bit GPO

(%'
quantizer, therefore, is a very good way of reducing the
sensitivity of a CTΔΣM to clock jitter. (a)

Example : Jitter Noise in 1 and 4 bit CTΔΣMs
u(t) v1 (t)
Assume that we need to design a CTΔΣM with an
in-band SQNR of 110 dB in a 25 kHz bandwidth. Several
combinations of order, OSR and number of quantizer
levels can be used to achieve the desired SQNR. We con-
sider two modulators: one which uses a 1-bit quantizer,
and another which employs a 16-level quantizer. Further,
we restrict the orders of both modulators to three. The
NTFs of both modulators are chosen to be maximally flat
with an out of band gain of 1.5. Clock jitter is assumed
white, with an rms value of 25 ps. Calculations show that
the two-level modulator needs twice the OSR as its 16-
level counterpart to achieve the same peak SQNR. We
also see that the SNR due to jitter is about 28 dB worse
in the single-bit case than in the multibit one. This makes
sense - the step size, relative to full scale, in the latter
is smaller by a factor of 15, and the MSA is higher by
about 2 dB. When compared to Ts , rms jitter is smaller
by a factor of 2 (6 dB), but OSR is also smaller by the
same factor (-3 dB). The net increase in SJNR due to
multibit operation, therefore, is seen to be (25 + 6 - 3)
= 28 dB.
2-levels 16-levels
Order 3 3
NTF’s OBG 1.5 1.5
OSR 128 64
fs 6.4 MHz 3.2 MHz
Ts 156.25 ns 312.5 ns
Maximum Stable Amplitude 0.8 FS FS
Peak SQNR 110 dB 110 dB
Peak SJNR 88 dB 116 dB
From the discussion above, we see that clock jitter
can be a potential show-stopper for a single-bit CTΔΣM
. This has motivated research into techniques that aim
to address this problem. One such approach the use of
switched-capacitor (SC) feedback [6]. An SC-feedback
DAC attempts to reduce jitter sensitivity by feeding a
packet of charge into the loop filter in an impulsive
fashion. Unfortunately, this greatly increases the peak-
to-average ratio of the feedback waveform, and causes
linearity problems in the loop filter. Further, SC DACs
severely compromise alias rejection of the modulator
around multiples of the sampling frequency [7].
Another (particularly elegant) approach to address
the jitter sensitivity of a single-bit CTΔΣM is the use of
FIR feedback [8], [9]. We illustrate with the single-bit
example shown in Fig. 6. The 2-level output sequence v
is filtered by an N-tap low pass FIR filter with transfer
function F(z), before exciting the main feedback DAC.
The DAC has an NRZ pulse shape. For simplicity, the
372 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
*^
v z −1 z −1 z −1 z −1
(b) a0 a1 aN −2 aN −1
v1 (t)
Fig. 6. Using an FIR feedback DAC to mitigate noise due to clock
jitter in a single-bit modulator.
tap weights of F(z) are assumed to be identical. Since
v = ±1, the magnitude of transitions in v is 2. With F(z)
in place, this is reduced to 2/N . Thus, the magnitudes
of the steps in the feedback DAC waveform (denoted
by v1 (t) in Fig. 6(a)) are N times smaller than what
they would have otherwise been. Since noise due to
clock jitter is proportional to the height of the transitions
in the DAC output, it follows that the in-band mean
square noise due to jitter is reduced by 20 log(N) dB.
This argument assumes that the jitter is common to all
the DAC elements. An implementation should therefore
use a common clock for all elements– i.e. not a tree of
clock buffers.
The FIR DAC has other important benefits. Since
F(z) is a low pass filter, the input component of v is not
affected, but the power of the shaped noise is reduced.
The DAC’s output v1 (t), therefore, has a reduced high
frequency content that closely follows the input u. The
error processed by the loop filter, which is u(t) − v1 (t),
is therefore much smaller. This relaxes the linearity
requirements of the loop filter, just like in a CTΔΣM
with a multi-bit DAC. Intuitively, since v1 (t) “looks”
like the output of a multibit DAC, one should expect
similar benefits with respect to clock jitter and loop filter
linearity.
Implementing the FIR DAC as drawn in Fig. 6(a) is
problematic when the DAC levels are not equally spaced
(due to mismatched components). Recognizing that v[n]
is a two level sequence, a linear DAC-filter combination
can be realized using the semi-digital approach [10], as
shown in Fig. 6(b). Here, the delays are implemented
digitally, while the individual DAC outputs (which are
assumed here to be currents) are weighted and summed
in the analog domain. It is easy to see that DAC mismatch
modifies the transfer function of the filter, but does not
cause nonlinearity.
Fig. 7 compares the PSDs of single-bit, multi-bit and
single-bit+FIR DAC third-order CTΔΣMs with clock
jitter [11]. The PSD without jitter is also shown. The
 0
exist. The switched-resistor NRZ DAC feeds back a rail-
−20 to-rail waveform. If the OTA was ideal (Gota → ∞), the
−40
virtual ground potential would be zero, and the current
through the integrating capacitor would be (u + v)/R,
−60 which would in turn be sunk by the OTA. In practice, vx
P SD (dB)

−80 would need to swing due to the finite transconductance

2 − level quantizer of the OTA. Finite bandwidth of the OTA would make
−100
matters worse – the rail-to-rail steps in the feedback
−120 12 − level quantizer waveform would necessitate large swings at OTA’s virtual
ground. Such large swings result in significant nonlinear
−140
2 − level quantizer Ideal currents in the OTA, and degrade CTΔΣM linearity.
−160 + 12 − tap F IR DAC
Several ways of addressing this have been proposed.
0 10 20 30 40 One method is to use a multi-stage OTA, so as to
f (kHz)
increase its gain within the signal band. This enhances
the linearity of the integrator. An alternative technique is
Fig. 7. Comparison of the PSDs of various CTΔΣMs with clock to use the concept of opamp assistance [13]. The idea is
jitter. The ideal (jitter-free) spectrum is also shown for comparison.
the following. The current that the OTA needs to sink is
known, since the feedback sequence v and the modulator
input u are readily accessible. Thus, the current (u+v)/R
multibit modulator employs a 12-level quantizer, and is
can be generated by the so-called ‘assistant’ circuitry,
clocked at 1/3 the clock rate of the single-bit design.
shown in the lower part of Fig. 8. A transconductor
This way, both modulators have the same in-band SQNR.
gm = 1/R generates the input component of ic . The
As expected, the performance of the single-bit design is
DAC component v/R is generated by a current steering
significantly worse than that of the multibit one. When a
DAC. Thus, the assistant supplies the current that the
12-tap FIR DAC is used, however, the noise due to jitter
OTA would otherwise be called upon to sink, and no
reduces by 20 log(12)=21.5 dB, and the performance of
current flows into the OTA. Thanks to this, vx remains
the 1-bit and multibit designs are nearly the same. The
zero, and speed and distortion problems are avoided. In
assumption here is that NTF of the single-bit modulator
practice, the OTA would have only sink the mismatch
has been restored after incorporating the FIR DAC.
between assistant and input currents. At any rate, the
This can be accomplished using several methods – in
quiescent current in the assistant circuitry must be large,
a CTΔΣM , using the method of moments [12] is a
since the magnitude of the error current is large.
convenient technique that avoids going back-and-forth
between continuous and discrete time domains. In a multibit modulator, this problem is avoided,
since the fedback waveform is a good approximation
A. Loop Filter Linearity of the input. Since the first integrator needs to process
the small difference between the input and feedback
4Vref waveform (which is a few quantizer levels), the power
u C R
dissipation of the integrator can be small.
R
u
Using a single-bit modulator with FIR feedback
R vx
(originally intended to address clock jitter) also helps
R Gota with respect to the linearity of the loop filter, as seen
v
 from the input and feedback waveforms of Fig. 6.
V
± ref
R To summarize the discussion so far, we have seen
u that using a plain 1-bit quantizer, while being a very
R efficient use of hardware, is severely impacted by jitter
u gm
and is problematic for the linearity of the CTΔΣM .
Assistant Fortunately, using FIR feedback with a one-bit ADC not
v (%'
Vref
only addresses the jitter problem, but also greatly relaxes
± R the linearity requirements of the loop filter, just like with
a multibit quantizer. FIR feedback, therefore, combines
Fig. 8. The problem of integrator nonlinearity in a single-bit
modulator, and its mitigating using opamp assistance. the beneficial aspects of single bit and multibit designs,
without the disadvantages of either approaches.
The loop filter processes the difference between
the modulator input and the feedback DAC waveform. IV. M EASUREMENT R ESULTS
This has serious linearity implications for the loop filter,
as illustrated using Fig. 8. The figure shows the first This section compares measurement results from
integrator of the loop filter, and is assumed to be realized three experimental CTΔΣM chips reported in the open
using OTA-RC techniques. For the time being, let us literature. The modulators cited here were all designed
assume that the circuitry marked “assistant” does not for the audio band (24 kHz bandwidth), and targeted sim-
2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 373
 ilar resolutions. They were all designed in the same flavor design choice. This was borne out by comparing mea-
of a UMC 180 nm CMOS process, and operated with surement results from three CTΔΣMs designed in the
the same 1.8 V supply. The first, reported in 2008, uses same process and supply voltage, targeting the same
a multi-bit architecture. The second, reported in 2010, bandwidth and similar specifications.
is a single-bit CTΔΣM which uses opamp assistance
to enhance the linearity of the first integrator. The two R EFERENCES
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dissipation, while achieving the same SNDR. A multi-
bit modulator with a sufficiently large number of levels
can be stable for virtually the full scale of the CTΔΣM
, making it attractive in such applications.

V. C ONCLUSIONS

This tutorial paper discussed tradeoffs in the design

of low power CTΔΣMs. For a wide range of resolutions
that occur in practice, it appears that using a single-
bit quantizer and FIR feedback makes for a compelling
374 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)