Department of Electrical Engineering

Faculty Member:____________________ Dated: ________________

Semester:__________________________ Section: ________________

Group No.:

EE-122: Computer Architecture and Digital Logic

Lab 8: Binary Adders and Subtractors

PLO4/ PLO4/ PLO5/ PLO8/ PLO9/

CLO4 CLO4 CLO5 CLO6 CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performan of data in Tool Safety and Team marks
ce Lab Usage Work Obtaine
Report d

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25

Marks
Navaal Iqbal 407799

Amna Ahmed 408099

EE122 Computer Architecture and Logic Design

Lab 8: Binary Adders and Subtractors

This Lab Activity has been designed to familiarize the students with design and working of
binary adders using basic logic gates.

Objectives:

Design and Implementation of Half Adder

Design and Implementation of a Full Adder using Half Adders
Extending the design to add 2-bit binary numbers
Verification of 4-bit adder IC
Gate-Level Verilog code for 4-bit adder

Lab Instructions:

✔ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva
session.
✔ The lab report will be uploaded on LMS before scheduled lab date. Complete the Pre-
lab task before coming to the lab and show it to teacher/lab engineer for subsequent
evaluation. Alternately each group to upload completed lab report on LMS for grading.
✔ The students failing to complete Pre-lab will not be allowed to attend lab session.
✔ The students will start lab task and demonstrate design steps separately for step-wise
evaluation.
✔ Remember that a neat logic diagram with pins numbered and nicely patched circuit will
simplify trouble-shooting/fault diagnostic process.
✔ After completion of lab, the students are expected to unwire the circuit and deposit back
components to lab staff.
✔ The students will complete lab task within the prescribed time and submit complete
report on LMS.
✔ There will be a viva/quiz session after demonstration for which students will be graded
individually.

EE122 Computer Architecture and Logic Design

Pre-Lab Tasks:

1. What do you understand by half and full adders and why are these circuits so named?

Half adder and full adder are combinational logic circuits used in digital electronics to perform
binary addition.

A half adder is a circuit that can add two single binary digits and produce a sum and a carry
output. However, it can't take into account any carry input from the previous stage. A half adder
has two input bits and two output bits.

A full adder, on the other hand, is a circuit that can add two binary digits along with a carry input
from the previous stage and produce a sum and a carry output. A full adder has three input bits
and two output bits.

The reason these circuits are called "half" and "full" adders is because of the number of input bits
they can handle. A half adder can add only two input bits, which is half the number of input bits
that a full adder can handle.

The sum output of a half adder is equal to the XOR of the two input bits, while the carry output is
equal to the AND of the two input bits. The sum output of a full adder is equal to the XOR of the
three input bits, while the carry output is the result of the addition of the three input bits using an
OR gate.

2. Give the truth tables for half adder and half subtractor.

Half Adder

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Half Subtractor:

EE122 Computer Architecture and Logic Design

 A B DIFFERENCE BORROW

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

3. Give the circuit designs for the half adder and half subtractor.

HALF ADDER

HALF SUBTRACTOR:

EE122 Computer Architecture and Logic Design

 4. Design a full adder and full subtractor using the above designed half adders and half
subtractors.

FULL ADDER

Full subtractor

EE122 Computer Architecture and Logic Design

 5. Give the truth tables for the full adder and full subtractor using your circuits.

Full Adder:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1
1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

EE122 Computer Architecture and Logic Design

 Full Subtractor:

A B C/bin Difference Borrow

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Lab Tasks:

Task 1:
_____________________________________________________________
Combine your previously designed full adder and full subtractor into a single circuit that uses a toggle
input T to switch between the addition and subtraction modes. Extend your design to a 4-bit
adder/subtractor
A B C T Sum/difference Carry/borrow
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 1 0
0 0 1 1 1 1
0 1 0 0 1 0
0 1 0 1 1 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 0 1 0 0
1 1 1 0 1 1
EE122 Computer Architecture and Logic Design
 1 1 1 1 1 1

Sum=AB’C’+ABC+A’BC’+A’B’C

=A(B’C’+BC)+A’(BC’+B’C)

=A(B⊕C)’+A’(B⊕, C)

=A⊕B⊕C

CARRY=BC+A’DC+A’BD+ABD’+ACD’

=BC+B(A’D+AD’)+C(A’D+AD’)

=BC+B(A⊕D)+C(A⊕D)

=BC+(B+C)(A⊕D)

EE122 Computer Architecture and Logic Design

Task 2:

____________________________________________________________

The previous designed full adder and subtractor uses addition and subtraction operations separately.
However, in practical situations, it is more convenient to use the addition operation for both adding and
subtracting. This is accomplished by taking a 1’s complement of the second number, adding a 1 to it
and then adding the answer to the first number. Implement this design by modifying the full adder
circuit. Your Proteus simulation must show the design that can add/subtract 4-bit numbers.

EE122 Computer Architecture and Logic Design

EE122 Computer Architecture and Logic Design
Task 3:

____________________________________________________________

Implement your circuit from task 2 in Verilog and show waveforms for both addition and subtraction
modes. You will have to choose the numbers (A and B) for adding/subtracting. Provide the chosen
numbers in the report.

Half adder:
module halfadder(Sum,Carry,A,B);
input A,B;
output Sum,Carry;
wire w1,w2;
assign Carry=A&B;
assign Sum=(~A&B)|(A&~B);
endmodule

halfadder testbench:
module halfaddertestbench;
reg IN1,IN2;
wire CARRY,SUM;
halfadder HA1(SUM,CARRY,IN1,IN2);
initial
begin
#100 IN1=1'b0;IN2=1'b0;
#100 IN1=1'b0;IN2=1'b1;
#100 IN1=1'b1;IN2=1'b0;
#100 IN1=1'b1;IN2=1'b1;
#100;
end
endmodule

fulladder:
module halfaddertestbench;
reg IN1,IN2;
wire CARRY,SUM;
halfadder HA1(SUM,CARRY,IN1,IN2);
initial
begin
#100 IN1=1'b0;IN2=1'b0;
#100 IN1=1'b0;IN2=1'b1;
#100 IN1=1'b1;IN2=1'b0;
#100 IN1=1'b1;IN2=1'b1;
#100;
end

EE122 Computer Architecture and Logic Design

endmodule

fulladder testbench:
module fulladdertestbench;
reg IN1,IN2,IN3;
wire CARRY,SUM;
fulladder FA1(SUM,CARRY,IN1,IN2,IN3);
initial
begin
#100 IN1=1'b0;IN2=1'b0;IN3=1'b0;
#100 IN1=1'b0;IN2=1'b0;IN3=1'b1;
#100 IN1=1'b0;IN2=1'b1;IN3=1'b0;
#100 IN1=1'b0;IN2=1'b1;IN3=1'b1;
#100 IN1=1'b1;IN2=1'b0;IN3=1'b0;
#100 IN1=1'b1;IN2=1'b0;IN3=1'b1;
#100 IN1=1'b1;IN2=1'b1;IN3=1'b0;
#100 IN1=1'b1;IN2=1'b1;IN3=1'b1;
end
endmodule
lab 8:
module lab8(carry_out,S0,S1,S2,S3,A0,A1,A2,A3,B0,B1,B2,B3,T);
input A0,A1,A2,A3,B0,B1,B2,B3,T;
output carry_out,S0,S1,S2,S3;
wire w1,w2,w3,w4;
assign w1=B0^T;
fulladder FA1(S0,C1,A0,w1,1’b0);
assign w2=B1^T;
fulladder FA2(S1,C2,A1,w2,C1);
assign w3=B2^T;
fulladder FA3(S2,C3,A2,w3,C2);
assign w4=B3^T;
fulladder FA4(S3,C4,A3,w4,C3);
endmodule
testbench8:
module testbench8;
reg A0,A1,A2,A3,B0,B1,B2,B3,T;
wire carry_out,S0,S1,S2,S3;
lab8 t1(carry_out,S0,S1,S2,S3,A0,A1,A2,A3,B0,B1,B2,B3,T);
initial
begin
#100 T=0; A0=1'b0;A1=1'b1;A2=1'b0;A3=1'b1;
B0=1'b1;B1=1'b1;B2=1'b0;B3=1'b1;
#100 T=1; A0=1'b1;A1=1'b0;A2=1'b1;A3=1'b1;
B0=1'b1;B1=1'b1;B2=1'b0;B3=1'b1;
#100;
end
EE122 Computer Architecture and Logic Design
endmodule

EE122 Computer Architecture and Logic Design

EE122 Computer Architecture and Logic Design
EE122 Computer Architecture and Logic Design