MOUNIKA.

E
Mail:- elikamounika017@gmail.com
PHONE:6309428213
17, Service Rd, Kallumantapa, Banaswadi,Bengaluru, Karnataka 560043

www.linkedin.com/in/mounika-elika-98852419b
Profile summary

⮚ 6 months certification course in Functional verification from VLSIGuru Institute.

⮚ Expertise on all the aspects verification flow from Spec to verification closure.
⮚ Extensive debug exposure using RTL files, Data flow tracing and schematic
⮚ Expertise in setting up regression flow, generating reports, analyse the failures
⮚ Expertise with coverage report analysis, updating/adding test cases for coverage closure
⮚ Experience of independently handling a block verification.
⮚ Expertise with standard protocols and quick learner
Education

B.Tech, Electronic and Communication Engineering, 2022, CGPA 7.2, Malineni Lakshmaiah
Engineering College.
Diploma, Electronics and Communication Engineering, 2019, 84.4%, Malineni Lakshmaiah
Engineering College.
Skill set

Programming Languages:-Verilog, SV.

Verification Methodologies:- UVM.
Protocols:- AXI, SPI.
EDA Tools:- ModelSim, Questasim, VCS.
Project

 Verification IP Development for AXI protocol using UVM.

o Tool: Questasim
o Duration: 3 months
 AXI is an AMBA protocol used for high performance applications. AXI supports various
features like out of order transactions, burst transfers, cacheble and bufferable
transactions few among various features supported.
 VIP was developed to work as both master and slave. Developed all the VIP components
and validated VIP for various AXI features.
 Responsibilities:-
 Develop VIP Architecture to be compatible with both master and slave behaviour.
 List down AXI features and develop testplan for AXI.
 Develop AXI VIP components
 Integrated AXI Master VIP with slave VIP
 Develop sanity testcases and debug the same
 Develop functional tests and debug the same
 Regression setup and closing of VIP validation using coverage criteria

 Design & verification of memory using SV.

o Tool: Quest Sim.
o Duration :1 month.
 Memory testbench was setup for configurable number of agents.implemented the
concept of semaphore to avoid the conflict from multiple agents concurrent access. Also
Develop the reference model and checker to check memory write read behavior.

Responsibilities:-
 Develop TB architecture to be compatible with configurable number agent.
 List down the design features and develop the testplan.
 Develop and integrate TB components.
 Develop the functional tests and debug the same.

 Design & verification of Asynchronous FIFO using Verilog.

o Tool: ModelSim.
o Duration: 1 month.
 Asynchronous FIFO is used to connect components transmitting and receiving data at
different frequencies. I was responsible for developing the RTL and functional verification
of the same using Verilog.
 FIFO is a design block used for connecting components working at either same or
different frequencies.

Responsibilities
 Understand the functionality of Synchronous and Asynchronous FIFO
 Develop Test bench for Synchronous and Asynchronous FIFO design using Verilog
 Listing down features, scenarios
 Implement various test cases
 Design & verification of SPI Controller using Verilog
o Tool: ModelSim.
o Duration: 1 month.
 SPI Controller is design block that acts as an interface between processor and SPI slaves.
SPI architecture is based on one master and multiple slaves.
 SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers,
address and data, other is SPI interface used for connecting with SPI slaves. SPI uses
SCLK, MOSI, MISO and CS to connect master to slave.

Responsibilities
 SPI protocol, architecture, components, signals
 Understanding the SPI timing diagram
 SPI controller test bench development and test case coding

 Design & verification of Interrupt controller using Verilog

o Tool: ModelSim.
o Duration: 1 month.
 Interrupt is an important aspect of processor and peripheral communication in any SOC. This
project focused on learning Interrupt controller verilog coding and TB development.

Responsibilities
 Understand the important of Interrupt in an SOC
 Understand how the interrupt logic works in processor and peripheral communication
 Develop the Interrupt controller architecture with processor and peripheral interfacing
 Develop the Verilog code for Interrupt controller
 Learn the concept of setting up test bench for complex design
 Develop different test cases for various interrupt handling possibilities

 Clock is important aspect of every electronic design.

o This project focused on understanding clock generation for a user provided frequency,
duty cycle and jitter.
Responsibilities
 Understand the important of clock in electronic designs
 Understand how to convert frequency to time period, Hz/KHz/MHz/GHz to
sec/ms/us/ns/ps
 Learn usage of $value$plusargs for reading user arguments
 Develop TB for clock generation logic checking
 Understand importance of time step in clock generation logic
  B.tech project
 Vehicle anti theft and alocohol detection system.
 When the key is turned on, switch signal also turns on . Alcohol sensor connected to
Microcontroller circuit gets activated, and checks for range. If range is above minimum
value it sends an message to registered number through GSM module & it stops the
working of motor automatically.
 If any one trying to stolen the vehicle with another key then the switch is pressed and it
send the signal to the microcontroller. controller sends a message to the requested
number through the GSM module. If the person replied to that message then the motor
is stops.

Personal Information

Date of Birth : 26th,march 2001

Current location :Bangalore.
Languages Known : Telugu, English.