CXA1372BQ/BS

RF Signal Processing Servo Amplifier for CD Player

Description
CXA1372BQ CXA1372BS
The CXA1372BQ/BS is a bipolar IC developed for
48 pin QFP (Plastic) 48 pin SDIP (Plastic)
RF signal processing (focus OK, mirror, defect
detection, EFM comparator) and various servo
control.

Features
• Dual ±5V and single 5V power supplies
• Low power consumption
• Fewer external parts
Absolute Maximum Ratings (Ta = 25°C)
• Disc defect countermeasure circuit
• Supply voltage VCC – VEE 12 V
• Fully compatible with the CXA1182 for microcomputer
• Operating temperature
software
Topr –20 to +75 °C
• Storage temperature
Functions
Tstg –65 to +150 °C
• Auto asymmetry control
• Allowable power dissipation
• Focus OK detection circuit
PD 457 (CXA1372BQ) mW
• Mirror detection circuit
833 (CXA1372BS) mW
• Defect detection, countermeasure circuit
• EFM comparator
Recommended Operating Conditions
• Focus servo control
VCC – VEE 3.6 to 11 V
• Tracking servo control
VCC – DGND 3.6 to 5.5 V
• Sled servo control

Structure
Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E95927A67-PS
 CXA1372BQ/BS

Block Diagram

C. OUT
DGND

SENS
DFCT

XRST
MIRR
DVcc

EFM
CC1

FOK
CC2

ASY
36 35 34 33 32 31 30 29 28 27 26 25

• IIL
↓
• TTL

24 DATA
CB 37

CP 38 23 XLT
• TTL
RFI 39 ↓ 22 CLK
• IIL

RFO 40 21 LOCK
• IIL DATA REGISTER
• TTL • INPUT SHIFT REGISTER
• ADDRESS DECODER 20 DIRC
DVEE 41 ↓
• IIL
• OUTPUT DECODER

TZC 42
• FS1 to 4 • TG1 to 2 • TM1 to 7 • PS1 to 3
19 AVEE
DFCT
TE 43 TG1 • TRACKING
PHASE COMPENSATION
TDFCT 44 18 SSTOP
TM1
• I SET 17 ISET
ATSC 45 • BPF • WINDOW COMPARATOR
• F SET 16 FSET
• FOCUS TM6
PHASE
COMPENSATION TM5 15 SL–
FZC 46
DFCT FS1 TM7
FE 47
TM4 14 SLO
FDFCT 48
TM3 13 SL+
FS4 TM2
FS3 FS2

TG2

1 2 3 4 5 6 7 8 9 10 11 12
FGD

TG2
FEO

TAO
FLB

SRCH
FE–

AVCC
TGU
VC

TA–
FS3

–2–
 CXA1372BQ/BS

Pin Configuration

CXA1372BQ

C. OUT
DGND

SENS
DFCT

XRST
MIRR
DVcc

FOK

EFM

ASY
CC2

CC1
36 35 34 33 32 31 30 29 28 27 26 25

CB 37 24 DATA

CP 38 23 XLT

RFI 39 22 CLK

RFO 40 21 LOCK

DVEE 41 20 DIRC

TZC 42 19 AVEE
CXA1372BQ
TE 43 18 SSTOP
TDFCT 44 17 ISET
ATSC 45
16 FSET
FZC 46
15 SL–
FE 47
14 SLO
FDFCT 48
13 SL+

1 2 3 4 5 6 7 8 9 10 11 12
TA–
FEO
FS3

AVcc

TAO
SRCH
FE–
VC

FLB

TGU
FGD

TG2

CXA1372BS
C. OUT
DGND

LOCK
DATA
SENS
DFCT

XRST
MIRR
DVEE

DIRC

AVEE
DVcc
RFO

FOK

EFM
CC2
TZC

CC1

CLK
ASY

XLT
RFI

CP

CB

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CXA1372BS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FGD

FLB

FE–
FS3
TE

SRCH

SSTOP
FE

TG2
TDFCT

TGU

FSET
TZC

AVcc
ATSC

SLO
VC

SL+

ISET
FDFCT

TAO

SL–
FEO

TA–

–3–
 CXA1372BQ/BS

Pin Description
Pin No.
Symbol I/O Equivalent circuit Description
Q S
Center voltage input.
For dual power supplies: GND
1 7 VC I
For single power supply:
(VCC + GND)/2

Vcc

147 48k Connects a capacitor between this

2 8 FGD I 2 pin and Pin 3 to cut high-frequency
130k gain.
20µA
VEE

46k 580k The high-frequency gain of the

3 9 FS3 I 3 focus servo is switched through FS3
ON and OFF.

40k External time constant to boost the

4 10 FLB I 4
low frequency of the focus servo.

5 11 FEO O Focus drive output.

11 17 TAO O 11 Tracking drive output.

14 250µA

2.5µA
14 20 SLO O Sled drive output.

90k
147
6 12 FE– I 6 Inverted input for focus amplifier.
40k
2.5µA

–4–
 CXA1372BQ/BS

Pin No.
Symbol I/O Equivalent circuit Description
Q S

147
I External time constant for forming
7 13 SRCH 7
the focus search waveforms.
50k 3.5µA 11µA

110k
20k External time constant for selecting
8 14 TGU I 8
the tracking high-frequency gain.
82k

147 External time constant for selecting

9 15 TG2 I 9
the tracking high-frequency gain.
470k

90k
147
12 18 TA– I 12 Inverted input for tracking amplifier.

3µA 11µA

10k
13 19 SL+ I 13 Non-inverted input for sled amplifier.

147
15 21 SL– I 15 Inverted input for sled amplifier.

3µA 22µA

–5–
 CXA1372BQ/BS

Pin No.
Symbol I/O Equivalent circuit Description
Q S

147 Sets the peak frequency of focus

16 22 FSET I 16
tracking phase compensation.
15k 15k

147 Current is input to determine focus

17 23 ISET I 17 search, track jump, and sled kick
level.

7µA

147 Limit SW ON/OFF signal detection

18 24 SSTOP I 18 for disc innermost track detection.

Used for 1-track jump. Contains a

20 26 DIRC I
47kΩ pull-up resistor.

At "Low" sled overrun prevention

21 27 LOCK I circuit operates. Contains a 47kΩ
20 pull-up resistor.
15µA
21 47k
147 Serial data transfer clock input from
22 28 CLK I 22
CPU. (no pull-up resistor)
23
24
Latch input from CPU.
23 29 XLT I 25
(no pull-up resistor)
Serial data input from CPU.
24 30 DATA I
(no pull-up resistor)
Reset input, reset at "Low".
25 31 XRST I
(no pull-up resistor)

26 32 C. OUT O Track number count signal output.

20k
147
26
27
Outputs FZC, AS, TZC and SSTOP
27 33 SENS O 100k through command from CPU.

–6–
 CXA1372BQ/BS

Pin No.
Symbol I/O Equivalent circuit Description
Q S

MIRR comparator output.

29 35 MIRR O 147 (DC voltage: 10kΩ load connected)
38

147
29 Connects MIRR hold capacitor.
20k
38 44 CP I Non-inverted input for MIRR
comparator.

34 40 CC1 O DEFECT bottom hold output.

147
147 35
37

Input for DEFECT bottom hold

35 41 CC2 I
output with capacitance coupled.

DEFECT comparator output.

30 36 DFCT O 147
30 147 (DC voltage: 10kΩ load connected)
34

Connects DEFECT bottom hold

37 43 CB I
capacitor.

147
31 37 ASY I 31 Auto asymmetry control input.

32 4.8k

EFM comparator output.

32 38 EFM O
(DC voltage: 10kΩ load connected)
Current source depending on
power supply
(VCC to DGND)

20k
147
33 FOK comparator output.
33 39 FOK O
(DC voltage: 10kΩ load connected)

–7–
 CXA1372BQ/BS

Pin No.
Symbol I/O Equivalent circuit Description
Q S

Input for RF summing amplifier

39 45 RFI I
output with capacitance coupled.
40k

147
39

RF summing amplifier output.

40 46 RFO O 147
40 Check point of eye pattern.

7µA

147
42 Tracking zero-cross comparator
42 48 TZC I input.
75k

147 470k
43 1 TE I 43 Tracking error input.

147
44 Connects a capacitor for time
44 2 TDFCT I
constant during defect.

Vcc

470k
45
Window comparator input for ATSC
45 3 ATSC I
detection.
330k 47P

VEE

60k
46 4 FZC I 147 Focus zero-cross comparator input.
46
1.2k

147 470k
47 5 FE I 47
Focus error input.

147
48
Connects a capacitor for time
48 6 FDFCT I
constant during defect.

–8–
 Electrical Characteristics (Ta = 25°C, VCC = 2.5V, VEE = –2.5V, D. GND = –2.5V)

SW condition Bias condition Measure- Description of output

No. Item Symbol SD ment waveform and measurement Min. Typ. Max. Unit
S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point method
1 Current consumption ICC 00 10, 36 8 19 27 mA
2 Current consumption IEE 00 19, 41 –24 –17 –8 mA
V1 = 10Hz, 100mVp-p
3 DC voltage gain GFEO 08 5 18.0 21.0 24.0 dB
GFEO = 20 log (Vout/Vin)
SG = 10kHz, 40mVp-p
4 Feedthrough VFEOF 00 5 Difference in gain when –35 dB
SD = 00 and SD = 08
5 Max. output voltage VFE01 O 08 5 V1 = 0.5VDC 2.0 V
6 Max. output voltage VFE02 O 08 5 V1 = –0.5VDC –2.0 V
7 Max. output voltage VFE03 O O 08 5 V1 = 0.5VDC 1.2 V
8 Max. output voltage VFE04 O O 08 5 V1 = –0.5VDC –1.2 V

FOCUS SERVO
9 Search output voltage VSRCH1 02 5 –640 –360 mV

–9–
10 Search output voltage VSRCH2 03 5 360 640 mV
∗(VCC + DGND)/2 = SENS
11 FZC threshold value VFZC 00 ∗ 27 39 50 61 mV
value when E4 is varied.
V2 = 10Hz, –500mVp-p
12 DC voltage gain GTEO 25 11 11.6 13.3 17.6 dB
GTEO = 20 log (Vout/Vin)
V2 = 10kHz, 40mVp-p
13 Feedthrough VTEOF 00 11 Difference in gain when –39 dB
SD = 00 and SD = 25
14 Max. output voltage VTE01 O 25 11 V2 = –0.5VDC 2.0 V
15 Max. output voltage VTE02 O 25 11 V2 = 0.5VDC –2.0 V
16 Max. output voltage VTE03 O O 25 11 V2 = –0.5VDC 1.2 V

TRACKING SERVO
17 Max. output voltage VTE04 O O 25 11 V2 = 0.5VDC –1.2 V
18 Jump output voltage VJUMP1 2C 11 –640 –360 mV
19 Jump output voltage VJUMP2 28 11 360 640 mV
CXA1372BQ/BS
 SW condition Bias condition Measure- Description of output
No. Item Symbol SD ment waveform and measurement Min. Typ. Max. Unit
S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point method
20 ATSC threshold value VATSC1 10 ∗ 27 ∗(VCC + DGND)/2 = SENS –45 –26 –7 mV
21 ATSC threshold value VATSC2 10 27 value when E3 is varied. 7 26 45 mV

SERVO
∗(VCC + DGND)/2 = SENS

TRACKING
22 TZC threshold value VTZC 20 ∗ 27 –20 0 20 mV
value when E2 is varied.
V5 = 10Hz, 20mVp-p
23 DC voltage gain GSLO 25 14 50 dB
Open loop gain
V5 = 10kHz, 100mVp-p
24 Feedthrough VSLOF 00 14 Difference in gain when –34 dB
SD = 00 and SD = 25
25 Max. output voltage VSL01 25 14 V5 = 1.0VDC 2.0 V
26 Max. output voltage VSL02 25 14 V5 = –1.0VDC –2.0 V
27 Max. output voltage VSL03 O 25 14 V5 = 1.0VDC 2.0 V

SLED SERVO
28 Max. output voltage VSL04 O 25 14 V5 = –1.0VDC –2.0 V

– 10 –
29 Kick output voltage VKICK1 23 14 –750 –450 mV
30 Kick output voltage VKICK2 22 14 450 750 mV
SSTOP threshold ∗(VCC + DGND)/2 = SENS
31 VSSTOP 30 ∗ 27 –40 –25 –10 mV
value value when E1 is varied.
32 SENS Low level VSENS 27 –2.0 V
33 COUT Low level VCOUT 26 –2.0 V
(VCC + DGND)/2 = value
34 FOK threshold value VFOKT 33 between Pins 39 and 40 –400 –356 –330 mV
when V4 is varied.
35 High level voltage VFOKH 33 2.2 V

FOK
36 Low level voltage VFOKL 33 V4 = 1Vp-p – 375mVDC –1.8 V
37 Max. operating frequency FFOK 33 45 kHz
CXA1372BQ/BS
 SW condition Bias condition Measure- Description of output
No. Item Symbol SD ment waveform and measurement Min. Typ. Max. Unit
S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point method
38 High level voltage VMIRH 29 V4 = 10kHz 1.8 V
39 Low level voltage VMIRL 29 1.0Vp-p – 0.4VDC –2.0 V
Max. operating
40 FMIR 29 V4 = 800mVp-p – 0.4VDC 30 kHz
frequency
Min. input operating

MIRROR
41 VMIR1 29 0.3 Vp-p
voltage
V4 = 10kHz – 0.4VDC
Max. input operating
42 VMIR2 29 1.8 Vp-p
voltage
High level output
43 VDFCTH 30 1.8 V
voltage
Low level output
44 VDFCTL 30 –2.0 V
voltage
Min. operating
45 FDFCT1 30 1 kHz
frequency
V4 = 0.8Vp-p + 375mVDC
Max. operating

– 11 –
46 FDFCT2 30 2.5 kHz

DEFECT
frequency
Min. input operating
47 VDFCT1 30 0.5 Vp-p
voltage V4 = 50Hz + 375mVDC
Max. input operating (square wave)
48 VDFCT2 30 1.8 Vp-p
voltage

49 Duty 1 DEFM1 O 31 V4 = 750kHz, 0.7Vp-p –50 0 50 mV

V4 = 750kHz,
50 Duty 2 DEFM2 O 31 0 50 100 mV
0.7Vp-p + 0.25VDC

51 High level output VEFMH O O 32 1.2 V

voltage
V4 = 750kHz, 0.7Vp-p
Low level output

EFM
52 VEFML O O 32 –1.2 V
voltage

53 Min. input operating VEFM1 O A 0.12 Vp-p

voltage
V4 = 750kHz
Max. input operating
CXA1372BQ/BS

54 VEFM2 O A 1.8 Vp-p

voltage
 CXA1372BQ/BS

Electric Characteristics Measurement Circuit

A
Vcc DGND DGND

0.01µ

1k

DGND
10k

10k

1M
DVcc DGND DGND DGND Vcc Vcc Vcc

S8
S9
3300P

10k
10k

10k

10k
A

36 35 34 33 32 31 30 29 28 27 26 25
CC2

MIRR
EFM

SENS
CC1

ASY

C. OUT
DVcc

XRST
DFCT
FOK

DGND
37 CB DATA
DATA 24
DGND 1000P
38 CP
XLT 23 XLT
DGND 3300P
39 RFI
+ V4 CLK 22 CLK

Vcc GND GND AVEE Vcc Vcc

40 RFO
AC V3 LOCK 21

GND DIRC 20
AC
GND
DVEE

A 41 DVEE AVEE 19 A

E1
42 TZC SSTOP 18
E2

GND 43 TE ISET 17
+ V2 240k
44 TDFCT FSET 16
AC 510k
0.1µ

GND 5.1k
GND SL– 15
45 ATSC
60k

130

GND
E3

GND 46 FZC SLO 14

S7
E4

13k
GND 47 FE SL+ 13
+ V1 + V5
48 FDFCT
SRCH

AC AC
AVcc
FGD

TAO
TGU
FEO

TG2
FS3

FE–

TA–
FLB
0.1µ

VC

GND GND
1 2 3 4 5 6 7 8 9 10 11 12
GND 100k
1000P

100k
0.1µ

0.033µ
A
S1 S2 S4 S5
200k 200k
S3

AVcc
130 S6
130

13k
13k

GND GND GND GND

– 12 –
 CXA1372BQ/BS

Description of Functions

Focus Servo

1.2k

56k

FZC FZC
FE 46
10k
22k 47
2200p FE DFCT
470k 20k 48k
FEO FOCUS COIL
Focus Phase 5
48 Compensation
0.1µ FDFCT FS4 100k
FGD
2 FS2 40k FE–
0.1µ 46k 6
3 40k 120k
11µ 22µ
FS3 580k FS3 10k
ISET 120k
17

50k
FS1 DGND
FLB FSET SRCH
4 16 7

0.1µ 510k 0.01µ 4.7µ

The above figure shows a block diagram of the focus servo.

Ordinarily the FE signal is input to the focus phase compensation circuit through a 20kΩ and 48kΩ resistance;
however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the
internal 470kΩ resistance and the capacitance connected to Pin 48. When this DFCT countermeasure circuit is
not used, leave Pin 48 open.
When FS3 is ON, the high-frequency gain can be cut by forming a low-frequency time constant through a
capacitor connected between Pins 2 and 3 and the internal resistor.
The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 16.
The focus search level is approximately ±1.1Vp-p when using the constants indicated in the above figure. This
level is inversely proportional to the resistance connected between Pin 17 and GND. However, changing this
resistance also changes the level of the track jump and sled kick as well.
The FZC comparator inverted input is set to 2% of VCC and VC (Pin 1); (VCC – VC) × 2%.
∗ 510kΩ resistance is recommended for Pin 16.

– 13 –
 CXA1372BQ/BS

Tracking Sled Servo

100k

0.022µ 18
TZC SSTOP
42 SSTOP
TZC 100k
1k
100k SLED MOTOR
SLO
14 M
0.047µ ATSC
1k 0.015µ
45 ATSC 22µA
SL– 120k 8.2k
BPF 1k
15
TM6
10k SL+ 3.3µ
TE TM5 22µA 13
43 100k
22µ
11µA
DFCT TM2
TE 470k
82k 15k
22k 680K TM4 TA–
680k
44 12
0.1µ TDFCT TG1 TG1 TM3 100k
66P 11µA
10k
TM1 10k TRACKING
90k
Tracking COIL
TGU TAO
8 Phase 11
20k Compensation
0.033µ
TG2 TG2 TM7
9

470k
FSET
16

510k

0.01µ

The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance connected to Pin 16.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
GND. When this resistance is 120kΩ:
TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
This current value is almost inversely proportional to the resistance and the variable range is approximately 5
to 40µA at TM3.
SSTOP is the ON/OFF detection signal for the limit SW of the linear motor's innermost track.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (470kΩ) and the capacitor connected to Pin 44.
TM-1 was ON at DFCT in the CXA1082 and CXA1182, but it does not operate in the CXA1372.

– 14 –
 CXA1372BQ/BS

Focus OK circuit

VCC

RFO 20k
RF signal 40 54k
C5 ×1
0.01µ 33 FOK
39 VG
RFI
15k 92k

0.625V

FOCUS OK AMP FOCUS OK

COMPARATOR

The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 39 from Pin 40 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constants of the HPF for the EFM comparator and mirror circuit and the LPF
of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block
error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.

EFM comparator
EFM comparator changes RF signal to a binary value. The asymmetry generated due to variations in disc
manufacturing cannot be eliminated by the AC coupling alone. Therefore, the reference voltage of EFM
comparator is controlled through 1 and 0 that are in approximately equal numbers in the binary EFM signals.

VC
AUTO ASYMMETRY
CONTROL AMP ASY R8 R9
100k 20k
31
×6 C8 C9

CMOS
Vcc AUTO ASYMMETRY DGND = 0V BUFFER
40k 40k BUFFER

32 CXD2500
RFI 39
EFM
EFM COMPARATOR

As this comparator is a current SW type, each of the High and Low levels is not equal to the power supply
voltage. A feedback has to be applied through the CMOS buffer.
R8, R9, C8, and C9 form a LPF to obtain (VCC + DGND)/2V. When fc (cut-off frequency) exceeds 500Hz, the
EFM low-frequency components leak badly, and the block error rate worsens.

– 15 –
 CXA1372BQ/BS

DEFECT circuit
After inversion, RFI signal is bottom held by means of the long and short time constants. The long time-
constant bottom hold keeps the mirror level prior to the defect.
The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms, and this is
differentiated and level-shifted through the AC coupling circuit.
The long and short time-constant signals are compared to generate at mirror defect detection signal.

0.033µ
CC1 CC2
34 35

a
RFO 40 b c
×2 e
30 DFCT
d

DEFECT AMP DEFECT BOTTOM DEFECT COMPARATOR

37 HOLD
CB
0.01µ

a RFO

b DEFECT
AMP

BOTTOM
c HOLD (1); d BOTTOM
Solid line CC1 HOLD (2);
Dotted line CC2
H
e DEFECT
L

– 16 –
 CXA1372BQ/BS

Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the
rotation cycle envelope fluctuation.

RFO
MIRROR HOLD AMP
0.033µ
38
H CP
39 PEAK &
RFI × 2.2 BOTTOM ×1
G HOLD J
I K
MIRROR AMP

29
20k MIRR
MIRROR
COMPARATOR DGND

RFO

0V

G
(RFI) 0V

H
(PEAK HOLD)
0V

I
(BOTTOM HOLD) 0V

J
K
(MIRROR HOLD)

H
MIRR
L

Through differential amplification of the peak and bottom hold signals H and I, mirror output can be obtained by
comparing an envelope signal J (demodulated to DC) to signal K for Which peak holding at a level 2/3 that of
the maximum was performed with a large time constant. In other words, mirror output is low for tracks on the
disc and high for the area between tracks (the MIRR areas). In addition, a high signal is output when a defect
is detected. The mirror hold time constant must be sufficiently large in comparison with the traverse signal.

– 17 –
 CXA1372BQ/BS

Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1372 can be broadly divided into four groups ranging in value from $0X to $3X.

1. $0X (“FZC” at SENS (Pin 27))

These commands are related to focus servo control.

The bit configuration is as shown below.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 FS4 FS3 FS2 FS1

Four focus-servo related switches exist: FS1 to FS4 corresponding to D0 to D3, respectively.

$00 When FS1 = 0, Pin 7 is charged to (22µA – 11µA) × 50kΩ = 0.55V.

If FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V.
$02 From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 5. This voltage level is obtained by equation 1 below.

(22µA – 11µA) × 50kΩ × resistance between Pins 5 and 6 .... Equation 1

50kΩ

$03 From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as
shown in Fig. 1 below.

0V

Fig. 1. Voltage at Pin 7 when FS1 gose from 0 → 1

This time constant is obtained with the 50kΩ resistance and an external capacitor.

By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)

0V

$ 00 02 03 02 03 02 00

Fig. 2. Constructing the search voltage by alternating between $02 and $03 (Voltage at Pin 5)

– 18 –
 CXA1372BQ/BS

1-1. FS4
This switch is provided between the focus error input (Pin 47) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.

$00 → $08
Focus OFF ← Focus ON

1-2. Procedure of focus activation

For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 5) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.

Fig. 3. S-curve

The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and
turning the focus servo switch ON are performed when the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 27) as the point A transit signal.
Focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.

(20ms) (200ms)
$02
($00) $03 $08

Drive voltage

∗ The broken lines in the figure

indicate the voltage assuming
the signal is not in focus.
Focus error

SENS pin
(FZC)

The instant the signal is brought into focus.

Focus OK

Fig. 4. Focus ON timing chart

– 19 –
 CXA1372BQ/BS

Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.

FZC ↓ ? Transfer $08

NO
YES

F. OK ? F. OK ?
NO NO
YES YES

Transfer $08 FZC ↓ ?

NO
YES

Latch Latch

(A) (B)

Fig. 5. Poor and good software command sequences

1-3. SENS (Pin 27)

The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: AS
$2X: TZC
$3X: SSTOP
$4X to 7X: HIGH-Z

2. $1X (“AS” at SENS (Pin 27))

These commands deal with switching TG1 and TG2 ON/OFF.

The bit configuration is as follows
D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 ANTI Break TG2 TG1

SHOCK circuit
ON/OFF ON/OFF

TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. The brake circuit (TM7) is to
prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually
though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by
the servo motor exceeding the linear range after a 100 or 10-track jump.
When the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc
and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the
tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking.

– 20 –
 CXA1372BQ/BS

[∗A] [∗B] D2
Envelope Waveform (MIRR)
RFI 39
Detection Shaping [∗C] [∗G] TM7
DQ Low: open
BRK
[∗D] [∗E] [∗F]
Tracking error High: make
CK
(TZC) 42 Waveform Edge Detection [∗H]
Shaping (Latch)

Fig. 6. TM7 operation (brake circuit)

From inner to outer track From outer to inner track

[∗A]

[∗B]

[∗C] ("MIRR")

[∗D]
("TZC")
[∗E]

[∗F]

[∗G]

Braking is
[∗H]
applied from
0V
here.

Fig. 7. Internal waveform

3. $2X (“TZC” at SENS (Pin 27))

These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 Tracking Sled
control control
00: OFF 00: OFF
01: Servo ON 01: Servo ON
10: F-JUMP 10: F-FAST FORWARD
11: R-JUMP 11: R-FAST FORWARD
↓ ↓
TM1, TM3, TM4 TM2, TM5, TM6

– 21 –
 CXA1372BQ/BS

DIRC (Pin 20) and 1 Track Jump

Normally, an acceleration pulse is applied for a 1-track jump. Then a deceleration pulse is given for a specified
time observing the tracking error from the moment it passes point 0, and tracking servo is turned ON again.
For the 100-track jump to be explained in the next item, as long as the number of tracks is about 100 there is
no problem. However a 1-track jump must be performed here, which requires the above complicated
procedure. For the 1-track jump in CD players, both the acceleration and deceleration take about 300 to
400µs. When software is used to execute this operation, it turns out as shown in the flow chart of Fig. 9.
Actually, it takes some time to transfer data.
Deceleration
Pulse waveform
Acceleration

Tracking error

Fig. 8. Pulse waveform and tracking error of 1-track jump

TR: REV TR: REV

$2C transfer latch Execute $2C transfer latch Execute
SL: OFF SL: OFF

TR: FWD
$28 transfer only

AAA AAAA
SL: OFF

AAA TZC ↓ ?

YES
NO

Execute
AAAA TZC ↓ ?

YES
NO

TR: FWD
Latch DIRC = L
SL: OFF

Timer (0.3ms) Timer (0.3ms)

TR: ON TR: ON
$25 transfer latch Execute DIRC = H
SL: ON SL: ON

Fig. 9. 1-track jump not using DIRC (Pin 20) Fig. 10. 1-track jump with DIRC (Pin 20)

The DIRC (Direct Control) pin was provided in this IC to facilitate the 1-track jump operation. Conduct the
following process to perform 1-track jump using DIRC (normal High).
(a) Acceleration pulse is output. ($2C for REV or $28 for FWD).
(b) With TZC ↓ (or TZC ↑), set DIRC to Low. (SENS Pin 27 outputs "TZC"). As the jump pulse polarity is
inverted, deceleration is applied.
(c) Set DIRC to High after a specific time.
Both the tracking servo and sled servo are switched ON automatically.
As a result, the track jump turns out as shown in the flow chart of Fig. 10 and the two serial data transfers
can be omitted.

– 22 –
 CXA1372BQ/BS

4. $3X
This command selects the focus search and sled kick levels.
D0, D1 ..... Sled, NORMAL feed, high-speed feed
D2, D3 ..... Focus search level selection

Focus search level Sled kick level

Relative
D7 D6 D5 D4 D3 D2 D1 D0 value
(PS4) (PS3) (PS2) (PS1)
0 0 0 0 ±1
0 1 0 1 ±2
0 0 1 1
1 0 1 0 ±3
1 1 1 1 ±4

– 23 –
 CXA1372BQ/BS

Parallel Direct Interface

1. DIRC

$28 latch $2C latch

XLT

DIRC

ON
FWD JUMP OFF

ON
REV JUMP OFF

TRACK SERVO ON
OFF

SLED SERVO ON
OFF

2. LOCK (Sled overrun prevention circuit)

LOCK

SLED SERVO ON
OFF

TG1, TG2 ON
OFF
UP
TRACKING GAIN DOWN

– 24 –
 CXA1372BQ/BS

CPU Serial Interface Timing Chart

DATA D0 D1 D2 D3 D4 D5 D6 D7
tWCK tWCK tSU th

CLK
1/fck

tD
XLT
tWL

(DVCC – DGND = 4.5 to 5.5V)

Item Symbol Min. Typ. Max. Unit
Clock frequency fck 1 MHz
Clock pulse width fwck 500 ns
Setup time tsu 500 ns
Hold time th 500 ns
Delay time tD 1000 ns
Latch pulse width tWL 1000 ns

System Control
Address Data SENS
Item
D7 D6 D5 D4 D3 D2 D1 D0 output

FS4 FS3 FS2 FS1

Focus control 0 0 0 0 Focus Gain Search Search FZC
ON Down ON Up
Tracking Brake TG2 TG1
0 0 0 1 Anti-shock A. S
control ON Gain set ∗1
Tracking mode 0 0 1 0 ∗
Tracking mode 2 Sled mode ∗3 TZC
PS4 PS3
PS2 PS1
Select 0 0 1 1 Focus Focus SSTOP
Sled kick + 2 Sled kick + 1
search + 2 search + 1
∗1 Gain set
TG1 and TG2 can be set independently.
When the anti-shock is at 1 (00011xxx), both TG1 and TG2 are inverted when the internal anti-shock is at High.

∗2 Tracking mode ∗3 Sled mode

D3 D2 D1 D0
OFF 0 0 OFF 0 0
ON 0 1 ON 0 1
FWD JUMP 1 0 FWD MOVE 1 0
REV JUMP 1 1 REV MOVE 1 1

– 25 –
 CXA1372BQ/BS

Serial Data Truth Table

Serial data Hex. Function
FOCUS CONTROL FS = 4 3 2 1
0 0 0 0 0 0 0 0 $00 0 0 0 0
0 0 0 0 0 0 0 1 $01 0 0 0 1
0 0 0 0 0 0 1 0 $02 0 0 1 0
0 0 0 0 0 0 1 1 $03 0 0 1 1
0 0 0 0 0 1 0 0 $04 0 1 0 0
0 0 0 0 0 1 0 1 $05 0 1 0 1
0 0 0 0 0 1 1 0 $06 0 1 1 0
0 0 0 0 0 1 1 1 $07 0 1 1 1
0 0 0 0 1 0 0 0 $08 1 0 0 0
0 0 0 0 1 0 0 1 $09 1 0 0 1
0 0 0 0 1 0 1 0 $0A 1 0 1 0
0 0 0 0 1 0 1 1 $0B 1 0 1 1
0 0 0 0 1 1 0 0 $0C 1 1 0 0
0 0 0 0 1 1 0 1 $0D 1 1 0 1
0 0 0 0 1 1 1 0 $0E 1 1 1 0
0 0 0 0 1 1 1 1 $0F 1 1 1 1
AS = 0 AS = 1
TRACKING CONTROL
TG = 2 1 TG = 2 1
0 0 0 1 0 0 0 0 $10 0 0 0 0
0 0 0 1 0 0 0 1 $11 0 1 0 1
0 0 0 1 0 0 1 0 $12 1 0 1 0
0 0 0 1 0 0 1 1 $13 1 1 1 1
0 0 0 1 0 1 0 0 $14 0 0 0 0
0 0 0 1 0 1 0 1 $15 0 1 0 1
0 0 0 1 0 1 1 0 $16 1 0 1 0
0 0 0 1 0 1 1 1 $17 1 1 1 1
0 0 0 1 1 0 0 0 $18 0 0 1 1
0 0 0 1 1 0 0 1 $19 0 1 1 0
0 0 0 1 1 0 1 0 $1A 1 0 0 1
0 0 0 1 1 0 1 1 $1B 1 1 0 0
0 0 0 1 1 1 0 0 $1C 0 0 1 1
0 0 0 1 1 1 0 1 $1D 0 1 1 0
0 0 0 1 1 1 1 0 $1E 1 0 0 0
0 0 0 1 1 1 1 1 $1F 1 1 0 1
DIRC = 1 DIRC = 0 DIRC = 1
TRACKING MODE
TM = 654321 654321 654321
0 0 1 0 0 0 0 0 $20 000000 001000 000011
0 0 1 0 0 0 0 1 $21 000010 001010 000011
0 0 1 0 0 0 1 0 $22 010000 011000 100001
0 0 1 0 0 0 1 1 $23 100000 101000 100001
0 0 1 0 0 1 0 0 $24 000001 000100 000011
0 0 1 0 0 1 0 1 $25 000011 000110 000011
0 0 1 0 0 1 1 0 $26 010001 010100 100001
0 0 1 0 0 1 1 1 $27 100001 100100 100001
0 0 1 0 1 0 0 0 $28 000100 001000 000011
0 0 1 0 1 0 0 1 $29 000110 001010 000011
0 0 1 0 1 0 1 0 $2A 010100 011000 100001
0 0 1 0 1 0 1 1 $2B 100100 101000 100001
0 0 1 0 1 1 0 0 $2C 001000 000100 000011
0 0 1 0 1 1 0 1 $2D 001010 000110 000011
0 0 1 0 1 1 1 0 $2E 011000 010100 100001
0 0 1 0 1 1 1 1 $2F 101000 100100 100001
– 26 –
 Application Circuit

FE
TE
RF
LDON
VCC
VO
VCC
GND
VDD
MUTE
SCOR
SQCK
SUBQ
GFS
CLK
XLT
DATA
XRST
SENS
FOK
LDON
GND
GND

RV1
FE
RV2
TE
GND
GND
RF
GND

GND GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
MIRR

VDD

SEIN
CNIN
XLAT
GND

MIRR
XLTO
C15

DATA
XRST

CLKO
SENS
EXCK

CLOK

DATO
MUTE
SQCK
SQSO

C16 C17 1 FOK SBSO 64

C11

C12
C13
C14
2 FSW SCOR 63

TD
SLD
FD
SPD
48 47 46 45 44 43 42 41 40 39 38 37 3 MON WFCK 62 WFCK
4 MDP EMPH 61

FE
TE
CP
CB

RFI

FZC
TZC
RFO
DVEE

ATSC
5 MDS DOUT 60 DOUT

FDFCT
TDFCT
1 VC DVCC 36 6 LOCK MD2 59
TRACK-D

GND
2 FGD CC2 35 7 NC C16M 58
GND C9
R1
3 FS3 CC1 34 8 VCOO C4M 57 GND
FOCUS-D
4 FLB FOK 33 9 VCOI FSTT 56
GND

GND
C10 PCM
5 FEO EFM 32 10 TEST XTSL 55
SLED-D
GND

6 FE– ASY 31 11 PDO XTAO 54

GND C23 CXA1372BQ DFCT
7 SRCH DFCT 30 12 VSS CXD2500AQ XTAI 53
SPIND-D

GND GND GND

GND
GND GND

8 TGU MIRR 29 13 NC VSS 52

GND
GND

C26
9 TG2 DGND 28 14 NC APTL 51
SSTOP

GND

– 27 –
10 AVCC SENS 27 15 NC APTR 50
GND
11 TA0 C.OUT 26 16 VPCO MNT0 49 MNT0
R1
12 TA– XRST 25 17 VCKI MNT1 48 MNT1

GND 18 FILO MNT2 47 MNT2

R7 19 FILI MNT3 46 MNT3

SL+
SL0
SL–
FSET
ISET
SSTOP
AVEE
DIRC
LOCK
CLK
XLT
DATA
13 14 15 16 17 18 19 20 21 22 23 24 20 PCO XRAOF 45 XRAOF GND
GND

C28
C27 21 AVSS C2PO 44
GND

R6 R4 R3 22 CLTV RFCK 43 RFCK

23 AVDD GFS 42 GFS
GND GND
24 RF XPLCK 41 XPLCK
GND
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK (48)
LRCK (48)
VDD
DATA (48)
BCLK (48)
DATA (64)
BCLK (64)
LRCK (64)
GTOP
XUGF

R1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1M UGFS
AVDD GTOP
GND

200p
GND

R10
R12

GND
GND

GND R14 R13

GND
VSS
VCC
GND
BCLK
DATA
LRCK

C2PO
MUTE
DEMP

WDCK

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA1372BQ/BS
 CXA1372BQ/BS

Notes on Operation

1. Connection of the power supply pin

Vcc VEE VC
dual ±5V power supplies +5V –5V 0V
single 5V power supplies +5V 0V VC

2. FSET pin
The FSET pin determines the cut-off frequency fc for the focus and tracking high-frequency phase compensation.

3. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
= 1/2 sled kick current

4. The tracking amplifier input is clamped at 1VBE to prevent overinput.

5. FE (focus error) and TE (tracking error) gain changing method

(1) High gain: Resistance between FE pins (Pins 5 and 6) 100kΩ → Large
Resistance between TA pins (Pins 11 and 12) 100kΩ → Large
(2) Low gain: A signal, whose resistance is divided, is input to FE and TE.

FE
TE

6. Input voltage of microcomputer interface Pins 20 to 25, should be set as follows.

VIH VCC × 90% or more
VIL VCC × 10% or less

7. Focus OK circuit
(1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
(2) The equivalent circuit of FOK output pin is as follows.
VCC

20k
FOK
33
50k
RL
100k
VCC

DGND DGND
FOK comparator output is:
Output voltage High: VFOKH ≈ near Vcc
Output voltage Low: VFOKL ≈ Vsat (NPN) + DGND
– 28 –
 CXA1372BQ/BS

8. Mirror Circuit
(1) The equivalent circuit of MIRR output pin is as follows.

Vcc

MIRR
29

20k RL

VEE DGND DGND

MIRR comparator output is:

Output voltage High: VMIRH ≈ VCC – Vsat (LPNP)
Output voltage Low: VMIRL ≈ near DGND

9. EFM Comparator
(1) Note that EFM duty varies when the CXA1372 Vcc differs from that of DSP IC (such as the CXD2500).
(2) The equivalent circuit of the EFM output pin is as follows.

4.8k 50

EFM
32

RL

700µA∗ 2mA∗
DGND

∗ When the power supply current between Vcc and DGND is 5V.

EFM comparator output is:

Output voltage High: VEFMH ≈ VCC – VBE (NPN)
Output voltage Low: VEFML ≈ VCC – 4.8 (kΩ) × 700 (µA) – VBE (NPN)

– 29 –
 Standard Circuit Design Data for Focus/Tracking Internal Phase Compensation

SW condition Bias condition Measure- Description of output

Mode Item Symbol SD ment waveform and measurement Min. Typ. Max. Unit
S1 S2 S3 S4 S5 S6 S7 S8 S9 E1 E2 E3 E4 point method
1.2kHz gain O 08 5 When CFLB = 0.1µF 21.5 dB
1.2kHz phase O 08 5 63 deg
1.2kHz gain O 0C 5 16 dB

FOCUS
1.2kHz phase O 0C 5 63 deg
1.2kHz gain O 25 11 13 dB
1.2kHz phase O 25 11 –125 deg
25
2.7kHz gain O 11 26.5 dB
13

TRACKING
25
2.7kHz phase O 11 –130 deg
13

– 30 –
CXA1372BQ/BS
 CXA1372BQ/BS

Example of Representative Characteristics

FOCUS frequency characteristics

40 180

35 135

CFLB = 0.1µ
30 90
CFGD = 0.1µ G

φ – Phase [degree]
25 45
G – Gain [dB]

20 0
φ
15 –45

10 –90
NORMAL
5 GAIN DOWN –135

0 –180
101 102 103 104 105

f – Frequency [Hz]

Tracking frequency characteristics

40 180

30 120
G
CTGU = 0.033µ

φ – Phase [degree]
20 60
G – Gain [dB]

10 0

φ
0 –60

NORMAL
–10 GAIN UP –120

–20 –180
101 102 103 104 105

f – Frequency [Hz]

– 31 –
 CXA1372BQ/BS

Package Outline Unit: mm

CXA1372BQ

48PIN QFP (PLASTIC)

15.3 ± 0.4

+ 0.4 + 0.1
12.0 – 0.1 0.15 – 0.05

36 25
0.15

37 24

13.5
48 13 + 0.2
0.1 – 0.1

1 12

0.9 ± 0.2
+ 0.15
0.8 0.3 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LEAD TREATMENT SOLDER / PALLADIUM

QFP-48P-L04 PLATING
EIAJ CODE ∗QFP048-P-1212-B LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.7g

CXA1372BS

48PIN SDIP (PLASTIC) 600mil

0.05
+ 0.1

+ 0.4
0.25 –

43.2 – 0.1

48 25
+ 0.3
13.0 – 0.1

0° to 15°
15.24

1 24
1.778
+ 0.4
4.6 – 0.1
0.5 MIN
3.0 MIN

0.5 ± 0.1
0.9 ± 0.15

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE SDIP-48P-02 LEAD TREATMENT SOLDER PLATING

EIAJ CODE SDIP048-P-0600-A LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 5.1g

– 32 –