Graphene nanoribbon FETs:
Technology exploration and CAD
Kartik Mohanram† Jing Guo‡
†
Department of Electrical and Computer Engineering, Rice University, Houston
‡
Department of Electrical and Computer Engineering, University of Florida, Gainesville
kmram@rice.edu guoj@ufl.edu
Abstract
Graphene nanoribbon FETs (GNRFETs) have emerged as a promis-
ing candidate for nanoelectronics applications. This paper summa-
rizes (i) current understanding and prospects for GNRFETs as ulti-
mately scaled, ideal ballistic transistors, (ii) physics-based model-
ing of GNRFETs to support circuit design and CAD, and (iii) vari-
ability and defects in GNRs and their impact on GNRFET circuit
performance and reliability.
1. Introduction
Graphene, which is a monolayer of carbon atoms packed into
a two-dimensional honeycomb lattice, has emerged as a promis-
ing candidate material for nanoelectronics applications. Graphene-
based devices offer high mobility for ballistic transport, high carrier
velocity for fast switching, monolayer thin body for optimum elec-
trostatic scaling, and excellent thermal conductivity [1–6]. The po-
tential to produce wafer-scale graphene films with full planar pro-
cessing for devices promises high integration potential with con-
ventional CMOS fabrication processes, which is a significant ad-
vantage over carbon nanotubes (CNTs) [6].
Although two-dimensional graphene is a zero band-gap semi-
metal, a band-gap is achieved by patterning graphene into a gra-
phene nanoribbon (GNR) that is a few nanometers wide [6–9]. The
band-gap of a GNR is in general inversely proportional to its width,
and width confinement down to the sub-10nm scale is essential to
open a band-gap that is sufficient for room temperature transis-
tor operation. Unlike CNTs, which are mixtures of metallic and
semiconducting materials, recent samples of chemically derived
sub-10nm GNRs have exhibited all-semiconducting behavior [9],
generating considerable excitement for transistor applications. The
two main types of GNRs, with the edges of the ribbons assumed
passivated by hydrogen atoms, are armchair-edge and zigzag-edge
GNRs (AGNRs and ZGNRs). ZGNRs are predicted to be metal-
lic by a simple tight-binding model, but a band-gap exists in more
advanced, spin-unrestricted simulations [10]. For digital circuits
applications, the focus has been on using AGNRs as the channel
material. AGNRs have an electronic structure that is closely related
to that of zigzag CNTs. The band-gap in AGNRs originates from
quantum confinement and edge effects play a critical role [10].
This paper first provides an overview of Schottky barrier (SB)
GNRFETs with intrinsic AGNR channels (GNRFETs henceforth,
unless specified otherwise). Unlike traditional MOSFETs, SBFETs
use metal or metal silicide contacts at the source and drain ends,
leading to the formation of SBs at these contacts. In SBFETs, the
gate modulates the quantum tunneling current through the SB [11].
Recently fabricated GNRFETs with channel lengths of the order of
200 nm delivered about 21% of the ballistic current at VD = 1V and
about 4.5% of the ballistic current at low VD < 0.1V [12]. Clearly,
these are preliminary devices, and it would be natural to expect
further advances such as the integration of ultrathin high-κ dielec-
trics [13] and aggressive channel length scaling to move the perfor-
mance of these devices closer to the ballistic limit, with switching
speeds, Ion /Ioff , and subthreshold slope that is competitive with
scaled CMOS.
Next, since GNRs and CNTs share similarities, modeling and
CAD for GNRFETs can expect to leverage the rich literature and
experience in physics-based efforts related to CNTFETs. How-
ever, several effects, e.g., edge bond relaxation and the third nearest
neighbor interaction that are not pronounced in CNTs have been
shown to play important role in the electronic structure of GNRs
and device characteristics of GNRFETs. Recent progress in physics-
based analytical modeling based on the Landauer approach for GN-
RFETs notwithstanding, several challenges on the modeling and
CAD fronts remain to be addressed.
Last, due to the atomically thin and nanometer-wide geometries
of GNRs, variability and defects are projected to have a larger im-
pact on GNRFET circuit performance and reliability in comparison
to conventional silicon devices. Variability, for example, can arise
from the difficulty of control of the GNR width, edge roughness,
or oxide thickness during fabrication. Defects may occur during
fabrication due to a charge impurity in the gate insulator or a lat-
tice vacancy, and result in a large performance variation or a non-
functional device. Not only must each of the variability and defect
mechanisms be identified and studied, the models developed for
GNRs and GNRFETs must be capable of predicting their effects in
isolation as well as together in a systematic manner.
This paper is organized as follows. Section 2 provides a short
introduction to short-channel, SB-type GNRFETs with intrinsic A-
GNR channels. Section 3 summarizes modeling and CAD chal-
lenges for GNRs and GNRFETs. Section 4 summarizes challenges
posed by variability and defects. Section 5 is a conclusion.
2. GNRFETs
In order to study how close the GNRFET operates to the ballis-
tic performance limit, it is necessary to use theoretical models and
quantum simulators capable of capturing several important features
of GNR device physics. Although most discussions in this paper
focus on SB-type GNRFETs [14], simulation studies of MOSFET-
type GNRFETs with doped reservoirs have also been reported in
literature [15–17]. In [18, 19], SB-type GNRFETs were also com-
pared to MOSFET-type GNRFETs. There is consensus that in ideal
devices, MOSFET-type GNRFETs show better device characteris-
tics over SB-type GNRFETs: larger maximum achievable Ion /Ioff ,
larger Ion , larger transconductance, and better saturation behavior.
Motivated by experimental work [20, 21], ballistic MOSFET-type
GNRFETs with wide monolayer and bilayer graphene channels The GNRFET channel is assumed to be comprised of 4 equi-distant
were studied in [22, 23], and it was concluded that bilayer devices GNRs, with a contact width of 10nm per GNR for a total contact
exhibit different but more favorable I-V characteristics in compar- width of 40nm in this paper. The current in the GNRFET is 4 times
ison to the monolayer devices. the current in the individual GNR channel, and the parasitics are
The GNRFETs considered in this paper have 15 nm-long intrin- also 4 times that for an individual GNR. The parasitic junction ca-
sic AGNR channel material. AGNRs are classified based on their pacitances CGD,e and CGS,e are determined by 3D electrostatics
index, n, into three families with n = 3p/3p + 1/3p + 2 [24] — to be 0.01– 0.1 aF/nm times the total GNRFET contact width. The
AGNR widths over the n = 9–18 range from the 3p family are con- substrate is usually thick enough that the extrinsic parasitic capac-
sidered here. Double gate geometry is implemented through a 1.5 itances CDB,e and CSB,e are negligible. The contact resistances
nm-thick SiO2 gate insulator (r = 3.9). The source and drain con- range from 1 KΩ to 100 KΩ, with reported values of approximately
tacts are metals, and the Schottky barrier height is equal to half 60KΩ [12].
the band-gap of the channel GNR (ΦBn = ΦBp = Eg /2). Simula- −5
10
−6
7 x 10
tions of such GNRFETs are carried out by self-consistent solution 6 VD = 0.05V
of the Schrödinger and Poisson equations in the atomistic pz orbital −6
10
VD = 0.75V 5
basis within the non-equilibrium Green’s function (NEGF) formal- Offset = 0.2V

ID (A)
ID (A)
4
ism [25]. Because the electric field varies in all dimensions for −7
10
VD = 0.5V VT = 0.1V
3
the simulated device structure, the 3D Poisson’s equation is used
−8 2
and numerically solved using the finite element method. A pz or- 10
VD = 0.25V Offset = 0V
1
bital coupling parameter of 2.7 eV is used and energy relaxation at VT = 0.3V
−9
the edges is treated according to ab initio calculations [10]. The 10
0 0.2 0.4 0.6 0.8
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

theoretical model computes the ballistic performance limits by as-
suming a single ballistic channel and ideal contacts (sufficiently
negative SBs) [26].
The I-V device characteristics for the ideal n = 12 GNRFET for
different drain voltages is shown in Figure 1(a). Ambipolar char-
acteristics due to both electron and hole conduction (SBFET-type
operation) are clearly shown, with electron conduction at high gate
voltages and hole conduction at low gate voltages. Minimum leak-
age current occurs at VG ≈ VD /2. If Ion is divided by the chan-
nel width, it is 6300 μA /μm for the n = 12 GNRFET when VD is
0.5 V. As drain voltage increases, SBFETs show linear behavior
in the overall range of gate bias. For example, the drain current
and the channel charge for VD = 0.75V are linearly proportional to
VG , whereas those for VD = 0.25V show exponential behavior in the
sub-threshold region.
The threshold voltage VT of the GNRFET is obtained using tra-
ditional VT extraction methods for MOS devices from the I-V
data [27]. When a low drain voltage VDS is applied to an n-type
GNRFET, the slope of the I-V curve at a high gate voltage is said to
intersect the VG axis at the threshold voltage VT . This is illustrated
for the I-V curve in Figure 1(b), where the VT is approximately 0.3
V. The leakage current at VG = 0 is large, but the threshold voltage
of the FET can be tuned by engineering the gate metal material to
shift the I-V curves along the x-axis, thereby moving the point with
minimum leakage current to VG = 0 [28]. Note that when the off-set
is applied to achieve minimum leakage, VT changes by an amount
equal to the off-set, illustrated by the I-V curve for an off-set of
0.2V and a VT of approximately 0.1V in the same figure. Finally,
both n-type and p-type FETs can be achieved on the same GNRFET
due to the ambipolar I-V characteristics. This has already been ex-
perimentally demonstrated in the context of CNTFETs [28], which
exhibit ambipolar I-V characteristics qualitatively similar to GN-
RFETs.
The drain current ID (VG , VD ) and channel charge Q(VG , VD )
computed for the intrinsic GNRFET can be used with data-driven
table lookup simulators to simulate extrinsic GNRFETs. Extrinsic
n-type and p-type GNRFETs can be modeled by adding the para-
sitic capacitances and contact resistances around the intrinsic GNR.
Two strategies — fabricating very narrow contacts to an individual
GNR or fabricating multiple GNRs in an array for a wide contact
— are currently under investigation in the device community. The
pitch refers to the spacing between the neighboring GNRs in the
GNRFET channel, and usually ranges from the GNR width to 1μm.
VG (V) VG (V)
(a) (b)
Figure 1: (a) I-V characteristics and (b) VT extraction at low
VD for ideal n = 12 GNRFETs
Preliminary results for circuit-level technology exploration based
on such GNRFETs, considering both performance robustness and
reliability was presented in [29]. By explicitly considering the
trade-offs between delay, energy, and noise robustness for differ-
ent values of VDD and VT , it was shown that traditional objectives
based on metrics like the energy-delay product (EDP) may lead
to unreliable designs with poor performance even for nominal de-
vices. At an operating point with VDD and VT tuned to comparable
performance and reliability to the 22 nm CMOS predictive technol-
ogy node, ideal ballistic GNRFETs enjoy a 40X EDP advantage.
This advantage in EDPs leaves enough headroom for robust design
with GNRFETs to overcome challenges due to variability and de-
fects described in Section 4.
3. GNRFET modeling and CAD
Although there is broad consensus that GNRFET modeling can
leverage the rich literature developed in the context of MOSFETs,
models for GNRFETs must be capable of treating new device phy-
sics specific to GNRs, such as edge scattering, edge bond relax-
ation, and the third nearest neighbor (3nn) interaction. Models must
also treat (i) the Dirac-Fermion-like E-k relation of graphene, (ii)
the quantum capacitance limit due to the low quasi-one-dimensional
density-of-states of GNRs, and (iii) transport from ballistic to the
quasi-ballistic regime for different edge qualities, channel lengths,
and bias regimes.
One of the main candidate approaches is the physics-based, semi-
analytical nanotransistor model based on the Landauer approach
that has previously been applied to model silicon nanoscale MOS-
FETs, nanowire FETs, and CNTFETs [26, 30–37]. Circuit mod-
els based on the Landauer approach provide a compact physical
description of transistor physics at the mesoscopic and molecular
scale. The model distills the essential physics of ballistic FETs
to the carrier statistics at the beginning of the channel and self-
consistent electrostatics described by a capacitance network. The
core of this approach requires the solution of the charge density in-
tegral for the channel and subsequent solution of the self-consistent
electrostatics equation for the local potential at the top of the energy
barrier.

As applied to CNTFETs in its simplest form, this approach as-
sumes ballistic carrier transport, i.e, the scattering effects of charge
carriers are ignored and it does not model real-device effects like
edge bond relaxation and third nearest neighbor interaction that
play an important role in the calculation of the band structure nec-
essary to simulate GNRFETs. For CNTs, a simple pz orbital tight
binding (TB) calculation with the first nearest neighbor interaction
yields an accurate E-k relation in the energy range relevant for car-
rier transport. For an AGNR, this calculation, however, fails to
yield even a correct band-gap, as indicated by comparing the TB
results to the ab initio simulation results [10, 38, 39]. In an AGNR,
the difference is due to both the edge bond relaxation and the third
nearest neighbor interaction (shown in figure 2), which a simple TB
calculation does not include.
Figure 2: The schematic sketch of an AGNR. The edge of the
honeycomb lattice is hydrogen terminated. The edge bonds
(colored lines) have a different bonding length and bonding pa-
rameter from those in the middle of the AGNR due to edge
bond relaxation. The interaction between the first nearest
neighbor (1nn), the second nearest neighbor (2nn), and the
third nearest neighbor (3nn) atoms are also shown.
Through a re-parameterization of the TB model using additional
parameters that describe these effects, it is possible to obtain a
band-structure in agreement with the ab initio calculations in the
energy range of interest [39]. When integrated with the basic Lan-
dauer approach, it is possible to derive an analytical model to de-
scribe ballistic GNRFETs that handles these effects [40]. Results
based on this simple model indicate the important role of the edge
bond relaxation and third nearest neighbor interaction effects on the
electrostatics of AGNRs. Edge bond relaxation results in a slight
decrease of the threshold voltage VT . The third nearest neighbor
interaction results in a further and larger decrease of VT , because
of the decrease in AGNR band-gap. At the same time, the gate ca-
pacitance slightly increases after edge effects are considered, due
to an increase of the density-of-states and hence the GNR quantum
capacitance.
Such physics-based compact models based on the Landauer ap-
proach serve as a good starting point for GNRFET models that in-
volve more complex interactions and/or many-body effects. The
models can also be validated and extended by more rigorous quan-
tum atomistic simulations and availability of more experimental
data. Extending these models to systematically understand and
predict the effects of variability and defects will help with CAD-
related efforts to optimize the performance and reliability of GN-
RFET circuits. However, the Landauer approach still involves nu-
merical computation of the charge density integral and solution to
the self-consistent electrostatics, which makes the study of GNR-
FET circuits computationally demanding and not scalable to large
circuits. Recent progress in CNTFET modeling that focus on com-
putational aspects of the Landauer approach provide good mathe-
matical continuity for simulators to obtain robust simulation results
with fast convergence, e.g., [34, 35, 37, 41] and are good starting
points for future research to address these issues.
−4
10
VD = 0.5V
−5
10
−6 N = 18
10
ID (A)
N = 15
−7
10
N = 12
−8
10
N=9
−9
10
0 0.2 0.4 0.6 0.8
VG (V)
Figure 3: I-V characteristics for different GNR widths
4. GNRFETs: Variability and defects
Variability and defects are expected to play an important role
in graphene electronics in practice. Variability, for example, can
come from the difficulty of control of the GNR width, edge rough-
ness, or oxide thickness during fabrication. Defects may occur dur-
ing fabrication due to a charge impurity in the gate insulator or
a lattice vacancy, and result in a large performance variation or a
non-functional device.
Figure 3 illustrates how variability in GNR width affects device
ID -VG characteristics. The band-gap of the n = 18 GNR is too small
to achieve a small leakage current, whereas that of the n = 9 GNR is
sufficiently large so that Ion /Ioff is as high as 1000 X. However, the
capacitance of a wider GNRFET is large due to the larger surface
of the GNR channel. The n = 18 GNRFET has 50% larger intrinsic
channel capacitance than the n = 9 GNRFET in the on state, which
can impact performance.
State-of-the-art etching techniques are far enough from atomistic
resolution that edge roughness is projected to play an important role
in GNRFETs [8]. Edge scattering, optical phonon scattering, and
defect scattering have all been identified to play an important role
in GNRFETs [12]. The effect of edge roughness on MOSFET-type
GNRFETs was reported in [42]. Across these studies, there is con-
sensus that edge roughness effects reduce Ion and increase Ioff ,
with the effect of edge roughness increasing as GNR width is de-
creased. Edge roughness effects of the same degree but with atomi-
cally different edge configurations are also expected to contribute to
increased variability across devices [42], especially at short channel
lengths [43]. It is, therefore, important to improve the edge quality
to optimize the performance of GNRFETs.
For SBFETs, a charge impurity in the gate oxide behaves as
a fixed external charge that plays an important role on the self-
consistent electrostatic potential. The location of the charge im-
purity in the gate oxide is important, since device characteristics
are affected most severely when it is located close to the source
because the SB between source and GNR is affected. Figure 4(a)
shows the severely affected Schottky barrier due to the charge im-
purity that is placed near the source and at a distance of 0.4 nm from
the GNR surface (see inset for position of charge impurity in the
cross-section of the simulated device). Both polarities of charges
are considered, and the charge magnitude is also varied.
A negative charge impurity increases the SB height and thick-
ness, whereas a positive charge impurity decreases the SB height
and thickness at the source contact. This affects the source-drain
current and the charge in the channel. With the charge impurity of
-2q, the electron flow is significantly reduced by the large barrier,
and the on current is a factor of six smaller than that in the ideal
device. For the device with the +2q charge impurity, both off and
on currents show a relatively smaller variation from the ideal de-
vice compared to that with the -2q charge impurity in the n-type
operation branch (VG > 0.25 V), as illustrated in Figure 4(b).
 0.8
VD = 0.5V Top Gate
0.6
impurity SiO2
-2q S D
0.4 SiO2
-q
ID (A)
Bottom Gate
EC (eV)
0.2
EFS
No impurity
0 10
S dimensional quantum simulation study,” IEEE Trans. Electron Devices, vol. 54,
−0.2
EFD
−0.4 +q
+2q
−0.6 D [16] G. Liang et al., “Ballistic graphene nanoribbon metal-oxide-semiconductor field-
−2 0 2 4 6 8 10 12 14 16
x (nm)
(a)
Figure 4: (a) Conduction band profile of n = 12 GNRs with and
without charge impurity. The inset shows the position of the
charge impurity in the cross-section of the simulated device.
(b) I-V characteristics for n = 12 GNRs with charge impurities
A recent study that compared SB-type GNRFETs to MOSFET-
type GNRFETs concludes that MOSFET-type GNRFETs are rela-
tively more robust, but equally vulnerable to these variability and
defect modes [19].
In practice, multiple defects and variability of all GNRs in the
array may exist and it may be that each GNR in the channel ex-
periences the same variation, defect, or combination thereof. For
example, if the pitch is comparable to the gate oxide thickness, it
is reasonable to expect an impurity to affect more than one GNR in
the GNRFET channel because the charge impurity’s electric field
is not completely screened by the gate. Although the results pre-
sented in [29] establish lower and upper bounds for the effects of
width variations and charge impurity defects on GNRFET circuits,
future studies are necessary to understand these and other variabil-
ity and defect effects as a function of device geometry and layout.
5. Conclusions
Graphene electronics has evolved to where experimental and the-
oretical advances indicate its promise as a candidate material for
nanoelectronics applications. This paper summarized state-of-the-
art in graphene research for digital circuits applications and out-
lined challenges that must be addressed on the technology, model-
ing, and CAD fronts.
Acknowledgements
The authors acknowledge the support of Hongjie Dai and his
group in the Department of Chemistry, Stanford University.
References
[1] K. S. Novoselov et al., “Electric field effect in atomically thin carbon films,”
Science, vol. 306, pp. 666–669, 2004.
[2] Y. Zhang et al., “Experimental observation of the quantum Hall effect and
Berry’s phase in graphene,” Nature, vol. 438, pp. 201–204, 2005.
[3] C. Berger et al., “Electronic confinement and coherence in patterned epitaxial
graphene,” Science, vol. 312, pp. 1191–1196, 2006.
[4] R. V. Noorden, “Moving towards a graphene world,” Nature, vol. 442, pp. 228–
229, 2006.
[5] A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Materials,
vol. 6, pp. 183–191, 2007.
[6] W. A. de Heer et al., “Pionics: The emerging science and technology of
graphene-based nanoelectronics,” in Intl. Electron Devices Meeting Technical
Digest, pp. 199–202, 2007.
[7] Z. Chen et al., “Graphene nano-ribbon electronics,” Physica E: Low-dimensional
Systems and Nanostructures, vol. 40, no. 2, pp. 228–232, 2007.
[8] M. Y. Han et al., “Energy band-gap engineering of graphene nanoribbons,” Phys-
ical Review Letters, vol. 98, p. 206805, 2007.
[9] X. Li et al., “Chemically derived, ultrasmooth graphene nanoribbon semicon-
ductors,” Science, vol. 319, pp. 1229–1232, 2008.
[10] Y.-W. Son, M. L. Cohen, and S. G. Louie, “Energy gaps in graphene nanorib-
bons,” Physical Review Letters, vol. 97, p. 216803, 2006.
[11] S. Heinze et al., “Carbon nanotubes as Schottky barrier transistors,” Physical
Review Letters, vol. 89, p. 106801, Aug. 2002.
10
−5 [12] X. Wang et al., “Room temperature all-semiconducting sub-10nm graphene
VD = 0.5V nanoribbon field-effect transistors,” Physical Review Letters, vol. 100, p. 206803,
2008.
10
−6
[13] B. Özyilmaz et al., “Electronic transport in locally gated graphene nanoconstric-
+2q
tions,” Applied Physics Letters, vol. 91, p. 192107, 2007.
−7
No impurity [14] Y. Ouyang et al., “Scaling behaviors of graphene nanoribbon FETs: A three-
-2q pp. 2223–2231, Sep. 2007.
10
−8 [15] G. Fiori and G. Iannaccone, “Simulation of graphene nanoribbon field-effect
0 0.2 0.4 0.6 0.8
transistors,” IEEE Electron Device Letters, vol. 28, pp. 760–762, Aug. 2007.
VG (V)
effect transistors: A full real-space quantum transport simulation,” Journal of
(b) Applied Physics, vol. 102, p. 054307, 2007.
[17] G. Liang et al., “Performance projections for ballistic graphene nanoribbon field-
effect transistors,” IEEE Trans. Electron Devices, vol. 54, pp. 677–682, Apr.
2007.
[18] G. Fiori et al., “Performance comparison of graphene nanoribbon Schottky
barrier and MOS FETs,” in Intl. Electron Devices Meeting Technical Digest,
pp. 757–760, 2007.
[19] Y. Yoon et al., “Performance comparison of graphene nanoribbon FETs with
Schottky contacts and doped reservoirs,” IEEE Trans. Electron Devices. To ap-
pear.
[20] B. Huard et al., “Transport measurements across a tunable potential barrier in
graphene,” Physical Review Letters, vol. 98, p. 236803, 2007.
[21] J. B. Oostinga et al., “Gate-induced insulating state in bilayer graphene devices,”
Nature Materials, vol. 7, pp. 151–157, Feb. 2008.
[22] M. I. Katsnelson, K. S. Novoselov, and A. K. Geim, “Chiral tunnelling and the
Klein paradox in graphene,” Nature Physics, vol. 2, pp. 620–625, 2006.
[23] Y. Ouyang, P. Campbell, and J. Guo, “Analysis of ballistic monolayer and bilayer
graphene field-effect transistors,” Applied Physics Letters, vol. 92, p. 063120,
2008.
[24] K. Nakada et al., “Edge state in graphene ribbons: Nanometer size effect and
edge shape dependence,” vol. 54, pp. 17954–17961, Dec. 1996.
[25] S. Datta, Quantum transport: Atom to transistor. Cambridge, UK: Cambridge
University Press, 2005.
[26] M. Lundstrom and J. Guo, Nanoscale Transistors: Device Physics, Modeling
and Simulation. New York, NY: Springer, 2006.
[27] G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE,
ch. 6, pp. 267–298. McGraw-Hill, Inc., 1993.
[28] Z. Chen et al., “An integrated logic circuit assembled on a single carbon nan-
otube,” Science, vol. 311, p. 1735, 2006.
[29] M. R. Choudhury et al., “Technology exploration for graphene nanoribbon
FETs,” in Proc. Design Automation Conference, pp. 272–277, 2008.
[30] K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor,” Journal
of Applied Physics, vol. 76, no. 8, pp. 4879–4890, 1994.
[31] A. Rahman et al., “Theory of ballistic nanotransistors,” IEEE Trans. Electron
Devices, vol. 50, pp. 1853–1864, Sep. 2003.
[32] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A circuit-compatible model
of ballistic carbon nanotube field-effect transistors,” IEEE Trans. Computer-
aided Design, vol. 23, pp. 1411–1420, Oct. 2004.
[33] H.-S. P. Wong et al., “Carbon nanotube transistor circuits: Models and tools
for design and performance optimization,” in Proc. Intl. Conference Computer-
aided Design, pp. 651–654, 2006.
[34] D. Jiménez et al., “A simple drain current model for Schottky-barrier carbon
nanotube field effect transistors,” Nanotechnology, vol. 18, p. 025201, 2007.
[35] B. C. Paul et al., “An analytical compact circuit model for nanowire FET,” IEEE
Trans. Electron Devices, vol. 54, pp. 1637–1644, Jul.
[36] J. Deng and H.-S. P. Wong, “A compact SPICE model for carbon-nanotube field-
effect transistors including nonidealities and its application–Part 1: Model of the
intrinsic channel region,” IEEE Trans. Electron Devices, vol. 54, pp. 3186–3194,
2007.
[37] H. Hashempour and F. Lombardi, “Device model for ballistic CNFETs using the
first conducting band,” IEEE Design and Test of Computers, vol. 25, pp. 178–
186, 2008.
[38] C. T. White et al., “Hidden one-electron interactions in carbon nanotubes re-
vealed in graphene nanostrips,” Nano Letters, vol. 7, pp. 825–830, 2007.
[39] D. Gunlycke and C. T. White, “Tight-binding energy dispersions of armchair-
edge graphene nanostrips,” Physical Review B, vol. 77, p. 115116, 2008.
[40] P. Zhao et al., “Analytical theory of graphene nanoribbon transistors,” in Proc.
Intl. Workshop on Design and Test of Nano Devices, Circuits and Systems, 2008.
To appear.
[41] A. Balijepalli, S. Sinha, and Y. Cao, “Compact modeling of carbon nanotube
transistor for early stage process-design exploration,” in Proc. Intl. Symposium
on Low Power Electronics and Design, pp. 2–7, 2007.
[42] D. Basu et al., “Effect of edge roughness on electronic transport in graphene
nanoribbon channel metal-oxide-semiconductor field-effect transistors,” Applied
Physics Letters, vol. 92, no. 4, p. 042114, 2008.
[43] Y. Yoon and J. Guo, “Effect of edge roughness in graphene nanoribbon transis-
tors,” Applied Physics Letters, vol. 91, p. 073103, 2007.