DPSK

In DPSK the phase of the modulated signal is shifted relative

to the previous signal element. The signal phase follows the
high or low state of the previous element.

bk dk=bk-dk-1 Product Output

Modulator DPSK

dk-1 XOR

C(t)
1 bit Delay

bk dk-1 XOR o/p

0 0 0
0 1 1
1 0 1
1 1 0
If next data bit is 1 there will be change in polarity in output
of XOR.
If next data bit is 0 there will be no change in polarity in
output of XOR.
The following figure represents the model waveform of DPSK.
The advantage with DPSK system is that it does not require a
synchronous carrier in the demodulator. So no local oscillator is
required at receiver side.
DPSK Demodulator

From the above figure, it is evident that the balance

modulator is given the DPSK signal along with 1-bit delay
input. Then the output is applied to a LPF. Then it is passed to
a shaper circuit, which is a comparator circuit, to recover the
original binary data as the output.
Case I : Let, both received DPSK and delayed signals have
same polarity and they are bk Ac sin ωct and bk Ac sin ωct. Then
the output of the balanced modulator =
bk Ac sin ωct × bk Ac sin ωct or (-bk Ac sin ωct)×(-bk Ac sin ωct)
= 𝒃𝟐𝒌 𝑨𝟐𝒄 sin2ωct
𝟏−𝐜𝐨𝐬𝟐𝛚𝒄 𝐭
= 𝒃𝟐𝒌 𝑨𝟐𝒄 [ ]
𝟐
𝒃𝟐𝒌 𝑨𝟐𝒄 𝒃𝒌 𝑨𝟐𝒄
= - cos2ωct
𝟐 𝟐
𝒃𝟐𝒌 𝑨𝟐𝒄
The output of LPF is and final output of the comparator
𝟐
is 1.
Case II : Let, both received and delayed signals are not of
same polarity and they are bk Ac sin ωct and -bk Ac sin ωct.
Then the output of the balanced modulator =
-bk Ac sin ωct × bk Ac sin ωct
= −𝒃𝟐𝒌 𝑨𝟐𝒄 sin2ωc1t
 𝟏−𝐜𝐨𝐬𝟐𝛚𝒄 𝐭
= −𝒃𝟐𝒌 𝑨𝟐𝒄 [ ]
𝟐
𝒃𝟐𝒌 𝑨𝟐𝒄 𝒃𝒌 𝑨𝟐𝒄
=− + cos2ωct
𝟐 𝟐
𝒃𝟐𝒌 𝑨𝟐𝒄
The output of LPF is - and final output of the comparator
𝟐
is 0.

QPSK
QPSK sends two bits of digital information at a time. Instead
of the conversion of digital bits into a series of digital stream,
it converts them into bit pairs.
QPSK Modulator
The QPSK Modulator uses a bit-splitter, two multipliers with
local oscillator, a 2-bit serial to parallel converter, and a
summer circuit. Following is the block diagram for the same.

At the modulator’s input, the message signal’s even bits (i.e.,

2nd bit, 4th bit, 6th bit, etc.) and odd bits (i.e., 1st bit, 3rd bit,
5th bit, etc.) are separated by the bits splitter and they are
multiplied with the same carrier to generate odd PSK (called
as PSKI) and even PSK (called as PSKQ). But the PSKQ carrier
signal is phase shifted before being modulated.
The QPSK waveform for two-bits input is as follows, which
shows the modulated result for different instances of binary
inputs.

QPSK can carry information at a rate which is double of that

of DPSK. It is applied in cable modem, satellite communication
etc. It selects one of the four possible carrier phase shifts:
For bit pairs 00, 01,10,11 phase shifts of 0°, 90°,180°, 270° etc
can be obtained.
QPSK Demodulator
The QPSK Demodulator uses two PSK demodulator circuits
with local oscillator, two low pass filters, two square wave
generators to obtain the digital data and a 2-bit parallel to
serial converter. Following is the diagram for the same.

The two PSK detectors at the input of demodulator

simultaneously perform the demodulation and the pair of
bits are recovered here from the original data. These signals
after processing, are passed to the parallel to serial converter
and from the output the digital signal can be retrieved.

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