FET Biasing

Types of Biasing

• Gate Bias
• Self Bias
• Voltage Divider Bias
• Source Bias

Biasing Provides fixed level of current flowing through the

device and provide fixed voltage drop across the device.
• Irrespective of the method of biasing it is
always necessary to reverse biased the
gate-source junction of JFET for its
proper operation.

• For proper operation of JFET, the gate-

source junction is always reversed bias.
• If the gate source junction becomes
forward bias then it allow the current to
flow through the gate terminal and that
may damage the JFET
 Self Biasing of JFET

Self-Bias JFETS (IS=ID in all FETs)

 Example

Find VGS and VDS in the figure below

 D-MOSFET BIASING
• Recall that depletion/enhancement
MOSFETs can be operated with either
positive or negative values of 𝑽𝑮𝑺

• A simple bias method, called zero bias, is

to set VGS = 0 V so that an ac signal at the
gate varies the gate-to-source voltage
above and below this bias point.

• Since VGS = 0 V, ID = IDSS as indicated. IDSS is

defined as the drain current when VGS = 0
V. The drain-to-source voltage is expressed
as Zero-biased D-MOSFET
𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝑰𝑫𝑺𝑺 𝑹𝑫
 Example

Determine the drain-to-source voltage in

the circuit shown. The MOSFET data sheet
gives VGS(off)=-8 V and IDSS =12 mA.
E-MOSFET BIASING

• Recall that enhancement-only MOSFETs must have

a VGS greater than the threshold value, VGS(th)

• Two ways to bias an E-MOSFET

• In either bias arrangement, the purpose is to make

the gate voltage more positive than the source by
an amount exceeding VGS(th).

• In the drain-feedback bias circuit in Fig (a) shown,

there is negligible gate current and, therefore, no
voltage drop across RG. As a result, VGS = VDS.

• Equations for the voltage-divider bias in Fig (b) are

as follows: E-MOSFET biasing arrangements.
𝑹𝟐
𝑽𝑮𝑺 = 𝑽
𝑹𝟏 + 𝑹𝟐 𝑫𝑫
𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹𝑫
 Example

Determine the amount of drain current in the

circuit shown. The MOSFET has a VGS(th) of 3 V.
FET AMPLIFIERS
 Transconductance

In a FET, the gate voltage controls the drain current. An

important FET parameter is the transconductance, gm,
which is defined as

𝑰𝒅
𝒈𝒎 =
𝑽𝒈𝒔

The transconductance is one factor that determines the voltage

gain of a FET amplifier.
 Common-Source (CS) Amplifiers (Bypassed RS)
A self-biased n-channel common source (CS) JFET amplifier with an ac source capacitively
coupled to the gate is shown below.
• The resistor RG serves two purposes:
a. It keeps the gate at approximately 0 V dc
(because IGSS is extremely small).
b. its large value (usually several mega ohms)
prevents loading of the ac signal source.

• IGSS is the gate reverse current in a FET, which is

measured when it is reverse-biased.
• The bias voltage is created by the drop across
RS. The bypass capacitor, C3, keeps the source
of the FET effectively at ac ground.
• The drain current swings above and below its
Q-point value in phase with the gate-to-source
JFET common-source amplifier voltage. The drain-to-source voltage swings
above and below its Q-point value 180° out of
phase with the gate-to-source voltage
Common Source JFET Amplifier
Characteristics Curves
 D-MOSFET
A zero-biased n-channel D-MOSFET with an ac source capacitively coupled to the
gate is shown in the figure below.

• The gate is at approximately 0 V dc and the

source terminal is at ground, thus making VGS
= 0 V.

• The signal voltage causes Vgs to swing above

and below its 0 value, producing a swing in
Id.

• The negative swing in Vgs produces the

depletion mode, and Id decreases. The
Zero-biased D-MOSFET
common-source amplifier. positive swing in Vgs produces the
enhancement mode, and Id increases.
When signal (Vin) is applied, Vgs swings above and below its zero value , producing a
swing in drain current Id
 E-MOSFET
The figure below shows a voltage-divider-biased, n-channel E-MOSFET with an ac signal
source capacitively coupled to the gate.

• The gate is biased with a positive voltage such that

VGS > VGS(th), where VGS(th) is the threshold value.

• As with the JFET and D-MOSFET, the signal voltage

produces a swing in Vgs above and below its Q-
point value. This swing, in turn, causes a swing in Id.
Operation is entirely in the enhancement mode.

Common-source E-MOSFET amplifier

with voltage-divider bias.
 Voltage Gain
𝑽𝒐𝒖𝒕
• Voltage gain,𝑨𝒗, of an amplifier always equals .
𝑽𝒊𝒏
• In the case of the CS amplifier, Vin is equal to Vgs, and Vout is equal to the signal
voltage developed across RD, which is IdRD. Thus,

𝑰 𝒅 𝑹𝑫
𝑨𝒗 =
𝑽𝒈𝒔

𝑰𝒅
• Since 𝒈𝒎 = , the common-source voltage gain is
𝑽𝒈𝒔

𝑨𝒗 = 𝒈𝒎 𝑹𝑫
 Input Resistance

• Because the input to a CS amplifier is at the gate, the input resistance is extremely
high. Ideally, it approaches infinity and can be neglected. The high input
resistance is produced by the reverse-biased pn junction in a JFET and by the
insulated gate structure in a MOSFET.

• The actual input resistance seen by the signal source is the gate-to-ground resistor 𝑹𝑮 in
parallel with the FET’s input resistance, 𝑽𝑮𝑺/𝑰𝑮𝑺𝑺. The reverse leakage current 𝑰𝑮𝑺𝑺 is
typically given on the data sheet for a specific value of 𝑽𝑮𝑺 so that the input resistance of
the device can be calculated.
 Example
a) What is the total output voltage (dc + ac) of the amplifier in the figure below? The 𝒈𝒎 is
𝟏𝟖𝟎𝟎 µ𝑺, 𝑰𝑫 is 𝟐 𝒎𝑨, 𝑽𝑮𝑺(𝒐𝒇𝒇) is −𝟑. 𝟓 𝑽, and 𝑰𝑮𝑺𝑺 is 𝟏𝟓 𝒏𝑨.

b) What is the input resistance seen by the signal source?

 Common-Drain (CD) Amplifier
• A common-drain (CD) JFET amplifier is shown in the figure below with voltages indicated.
• Self-biasing is used in this circuit.
• The input signal is applied to the gate through a coupling
• capacitor, and the output is at the source terminal.
• There is no drain resistor.
• This circuit is sometimes called a source-follower

JFET common-drain
amplifier
(source-follower).
 Voltage Gain
• As in all amplifiers, the voltage gain is 𝑨𝒗 = 𝑽𝒐𝒖𝒕/𝑽𝒊𝒏. For the source-follower, 𝑽𝒐𝒖𝒕
is 𝑰𝒅𝑹𝑺 and 𝑽𝒊𝒏 is 𝑽𝒈𝒔 = 𝑰𝒅𝑹𝑺, as shown in the figure below. Therefore, the gate-to-
source voltage gain is 𝑰𝒅𝑹𝑺/(𝑽𝒈𝒔 + 𝑰𝒅𝑹𝑺). Substituting 𝑰𝒅 = 𝒈𝒎𝑽𝒈𝒔 into the
expression gives the following result:

𝒈𝒎 𝑽𝒈𝒔 𝑹𝑺
𝑨𝒗 =
𝑽𝒈𝒔 + 𝒈𝒎 𝑽𝒈𝒔 𝑹𝑺

Cancelling 𝑽𝒈𝒔 yields

𝒈𝒎 𝑹𝑺
𝑨𝒗 =
𝟏 + 𝒈𝒎 𝑹𝑺
• Notice that the gain is always less then 1. If 𝒈𝒎 𝑹𝑺 ≫ 𝟏, then a good
approximation is 𝑨𝒗 ≅ 𝟏.
• Since the output voltage is at the source, It is in phase with the source (input)
voltage.
 Input Resistance

Because the input signal is applied to the gate, the input resistance seen by the
input signal source is extremely high. The gate resistor RG, in parallel with the input
resistance looking in at the gate, is the total input resistance.

𝑹𝑰𝑵 = 𝑹𝑮 ∥ 𝑹𝑰𝑵(𝒈𝒂𝒕𝒆)

Where, 𝑽𝑮𝑺
𝑹𝑰𝑵(𝒈𝒂𝒕𝒆) =
𝑰𝑮𝑺𝑺
Example

(a)Determine the voltage gain of the

amplifier in Figure (a) using the data
sheet information in Figure (b).
(b)Determine the input resistance at 25°C.
Assume minimum data sheet values
where available.
Homework

1. Repeat part (b) in Example 2 for 𝑻𝑨 = 𝟔𝟓℃

2. What factors determine the voltage gain of a CS FET amplifier?
3. A certain CS amplifier has an RD = 1.0 kΩ. When a load resistance
of 1.0 kΩ is capacitively coupled to the drain, how much does the
gain change?