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TOOLS:
1) Find the following for the memory modules
dti_sp_tm28_1024x8_4ww1x_m_a.v
dti_dpp_tm28hpclvt_256x8_t4ww1xoec_m_b.v
dti_sp_tm28_32x53_4ww1x_m_a.v

Soln:
1.dti_sp_tm28_1024x8_4ww1x_m_a.v
1) Number of address lines
10.
2) Number of data lines

3) Is the memory repairable or not

Notrepairable
4) Is it dual port or single port
Single port.

2.dti_dpp_tm28hpclvt_256x8_t4ww1xoec_m_b.v
1) Number of address lines
8.
2) Number of data lines
8
3) Is the memory repairable or not
Repairable.
4) Is it dual port or single port
Dual port.

3.dti_sp_tm28_32x53_4ww1x_m_a.v
1) Number of address lines
5.
2) Number of data lines
53.
3) Is the memory repairable or not
Not repairable.
4) Is it dual port or single port
Single port.
2. Write down the functionality of the following commands and list out few
of its switches
- set_context
- set_tsdb_output_directory
- read_verilog
-set_design_sources
- set_current_design
-set_design_level
-set_dft_specification_requirements
- add_clocks
- check_design_rules
- create_dft_specification
-process_dft_specification

-set_context:
Context: unspecified, all contexts
Mode: all modes
Specifies the current usage context of Tessent Shell.
A required literal that sets the context to dft. In the basic dft context,
you load your design in setup mode and then move to the insertion
mode to execute design editing commands.

-rtl | -no_rtl
In dft context, these switches specify whether you are performing
netlist editing or RTL editing. You must use the -rtl option if you are
editing RTL.

- set_tsdb_output_directory:

Context: unspecified, dft, patterns

Mode: setup
Sets the TSDB output directory used by the process_dft_specification
command.

-read_verilog
Context: all contexts
Mode: setup
Reads one or more Verilog files into the specified or default logical
library.

You define the list of available libraries with the

set_logical_design_libraries command which
you only use in rtl context; only one library exists in no_rtl context
and it is named “work”.

-verbose :
An optional switch that reports each file read. For every file read,
including the ‘include
files, the following messages are returned.

-set_design_sources:
Context: unspecified, all contexts
Mode: setup
Specifies where the tool should look for the definition of undefined
modules in the list of files specified by the read_verilog command.

- set_current_design:
Context: all contexts
Mode: setup, insertion
Specifies the top level of the design for all subsequent commands
until reset by another execution of this command.

-set_design_level:
Context: dft, patterns
Mode: setup, insertion
Prerequisites: You can set the level can only after the design is
elaborated.
Specifies the level of the current design.
set_design_level {chip | physical_block | sub_block}.

-set_dft_specification_requirements:
Context: dft
Mode: setup
Specifies the requirements to be checked when the
check_design_rules command runs, and those to be included into
the DftSpecification when the create_dft_specification command is
run.

- add_clocks:
Context: all contexts
Mode: setup
Adds scan or non-scan clocks to the clock list for proper scan
operation.

- check_design_rules:
Context: dft, patterns
Mode: setup
Transitions the tool from setup mode to analysis mode.

- create_dft_specification:
Context: dft (with no sub context)
Mode: analysis
Creates the DftSpecification(design_name,id) configuration wrapper
and returns the newly created wrapper object so that it can be
stored in a variable and used to customize the created specification.

-process_dft_specification:
Context: dft (with no sub context)
Mode: setup, analysis
Validates and processes the content contained in a DftSpecification
wrapper.
Design 8 KB memory using 1 KB memory
module Memory_1KB (
input wire [9:0] address,
input wire [7:0] data_in,
input wire write_enable,
input wire read_enable,
output wire [7:0] data_out
);
reg [7:0] memory [0:1023];
always @(posedge clk) begin
if (write_enable)
memory[address] <= data_in;
if (read_enable)
data_out <= memory[address];
end
endmodule
module Memory_8KB (
input wire [12:0] address,
input wire [7:0] data_in,
input wire write_enable,
input wire read_enable,
output wire [7:0] data_out
);
wire [9:0] addr_1kb [0:7];
wire [7:0] data_out_1kb [0:7];
assign addr_1kb[0] = address[9:0];
assign addr_1kb[1] = address[9:0] + 1024;
assign addr_1kb[2] = address[9:0] + 2048;
assign addr_1kb[3] = address[9:0] + 3072;
assign addr_1kb[4] = address[9:0] + 4096;
assign addr_1kb[5] = address[9:0] + 5120;
assign addr_1kb[6] = address[9:0] + 6144;
assign addr_1kb[7] = address[9:0] + 7168; Memory_1KB mem0 (
.address(addr_1kb[0]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[0])
);
Memory_1KB mem1 (
 .address(addr_1kb[1]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[1])
);
Memory_1KB mem2 (
.address(addr_1kb[2]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[2])
);
Memory_1KB mem3 (
.address(addr_1kb[3]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[3])
);
Memory_1KB mem4 (
.address(addr_1kb[4]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[4])
);
Memory_1KB mem5 (
.address(addr_1kb[5]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[5])
);
Memory_1KB mem6 (
.address(addr_1kb[6]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
 .data_out(data_out_1kb[6])
);

Memory_1KB mem7 (
.address(addr_1kb[7]),
.data_in(data_in),
.write_enable(write_enable),
.read_enable(read_enable),
.data_out(data_out_1kb[7])
);
assign data_out = data_out_1kb[0];