1
A High Step-Up Isolated DC-DC Converter
Based on Voltage Multiplier Cell
Bernardo Andres, Leonardo Romitti, Fabrício H. Dupont, Leandro Roggia and Luciano Schuch,
Member, IEEE

Abstract—Generating sources of renewable systems, like
photovoltaic module or fuel cell, have a low output voltage that has
to be boosted for most of applications, such as grid-tie inverters.
To accomplish this, an isolated dc-dc high step-up SEPIC (single
ended primary inductor converter) with a Greinacher voltage
doubler cell is presented. It has the advantage of continuous input
current, high efficiency, high voltage gain, isolation and demands
a single switch, being suitable for low power grid-tie photovoltaic
systems. The operating principles and steady-state analysis are
presented, including the detailed analysis of resonant stage and the
effects of transformer winding capacitances on converter
operation are investigated. Moreover, the effects of resonance
frequency variations on converter efficiency is experimentally
investigated. Experimental results on a 50 kHz, 200 W prototype
are presented to validate the proposed concept.
Index Terms—Isolated SEPIC, Resonant stage, Voltage
multiplier cell.
I. INTRODUCTION
H IGH step-up converters are often used in renewable
systems, specifically in low power grid-tie systems with
two converters, where the output voltage of the photovoltaic
module is low and has to be boosted, making the high-step up
dc-dc converter very attractive [1]. These systems, as shown in
Fig. 1, are also known as ac photovoltaic modules (module-
integrated-converter – MIC), where a high step-up converter, in
first stage, provides a high voltage gain and is connected to a
grid-tie inverter [2]. A great number of isolated and non-
isolated topologies have been proposed for this application.
Several classic non-isolated step-up converters can be used,
however, as many of them present reduced voltage step-up ratio
[3], methods to increase voltage gain are needed, such as
cascade boost converters, coupled-inductor based boost
converters, switched capacitor, switched inductor, voltage
multiplier, among others [4]-[5]. Voltage multiplier cells
(VMCs) applied on secondary side provide the advantages of
increased converter static gain, in some cases clamping the
voltage spikes on diodes, without elevating voltage stress over
the switch, unlike voltage boost techniques applied on primary
This work was supported by Coordenação de Aperfeiçoamento de Pessoal
de Nível Superior – Brasil (CAPES/PROEX) – Financial Code 001, INCTGD,
CNPq (465640/2014-1), CAPES (23038.000776/2017 – 54), FAPERGS
(17/2551-0000517-1).
Bernardo Andres, Leonardo Romitti, Leandro Roggia and Luciano Schuch
are with Power Electronics and Control Research Group, Department of
Fig. 1. MIC converter with emphasis on first stage.
side. These VMCs used on secondary side are based on
switched-capacitor techniques and the most commonly used are
known as voltage doubler (VD) and voltage tripler (VT), with
the possibility of expansion to raise voltage gain, although
increasing the number of converter components [4].
Many authors have proposed new topologies with high
voltage gain without using transformer, combining voltage
boosting techniques and the use of snubber circuit to reduce
voltage spikes across the switch [5], or replacing diodes with
synchronous switches, achieving soft-switching and reducing
EMI issues [6]. Despite of its advantages, non-isolated
converters require additional circuits or techniques to mitigate
leakage current.
Galvanic isolation is desirable for this application in order to
maintain security of the whole system, besides mitigating
leakage current and electromagnetic interference (EMI)
problems [7]. Therefore, regarding isolated converters, in [8] a
high voltage gain converter with a lower transformer turn ratio
is obtained, through the integration of cascading boost with an
isolated buck-boost converter and mitigating voltage spike
caused by leakage inductance. Despite of its advantages, this
converter has a large number of switches, which significantly
increases the cost of whole system and, besides that, maximum
efficiency obtained is not attractive for this application. There
are other options to increase maximum efficiency and obtain
high voltage gain, with the use of a resonant full-bridge
converter, replacing the secondary diodes with active switches,
obtaining soft-switching conditions for diodes and switches [9]
or with addition of a voltage multiplier on secondary side,
reducing turn ratio of transformer [10]. Although these
advantages were experimentally validated, those converters still
Electrical Engineering, Federal University of Santa Maria, Santa Maria
97015900, Brazil. (e-mails: adoandres, Leonardo.romitti, roggia, schuch.prof
{@gmail.com})
Fabrício Hoff Dupont is with Technology Development Group, Community
University of Chapecó Region, 89809-900, Chapecó. (e-mail:
fhdupont@gmail.com)

Fig. 2. Isolated SEPIC derivation: (a) Classic SEPIC; (b) Isolated SEPIC using cantilever model; (c) Isolated SEPIC with VMC on secondary side.
have the same problem of excessive number of active switches
for a low power application.
In this low power application, some authors have proposed
a single switch converter, using coupled inductor for isolation
and VD circuit on secondary side to increase voltage gain [11].
Despite of these advantages, this topology has a large leakage
inductance, due to coupled inductor, which requires an
additional snubber circuit. Furthermore, maximum efficiency is
obtained in a very low power, while in the full-load condition
this value is considerably lower. Similar to this, a current-fed
converter with high voltage gain also uses a voltage multiplier
on secondary and a snubber circuit on primary, mitigating
voltage spikes across the switch [12]. Once again, the problems
are low maximum efficiency in the full-load condition, besides
the requirement of using a snubber circuit due to high leakage
inductance. Some other works proposed different snubber
circuits that can be used in single switch converters with high
leakage inductance [13]-[14], but, even with the improvements,
in general the results are unattractive, without reaching a high
efficiency, considering the addition of an auxiliary circuit.
Therefeore, single switch converters are more suitable for
lower power applications, reducing volume, costs and
complexity. Basic single switch isolated topologies are:
flyback, ZETA, SEPIC and Ćuk. Flyback converter is suitable
for low power applications, however, it has low efficiency
because of the high voltage and current stresses on the
components [15]. Moreover, it presents problems regarding to
high leakage inductance, due to its coupled inductor, which
causes several voltage spikes across the switch and rectifying
diode, and discontinuous input current, requiring a large input
capacitance [16]. Isolated ZETA converter has the same
problem of discontinuous input current and high leakage
inductance. Those two converters always require a coupled
inductor for isolation, even with the use of different cells to
increase its voltage gain. Among these options, isolated SEPIC
and Ćuk converters are a good option for this application, since
they provide continuous input current, however, Ćuk has a
higher component count, in standard version and with increase
of cells, as shown in [17]. Hence, isolated SEPIC (iSEPIC) is a
very good choice, with low component count, and significantly
reducing the dc magnetizing current with the appropriate choice
of voltage multiplier cells (VMCs), allowing to use a
transformer instead of coupled inductor [18], besides increasing
voltage gain.
Therefore, this paper proposes an isolated single switch dc-
dc converter achieving high voltage gain and high efficiency
using a transformer for galvanic isolation without using a
snubber circuit, which significantly reduces volume and cost of
the whole system. To achieve this, a VD cell is used on
secondary side of an iSEPIC. The derivation of proposed
2
converter is presented in Section II. In [19] a similar topology
is presented, however, some notables differences in our work
are: reduced leakage inductance and higher magnetizing
inductance, no use of snubber circuit with low voltage stress
across the switch and, besides that, primary capacitor C is taken
into account on resonance analysis and effects of winding
transformer capacitance are investigated.
The converter has the following features: 1) quasi zero-
current switching (qZCS) turn-on of switch disregarding the
use of snubber circuit; 2) ZCS turn-off of all diodes, mitigating
losses associated with diode reverse recovery; 3) Clamp of
voltage spikes across the diodes; 4) Small input current ripple
due to input inductor; 5) Reduced voltage spikes across the
switch, without use of snubber circuit, due to low leakage
inductance of transformer; 6) High efficiency with low cost,
achieving high voltage gain. Experimental results on a 50 kHz,
200 W prototype are presented to validate these features.
In Section II, the derivation of converter is presented,
showing some cells used on secondary and its influence on
magnetizing current, justifying the choice of VD cell. In Section
III, theoretical analysis of proposed converter is presented, with
emphasis on resonant stage and effect of winding transformer
capacitance on converter operation. Experimental results are
shown in Section IV, validating the proposed concept and
verifying the effects shown on previous section. Section V
concludes the paper.
II. DERIVATION OF CONVERTER
From the classic SEPIC topology, shown in Fig. 2a, the
iSEPIC is obtained substituting the inductor Lo by a coupled
inductor, using the Cantilever model, which is an interesting
option to represent the magnetic element (transformer or
coupled inductor) on isolated converters [20], as shown in Fig.
2b. In order to increase the voltage gain without increasing the
voltage stress over switch, the VMC is added on secondary side,
as shown in Fig. 2c. Greinacher VD cell, Dickson and Ladder
VT cells, shown in Fig. 3, are interesting options that can be
used on secondary side [21]-[23]. Besides the increase of
voltage gain, the circuit of these cells mitigates the voltage
spikes over the diodes. As aforementioned, an appropriate
choice of VMC can significantly reduce the dc magnetizing
current, guaranteeing that the magnetizing inductance, Lmag¸
does not store energy. Thus, a transformer is used for galvanic
Fig. 3. Cells applied on secondary to increase voltage gain.

Fig. 4. Isolated SEPIC: (a) classical; (b) with VD; (c) with VT.
isolation instead of a coupled inductor, consequently providing
a better utilization of BxH curve, reducing its volume and its
leakage inductance, Lr [20]. This can be achieved by the use of
VD, but it is not possible with VT cells.
To better understand this, Kirchhoff current law (KCL) is
applied on indicated node in Fig. 4, where classical isolated
SEPIC is presented with and without voltage cells on
secondary. Taking into account that the dc current is
theoretically null in a capacitor, the average magnetizing
current of the converters is given by
iLmag  avg   i1( avg )  iC ( avg )  ni2( avg ) . (1)
For the classical iSEPIC and with VT cell on secondary side,
the average magnetizing current is given by
iLmag  avg   ni2( avg )  nI o , (2)
where Io is the average output current. In these cases, the
magnetizing current has a dc component. For the iSEPIC with
VD cell on secondary side, the average magnetizing current is
given by
iLmag  avg   ni2(avg )  0. (3)
In this case, the average value of i2 is equal to the average
value of C1, therefore, there is no dc component in iLmag. A
simple approach, based on dc level of magnetizing current, is
shown in [24] in order to define if a couple inductor or a
transformer is used for isolation. Basically, the coupled
inductor has a dc level on magnetizing current, while
transformer theoretically has zero dc level on this current, as
Fig. 5. Comparison between coupled inductor and transformer.
3
shown in Fig. 5.
The main advantage of this feature is the use of a transformer
instead of a couple inductor. Besides the aforementioned
advantage of better utilization of BxH curve, leakage flux on
transformer is intrinsic and results of its design, while in
coupled inductor this is necessary to store energy, resulting in a
dc component on magnetizing current [24]. Leakage inductance
effects on power converters are well known and the main
concern is voltage stress across the switch, due to large spikes,
requiring a snubber circuit. Therefore, Greinacher voltage cell
applied on secondary of isolated SEPIC increases converter
static gain and efficiency while reduces volume and cost.
III. THEORETICAL ANALYSIS OF CONVERTER
The circuit of isolated SEPIC with VD Greinacher cell
(VDiSEPIC) is shown in Fig. 6. Some relevant issues to
theoretical performance of the converter are presented in this
section: principle of operation with detailed analysis of resonant
stage, voltage gain derivation, voltage stress, current stress, and
analysis of winding transformer capacitance effects.
A. Principle of operation
In order to simplify the steady-state analysis, the following
assumptions are made:
1) All power devices are ideal;
2) If a well-designed transformer is used, with a high-
quality material, the impact of magnetizing inductor,
Lmag, in converter operation, is small, however, to
provide higher accuracy in analysis, this inductor is
taken into account.
3) Output voltage is constant, therefore, capacitor Co is
not taken into account on the analysis.
The converter has three different resonant operation modes,
according to resonant period (Tr), switching period (Ts) and
duty cycle. This can be better understood with Fig. 7, where
these modes are presented. The best option is the first mode,
nearly to second mode, where total switching losses are smaller,
since that ZCS condition is obtained in all diodes and the value
of switch current on turn-off transition is smaller than in third
Fig. 6. Topology circuit of VDiSEPIC.
Fig. 7. Converter operation according to variation of resonance: (a) below
resonance operation – first mode: DTs > 0.5Tr; (b) exactly resonance
operation – second mode: DTs = 0.5Tr; (c) above resonance operation – third
mode: DTs < 0.5Tr.

Fig. 8. Key waveforms of VDiSEPIC in CCM operation.
mode. This will receive more attention during the description
of operation stage II and in experimental results.
Fig. 8 shows the key waveforms of the converter in one
switching period, in continuous-conduction-mode (CCM). It is
important to mention that these waveforms are obtained for
operation below resonance frequency. The converter has four
operation stages in one switching period, as shown in Fig. 9.
The converter operation is given as follows:
Stage I (t0 – t1): This stage begins when switch S1 is turned
on. For a short period, the current i1 has a linear decreasing, due
to the negative voltage over the leakage inductor,
demagnetizing it. This also happens with iD2, that has a linear
decreasing, with the same rate of i1 reflected to secondary side.
On the other hand, the switch current, iS, has a linear increasing,
with the same rate of i1. This results in a quasi-ZCS turn on of
the switch. This stage ends when current i1 reaches 0 A and
diode D2 is turned off under ZCS condition. The duration of this
stage is considerably smaller than stage II and, moreover, the
voltage ripple over the capacitors ideally is small, therefore,
because of this, the voltages across capacitors are constant on
this stage. The main equations of this stage are given by
v
vCr (t )  nVin  Cr  vCr  min  , (4)
2
4
Fig. 9. Current flow path in four stages during one switching period in CCM
operation: (a) stage I; (b) stage II; (c) stage III; (d) stage IV.
vc
vC (t )  Vin   vC  max  , (5)
2
V
iLin  t   iLin  t0   in t, (6)
Lin
vCr  min   Vo
vC  max  
i1  t   ni2 (t )  niD 2  i1 (t0 )  n t, (7)
Lr
vC  max 
iLmag  t   iLmag  t0   t, (8)
Lmag
is (t )  iLin  t   iLmag  t   i1  t  . (9)
Stage II (t1 – t2): This stage begins when current i1 changes
its direction, therefore, the diode D1 is turned on. A resonance
occurs among Lr and the equivalent capacitance, obtained from
a series association of Cr and C reflected to secondary. Hence,
during this stage, the current through D1 is sinusoidal, while the
current through the switch is a combination of this sinusoidal
current, from the resonance, with a trapezoidal current, from
input inductor, Lin. Currents through Lin and Lmag are increasing
linearly, since the voltage across Lin is equal to Vin and voltage
across Lmag is equal to vC. During this stage, the capacitor C is
discharged, while the capacitor Cr is charged. The equivalent
circuit, used to analyse the resonance and obtain the resonant
parameters, reflecting Lr and C to secondary, is shown in Fig.
10.
Taking into account that magnetizing inductance is
significantly higher than leakage inductance, this element can
be neglected in resonance analysis. In Fig. 10, leakage
inductance Lr is referred to secondary multiplying its
inductance by square of turn ratio, n², and C is referred to
secondary as CS, dividing its capacitance by n². The equivalent
 5

vc
vC (t )  Vin   vC  min  , (18)
2
Vin  T 
iLin  t   iLin  t 2   t  R  =iLin  max  , (19)
Lin  2 
Fig. 10. Converter equivalent circuit of resonant stage. vC min  T 
capacitance is composed by a series association of Cs and Cr.
iLmag  t   iLmag  t2      t  R  =iLmag  max  , (20)
Lmag  2 
Therefore, Ceq, resonance frequency, fr, and resonant
is (t )  iLin  t   iLmag  t  . (21)
impedance, Zr, are given by

C Stage IV (t3 – t4): This stage begins when switch is turned

Cr 2 off. Since the current i1 is equal to zero at the beginning of this
Ceq  n , (10)
C stage, there is no change on its polarity, as happens in stage I,
Cr  2 therefore, there is no soft-switching in this stage and, moreover,
n
differently from stage 2, this one occurs without resonance, and,
1 1 1 n 2 Lr consequently, currents and voltages are not sinusoidal. In this
fr  ;  ; Zr  . (11)
2π  r Tr 2π C n 2 L C eq stage, the capacitor C is charged, while the capacitor Cr is
eq r
discharged. The voltage across Lin is the difference between Vin
Using Kirchhoff’s voltage law (KVL), and applying Laplace and VDS¸ resulting in a linear decreasing of iLin, while voltage
Transform and inverse Laplace Transform, considering initial across Lmag is the difference between vC and VDS, also resulting
conditions of i1 and vCeq, as shown in [25], i1 is obtained in time in a linear decreasing of iLmag. This stage ends when switch is
domain, given by turned on. The main equations are given by

Ceq  iLin  max   t  DTs   ... 

i1 (t )  ni2 (t )   niD1  n vCeq (0)sin(wr t ), (12)
n 2 Lr 1 
vC  t   vC  min     t  DT 2 V  V   (22)
C  s DS in

where vCeq(0) is obtained by the difference between vCr(0) and  
 2 Lin 
nvC(0). The main equations are given by
 iLin max   t  DTs   .. 
 
vC (t ) 

CvC (0)  Ceq nvCeq (0)  Ceq nvCeq (0))cos(wr t )   iLmag  max   t  DTs   .. 
C  
(13) 1   t  DTs 2 VDS  Vin  
vCr (t ) 

Cr vCr (0)  Ceq vCeq (0)  Ceq vCeq (0)cos(wr t )  vCr  t   vCr  max     ..  (23)
nCr  2Lin 
Cr
 2 
iLin  t   iLin  t1  
Vin
t, (14)   t  DT  VDS  Vin  
Lin  
 2Lmag 
vC (t )
iLmag  t   iLmag  t1   t, (15) VDS  Vin 
Lmag iLin  t   iLin max    t  DTs  , (24)
Lin
is (t )  iLin  t   iLmag  t   i1  t  . (16)
VDS  Vin 
iLmag  t   iLmag  max    t  DTs  , (25)
This stage ends when current i1 reaches 0 A, and, Lmag
consequently, diode D1 is turned off under ZCS condition. i1  t   iLin  iLmag  ni2 (t )  niD 2 . (26)
Stage III (t2 – t3): This stage begins after resonance is over.
If the converter operates close to second mode, as shown in Fig. B. Voltage gain
7, the duration of this stage is considerable smaller than The process to obtain the static gain of this converter,
previous stage. The capacitor C is in series with Lmag, and its applying the volt-second balance to the input inductor, Lin, is
voltage, vC, can be considered constant, as well as voltage vCr. shown in [25], resulting in
The voltage over Lr is practically null, as well as the current i1,
that is equal to zero until the switch is turned off. This stage Vo n
ends when S1 is turned off, with losses, without soft-switching. M   . (27)
Vin 1  D
This stage happens in first and second modes of operation, but
not in third. The main equations are given by C. Voltage and current stress
The voltage stress over the switch is given by
vCr
vCr (t )  nVin   vCr  max  , (17)
2
 6

Vin V
VDS   o. (28)
1 D n
For diodes D1 and D2, the voltage stresses are given by

nVin
VD1  VD 2  Vo   (29)
1 D

Even with the increase of static gain, voltage stress across

the switch is the same of isolated SEPIC, while voltage stress
on diodes is smaller. RMS equations of currents are deduced
and presented in [25], playing an important role on converter
design and losses estimation.
Average voltage over the capacitors is given by
V 1  D 
VC  Vin  o ,
n
VC1  nVin  Vo 1  D  , (30)
nVin
VCo  Vo  .
1 D
D. Voltage and Current Ripples
The percentage ripple of iLin, vC, vCr and vCo is given by
DVin  100 
iLin  %   iLin  DTs   iLin  0     (31)
Lin f s  I in 
Fig. 12. Impact of Ct: (a) before the beginning of stage II; (b) in currents of
I in 1  D   100  converter’s operation.
vC  %   vC Ts   vC  DTs     (32)
Cf s  Vin  0 A, starting the discharge of equivalent capacitance, Ct.
I in 1  D   100  Ideally, disregarding voltage ripple of capacitors, during this
vCr  %   vC1  DTs   vC1 Ts     . (33) short period, voltage across Ct is changed from Vo/n – Vin to Vin,
nC1 f s  nVin 
resulting in a linear current. The impact of Ct is shown in Fig.
DI o  100  12a, where waveforms of iCt, i1, iCr, iD1 and iD2 are shown, giving
vCo  %   vCo  DTs   vCo Ts     . (34) a zoom between beginning and the end of Ct discharge. In Fig.
Co f s  Vo 
12b, key current waveforms are shown for a switching period.
These equations will be used in next section to determine
It can be seen from these waveforms that the main effects of
the minimum values of the inductance and capacitances.
Ct discharge are the reduction of resonant period, once linear
E. Winding transformer capacitance current cuts off part of original resonant period compared to
Cantilever model can be used to represent a transformer, when Ct is disregarded, and the increase of peak value of is and
however, stray capacitances are not taken into account. A real iD1 and minimum value of i1.
transformer has windings self-capacitances and interwinding
capacitances. Self-capacitances can be represented on primary IV. EXPERIMENTAL RESULTS
side by a single equivalent capacitance, similar to what is done A 200 W prototype of the converter was built and tested to
with leakage and magnetizing inductances [26], and has an validate the proposed concept.
important impact on converter operation, specifically affecting
the resonance of stage II. Interwinding capacitance couples A. Design Guidelines
primary and secondary voltages and gives an indication of how The input voltage is equal to 37.4 V, due to voltage at
much common mode noise is allowed, but can be disregarded maximum power point of a Canadian photovoltaic module,
on four stages of converter’s operation. model CS5A-200M [27], with a maximum power of 200 W, for
Therefore, referring self-capacitance of secondary to an irradiance of 1000 W/m², while output voltage is equal to
primary and disregarding interwinding capacitance in this case, 400 V, an usual value used in grid-tie inverters. Therefore, the
results in an additional stage, shown in Fig. 11, when i1 reaches required static gain is 10.695, while average output current is
equal to 0.5 A. A duty cycle of 0.44 was chosen, keeping
balance between efficiency, turn ratio and voltage stress across
semiconductors. Similar values are widely used in the
conception of high static gain converters with similar values of
input voltage and output power [28]-[29]. Briefly, this occurs
since that high values of duty cycle significantly increases the
Fig. 11. Discharge of capacitance Ct.

voltage stress over switch. On the other hand, low values of
duty cycle increase the required turn ratio, which causes more
transformer losses. Therefore, turn ratio has to be equal to six
to obtain the specified output voltage. Finally, switching
frequency is equal to 50 kHz.
1) Transformer
The transformer was acquired through a local supplier of
magnetic materials, called Magmattec – Technology in
Magnetics Materials. The design of this component was made
considering a maximum flux density of 0.51 T, using two
nanocrystalline cores, model 2xMMT520T40.31.10B [30], in
parallel. These cores have positive characteristics that provide
low leakage flux and consequently a small leakage inductance.
The primary coil is composed of three AWG 20 wires in
parallel, resulting in a copper wire resistance of 9 mΩ. The
secondary coil is composed of one AWG 25 wire, resulting in a
copper wire resistance of 318 mΩ. The leakage inductance is
500 nH, while the magnetizing inductance is 1 mH.
2) Capacitors
The input capacitor and resonant capacitor are defined by
two conditions: maximum voltage ripple of 5% and an
equivalent capacitance Ceq that guarantee converter operation
below resonance operation, according to (10)-(11). From (32),
the minimum capacitance obtained is equal to 32 µF. From (33),
the minimum capacitance obtained is equal to 890 nF. It is
important highlight that the winding transformer capacitance
has a significant impact on resonant waveforms. Briefly, the
discharge of this capacitance directly affects the resonant stage
II, therefore, a linear current cuts off part of resonance, reducing
its period. The experimental results in next section will show
this effect. Therefore, the solution is to test the converter using
capacitance values for C and Cr close to what was obtained with
(32) and (33), and slowly increase these values until converter
is operating near the condition Tr/2 = DTs. As to the output
capacitor, the maximum voltage ripple defined is equal to 0.1%,
therefore, according to (34), the minimum capacitance obtained
is equal to 11.2 µF.
3) Input Inductor
The input inductor was chosen to guarantee a maximum
current ripple of 30%. From (31) the minimum inductance
obtained is 205 µH. Therefore, an inductor was made using a
Kool Mu toroidal core, model 77090 [33], with an AC flux of
0.035 T. A single AWG 18 wire was used with 35 turns,
resulting in a DCR equal to 38 mΩ. The obtained inductance is
equal to 220 µH.
4) Semiconductors
The choice of the semiconductors is based on maximum
voltage and current stresses over them. Therefore, the chosen
switch is the IPP051N15N5, while the chosen diodes are
MUR860.
B. Experimental Results
The prototype specification is shown in Table I. Tektronix
Encore MD03000 oscilloscope and a Yokogawa WT1600
power meter were used to measure main parameters.
As aforementioned, the experimental resonant period has a
substantial difference to the theoretical due to the effect of
winding transformer capacitance. Different from C and Cr, that
7
TABLE I
Main Parameters and Component Rating
Parameter/Component Specification/Value
Input Voltage 37.4 V
Duty Cycle 0.44
Output Voltage 400 V
Switching Frequency 50 kHz
Switch S IPP051N15N5 (150 V/120 A, 5.1 mΩ)
Diodes D1, D2 MUR860 (600 V/8 A, vf = 0.9 V)
Transformer
500 nH, 1 mH, 8:48, 2xMMT520T40.31.10B [30]
Lr, Lm, N1:N2, Core
9 mΩ (3x20 AWG), 318 mΩ (1x25 AWG)
DCR N1, DCR N2
Input Inductor Lin 220 µH/ 77090 [33]/ DCR: 38 mΩ (1x18 AWG)
4x10 µF/100 V Electrolytic ESK106M063AC3 (32 mΩ)
Input Capacitor C
3x3.3 µF/100 V film BFC246804335 (10 mΩ)
Resonant Capacitor Cr 3x470 nF/250 V film BFC246817474 (8 mΩ)
Output Capacitor Co 1x100 µF/450 V Electrolytic B43505C5107M000 (960 mΩ)
resonate with Lr, this intrinsic capacitance cuts off part of the
resonant current in the beginning of stage II. Therefore, the
converter was initially tested with the capacitance C equal to 33
µF and the capacitance Cr equal to 1 µF. According to (11),
considering theses capacitances, the leakage inductance, the
switching period and duty cycle, half of the resonant period has
a closer value to the period that switch is ON, being equal to 8.8
µs. However, in the experimental test, half of resonant period
has an approximate value of 7 µs. Taking this into account, both
capacitances were increased until Tr/2 has a close value to DTs.
This condition is obtained for C = 50 µF and Cr = 1.4 µF.
According to (29) and (30), the ripple of vC is equal to 3.2%,
while ripple of vCr is equal to 3.18%. Due to the low availability
of capacitors in the laboratory, to achieve the required
capacitances, C is composed of a parallel association of
electrolytic and film capacitors, while Cr is composed of a
parallel association of film capacitors.
Fig. 13 shows main waveforms of switch at full-load
condition with a zoom on turn-on transition. iS waveform shows
that converter is operating near to second mode, since half of
resonant period is lower than the period that switch is on, and
the effect of Ct can be seen, being in agreement with theoretical
analysis and waveforms of Fig. 12. Furthermore, the zoom on
turn-on transition shows that turn-on switching losses are
negligible. Finally, it can be seen there is a voltage spike across
switch due to leakage inductance of transformer, although, this
is not a concern, once that maximum voltage across switch is
95 V, while maximum voltage of switch S1 is 150 V and there
is no need to use an additional snubber circuit. This happens
because leakage inductance has a small value, a positive
characteristic of well-designed transformers using
nanocrystalline core.
Fig. 14 shows main waveforms of transformer. The
waveform of i1 confirms the converter operation in first mode,
10 V/div
vGS
vDS iS
50 V/div
vDS
10 A/div
iS 100 ns
10 µs
Fig. 13. Experimental waveforms of switch S1 with zoom on turn-on.
 8

20 V/div
vGS
10 A/div
i1
50 V/div

v n1
250 V/div
vn2 10 µs

Fig. 14. Experimental waveforms of transformer.

besides showing the effect of Ct discharge after its value reaches

0 A. As well as voltage across the switch, there is a voltage
spike across primary winding, however, it is not a concern,
since voltage peak is not high. Differently, on secondary side
the voltage is clamped because of capacitors, without spikes, an
effect that also occurs on diodes, as shown in Fig. 15. Voltage
stress across diodes is close to output voltage, with a value of -
411 V.
In Fig. 16, turn-off transition of diodes D1 and D2 is shown,
verifying ZCS condition. To understand this, waveforms of
secondary current, i2, and voltages across diodes are shown. For
diode D1, it can be seen that when i2 reaches 0 A, stage I ends,
with its voltage remaining 0 V. According to Fig. 11, before
resonance begins, there is a linear current due to Ct discharges,
and this can be seen in Fig. 15. For diode D2, ZCS condition
depends on the operation mode of converter and, as shown
before in experimental waveforms of switch and transformer,
this is achieved.
In section III, it was affirmed that, considering Fig. 7, first
operation mode, nearly to second mode, is the best choice for
this converter. To better understand this, Fig. 17 shows i1, is and
iD1, varying the resonance frequency through the variation of
Cr. To experimentally verify this, the secondary capacitance
was varied, testing four different values: 0.43 µF, 0.9 µF, 7.97
µF and 10.33 µF, in order to obtain different operation modes.
The result is shown in Fig. 18, where waveforms of vGS, i1 and
is are shown, respectively. There is a substantial difference
among these tested values, since resonant period has higher
variations for lower values of Cr. As the capacitance value is
increased, variations of resonant period are smaller, therefore,
20 V/div
vGS
i In Fig. 20, the converter efficiency is presented for different
2
10 A/div
v D2
250 V/div
vD1
250 V/div 10 µs
Fig. 15. Experimental waveforms of diodes.
i2 1 A/div vD1 250 V/div
ZCS turn-off
ZCS turn-off
vD2
250 V/div
i2 2 A/div
Fig. 16. Experimental waveforms of turn-off transition for diodes.
Fig. 17. Impact of Cr and resonance frequency in i1, is and iD1.
it was necessary to use capacitance values considerably higher
than shown in Table I.
The results show that as the capacitance value is reduced,
resonant period is shorter, increasing current peak and
consequently increasing RMS value of these currents, which
reduces converter’s efficiency, since conduction losses are also
increased. On the other hand, as the capacitance value is
increased, resonant period is longer, decreasing current peak
and RMS value of these currents, however, ZCS condition is
lost, since half of resonant period is higher than the period that
switch is ON. Besides that, higher values of capacitance
increase converter volume, which is undesirable for this
application. To verify this analysis, Fig. 19 shows converter
efficiency varying capacitance of Cr, with a nominal power of
200 W, measured by YOKOGAWA WT300. It can be seen that
maximum efficiency is obtained for values slightly higher than
1.5 µF and lower than 2 µF, therefore, according to Table I, the
selected value for Cr is an appropriate choice.
C. Efficiency Results and Loss distribution
output power levels. It is important to highlight that the
capacitance value of Cr used to obtain the efficiency curve is
the same shown in Table I, equal to 1.4 µF. The maximum
measured efficiency is 96.85 % at 180 W, while the full-load
efficiency is 96.6 %. The European weighted efficiency of
converter is 95.8 %, while Californian energy commission
weighted efficiency is 96.3 %. It is important to highlight that
the converter efficiency is higher than 96% for most part of the
output power range, as shown in Fig. 20. It is important to
highlight that the converter efficiency is higher than 96% for
most part of the output power range, proving that a high
efficiency can be achieved when following the considerations
approached in this paper regarding the cell selection for the
 9

20 V/div 20 V/div
v GS v GS

10 A/div 10 A/div

i1 i1
is is
10 A/div 10 A/div

(a) (b)

20 V/div 20 V/div
v GS vGS
10 A/div 10 A/div

i1 i1
is is
10 A/div 10 A/div

(c) (d)
Fig. 18. Experimental waveforms of vGS, i1 and is using: (a) C1 = 0.43 µF; (b) C1 = 0.9 µF; (c) C1 = 7.97 µF; (d) C1 = 10.33 µF.

calculation. The losses of diodes are given by

Fig. 19. Measured efficiency varying capacitance Cr.
Fig. 20. Measured efficiency of the converter.
converter.
To understand the efficiency behavior, the losses estimation
is evaluated. In this sense, the losses of each component were
calculated. In relation to the switch, the losses can be calculated
by
 
Ps  RDS (on )is ( RMS ) 2  0.5 f s  VDS is t 3  toff  ton VDS 2Coss  . (35)
 
Where RDS(on) is the static drain-to-source ON-resistance,
is(RMS) is the rms current of switch, fs is the switching frequency,
VDS is the maximum voltage stress over the switch, is(t3) is the
switch current at instant t3, toff and ton are the switching time for
turn-on and turn-off and Coss is the output capacitance provided
by manufacturer [31]. An important issue to highlight in this
case is that the switch current on turn-off (t3) is equal to the
maximum value of iLin. This value is obtained considering Iin
and the current ripple ∆iLin.
Since there is a qZCS condition, the ton is disregarded on
2
PD   I Dx ( avg ) v f . (36)
x 1
Where x can be 1 or 2, the ID(avg) is the average current of
each diode and vf is the forward voltage given by the
manufacture datasheet [32]. Since both diodes achieve ZCS
condition for turn-off transition, these losses can be neglected.
The inductor losses can be calculated by
PLin  DCRLin iLin ( RMS ) 2  PL Ae le . (37)
Where DCRLin is the copper wire resistance and iLin(RMS) is
the RMS current of input inductor. The parameter PL is the core
loss density, defined by PL = aBpkbfsc, where a, b and c are
constants given in the datasheet and Bpk is the AC magnetic flux
density. The value of PL also can be determined from the chart
provided by the manufacture core information [33]. Ae is the
transversal core area and le is the core medium path length. Both
parameters are also available in [33].
The transformer losses are the sum of copper losses and core
losses and can be calculated by
PT  DCRn1i1( RMS ) 2  DCRn 2 i2( RMS ) 2  Pe  Ph (38)
Where DCRn1 and DCRn2 are the copper wire resistance of
primary and secondary coil, respectively, i1(RMS) and i2(RMS) are
the RMS current of primary and secondary coil, respectively.
Pe is the eddy current loss and Ph is the hysteresis loss. Usually,
the core manufacture datasheet provides a graph relating the
power loss density versus peak AC flux density. In this case,
the local supplier gives an estimation of core losses based on
the peak AC flux density of 0.51 T, considering the graph of
power loss density presented in [30].
The capacitor losses are given by
3
PC   ESRI C ( RMS ) 2 (39)
x 1
In this case, since the input capacitor is composed by some
capacitors connected in parallel, including film capacitors, the
ESR is significantly reduced so that the losses associated to this
element are small. The same occurs for resonant capacitor,
since RMS current on secondary is smaller than on primary and
only film capacitors were used. Therefore, most of capacitor
 10

loss distribution is shown in Fig. 21. It is important to highlight

that the use of transformer associated to a cell on secondary side
enable to choose a switch with a low value of RDS(on), which
reduces the conduction losses, while the qZCS reduces the
switching losses. The ZCS condition for both diodes associated
to a low average current results in less than 1 W of losses in
these elements. Therefore, it is expected that the majority of
losses are associated to the transformer, however, its losses
reduces less than 1.5% of converter efficiency. It is important
to mention that losses associated to input inductor are higher
Fig. 21. Efficiency evaluation: Loss distribution.
than in semiconductors, which confirms that the insertion of
this component on primary side is not a suitable choice, since it
losses are due to the output capacitor. can degrade converter efficiency and increase voltage over
In order to validate the currents of converter components, a switch. Finally, the obtained theoretical efficiency for 200 W is
digital simulation was performed in PSIM®. After that, using all equal to 96.85%, while the experimental efficiency is equal to
the losses equations and MATLAB software, the losses and 96.6%, therefore, there is a small difference of 0.25%, which is
efficiency of converter were calculated for full-load condition. equivalent to 0.5 W.
All the RMS equations can be found in [25]. The result of the Finally, Table II shows a comparison among the presented
TABLE II
Comparison among proposed converter with other converters presented in the literature
Converter Static Gain Specification Voltage over main switch Maximum Efficiency Full-load efficiency Isolated
fs = 50 kHz
n Po = 200 W Vin V
VDiSEPIC
Vin = 37.4 V = o 96.85% 96.6% Yes
1 D 1 D n
Vo = 400 V
fs = 50 kHz
nD Po = 100 W Vin V
[34]
Vin = 48 V = o 95.8% 93.8% Yes
1 D 1  D nD
Vo = 200 V
fs = 50 kHz
1 D Po = 300 W Vin Vo
[35] 2n = 95% 93.3% Yes
1  2D Vin = 25 V 1  2 D 2n 1  D 
Vo = 400 V
fs = 50 kHz
[36]
 3  2n2  n3  Po = 216 W Vin
=
Vo
96.2% 96% No
1 D Vin = 38 V 1  D  3  2n2  n3 
Vo = 200 V
fs = 30 kHz
n+2+D Po = 220 W Vin Vo
[37] = 96.2% 94% No
1  D  Vin = 26V 1 D n  2  D
Vo = 300 V
fs = 50 kHz
1  D  2n 1  D  Po = 200 W Vin Vo (1  D)
[38]  96.1% 94% No
1  D  2 V in = 20 V 1  D  1  D  2n 1  D 
Vo = 200 V
fs = 50 kHz
D Po = 100 W DVin Vo
[39] = 91.4% 91.4% No
1  D 2 Vin = 24 V
Vo = 172 V
1 D n
fs = 40 kHz
1  3D Po = 200 W Vin V
[40]
Vin = 20 V = o 94.5% 93% No
1 D 1  D 1  3D
Vo = 250 V
fs = 50 kHz
1  nD Po = 200 W 1  nD
[41] 1  D  Vin 1  D   VC 2  Vo  VC 2 94.3 92. No
1  D  Vin = 24 V 1  D 
Vo = 200 V
fs = 50 kHz
1  nD Po = 221 W M n M n
[42] 1  D  Vi  V 94.8 93.2 No
1  D  Vin = 28 V  n  2 M  n  2 o
Vo = 388 V
fs = 33 kHz
1 D Po = 120 W MVi  2 Vo  2
[43] 2  94.4 92.5 No
1  D  Vin = 12 V 2MVi 2Vo
Vo = 94.86 V
fs = 50 kHz
3  2n2  n3 Po = 250 W Vi Vo
[44]  95.9 95.4 No
1 D Vin = 29 V 1  D 3  2 n2  n3
Vo = 450 V
fs = 50 kHz
2  n  nD Po = 250 W Vi Vo
[45]  96.58 92.21 No
1  D 2 Vin = 16 V 1  D 2  n  nD
Vo = 400 V

3 "A survey on voltage boosting techniques for step-up DC-DC converters,”
8 8.
4 1 - Gate Driver Source
2 - Gate Driver
3 - Input inductor
4 - Switch
5 - Transformer
1 2 7 6 - Resonant Capacitor
7 - Diodes
5 6 8 - Output capacitor
Fig. 22. Photograph of converter prototype.
converter with other converters presented in literature. To
perform this, the switching frequency and input and output
voltage levels have to be equal or at least has a close value, in
order to be able to compare the efficiencies. In general, it can
be seen that VDiSEPIC achieve a high static gain and, in most
cases, the maximum and full-load efficiency are significantly
higher than the other converters. Moreover, due to the low
values of leakage inductance, the presented converter shows
attractive results without the need of snubber circuits. The
converter prototype is shown in Fig. 22.
V. CONCLUSIONS
In this paper, a high voltage gain single switch isolated dc-
dc SEPIC with voltage doubler cell was proposed for primary
stage of a MIC for photovoltaic applications. Theoretical
analysis, with emphasis on resonant stage, besides the influence
of winding transformer capacitance, was performed. In
addition, the use of a nanocrystalline core with a well-designed
transformer results in a low leakage inductance, which enables
the converter to operate without an additional snubber circuit,
maintaining the safety of switch. Effects of transformer winding
capacitance were investigated, including the impact on current
waveforms of converter, which directly influences on resonant
stage. Experimental results show the qZCS condition for power
switch, besides the ZCS condition for both diodes, reducing
switching losses of converter. Measured efficiency modifying
resonant period through the variation of capacitance Cr shows
that maximum efficiency occurs when converter is operating at
first mode, near to second mode. Finally, maximum efficiency
of 96.85% was obtained close to full-load condition, achieving
a high voltage gain with low component count, as initially
desired.
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