ISSCC2023-Amplifiers and Oscillators

ISSCC
2023
SESSION 3
Amplifiers and Oscillators
A 120.9dB DR, -111.2dB THD+N
Digital-Input Capacitively-Coupled
Chopper Class-D Audio Amplifier
Huajun Zhang1, Marco Berkhout2, Kofi A. A. Makinwa1, Qinwen Fan1
1Delft University of Technology, Delft, The Netherlands

2Goodix Technology, Nijmegen, The Netherlands
© 2023 IEEE 3.1: A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier
International Solid-State Circuits Conference 1 of 47
Outline
 Digital-Input Class-D Audio Amplifiers
 Digital-Input Capacitively-Coupled Chopper
Class-D Amplifier
 Implementation Details
 Measurement Results
 Conclusion
Digital-Input Class-D Amplifier (CDA)
 Switching output stage  high efficiency

 Mostly digital implementation
 Distortion due to non-ideal switching (e.g. dead time)
 High supply sensitivity
Closed-Loop CDA
[T. Ido, ISSCC’06]

[E. Cope, ISSCC’18]
 Feedback loop suppresses output-stage distortion

 LC filter adds distortion
 IDAC/RDAC limits DR and THD
Digital Feedback after LC Filter
[D. Schinkel, JSSC’17]
 ADC senses LC output  LC distortion suppressed

 IDAC/RDAC limits DR and THD
Capacitive Feedback CDA
[H. Zhang, ISSCC’22]
 Noiseless feedback network

 Chopping mitigates loop filter’s 1/f noise
 LC filter in the loop  distortion suppressed
Design Challenges for Digital Input
 Potential distortion due to mismatch, ISI, and IMD
Outline
Class-D Amplifier
 Conclusion
Overview
 Capacitively coupled front-end

 Error signal (VERR = VOUT − DINVREF) amplified by 8x
 Loop filter noise attenuated by 18dB
Chopping-Induced Intermodulation
 fCHOP = fS/2 (384kHz) avoids quantization noise folding

[H. Chandrakumar, JSSC’18]
CCCA Swing
 fS = 768kHz limits swing

due to DAC image
Deadband (DB)
 20ns DB blocks chopping glitches

 Gives DAC reference time to settle
Loop Dynamics
 Feedback around LC filter (88kHz nominal) [H. Zhang, VLSI’21]
 Loop bandwidth ~500kHz  ~50dB nonlinearity suppression

Loop Filter Output Swing
 ~500kHz loop vs. 88kHz LC  large overshoot

Loop Filter Output Swing
 8-bit DAC limits signal range loss under 0.5dB

Dynamic Element Matching
 256 control lines needed to DEM 8-bit unary DAC
Noise-Shaped Segmentation
[R. Adams, ISSCC’98]
 DSM reduces bit width, shapes gain error

 Q-noise recovered by LSB DAC
 Over-range needed to accommodate Q-noise swing
Noise-Shaped Segmentation
[J. Steensgaard, PhD Thesis’99]
 2nd order less prone to idle tones than 1st order

 2-bit over-range needed
Real-Time (RT) DEM
[E. van Tuijl, ISSCC’04]
*Illustrated for a 3-bit DAC
 Mismatch averaged within each sample period (TS)

 No idle tone issue
Real-Time (RT) DEM
[E. van Tuijl, ISSCC’04]
 Signal-dependent # transitions between samples

 Distortion due to ISI
DAC Spectrum Without Deadband
 1% ISI on rising edges

Real-Time (RT) DEM
 Deadband blocks signal-dependent transitions

along with chopping glitches
DAC Transition With Deadband
 1% ISI on rising edges

Outline
Class-D Amplifier
 Conclusion
Digital-Input Processing
Digital-Input Processing
Front-End CCCA
 12fF CU using custom MOM caps

 ~0.005% 1-σ mismatch*
*Estimated based on PDK data of pcell MOM caps
Amplifying Error Signal
High-Voltage Feedback
[H. Zhang, JSSC’22]

 Chopper clock level shifted to feedback HV output
Timing Alignment
[H. Zhang, JSSC’22]

 Replica employed to remove skew on ΦDAC
Top-Level Schematic
 So far: DAC + capacitively coupled front-end

Top-Level Schematic
 3-stage loop filter + PWM output stage [H. Zhang, VLSI’21]

[H. Zhang, VLSI’20]
Outline
Class-D Amplifier
 Conclusion
Prototype
 180 nm BCD
 7.5 mm2
 14.4V PVDD
 1.8V AVDD/DVDD
 1.8V DAC VREF
 10μF ext. decap
 Interpolation
filter & DSMs
on FPGA
Output Spectrum
Output Spectrum
 DR = 120.9 dB
Output Spectrum
 ~−80dBc spurs present with 1st-order segmentation

THD+N vs. Output Power
 Peak THD+N = -112.1 dB

THD+N vs. Output Power
 Peak THD+N = -112.1 dB

THD+N vs. Frequency
Power Efficiency
90%
86%
Performance Summary & Comparison
E. Cope D. Schinkel J.-M. Liu T. Ido ADI
This Work
ISSCC 2018 JSSC 2017 JSSC 2014 ISSCC 2006 SSM3582A
Area (mm2) 7.5 4.3 - - 23(1) -
Architecture Closed-Loop Closed-Loop Closed-Loop Open-Loop Closed-Loop Closed-Loop
DAC Type CDAC RDAC IDAC - IDAC -
Supply (V) 14.4 8~20 25 18 35 4.5~16.5
IQ,PVDD (mA) 13.9 20.5 - 9.4 - 12.3
RLOAD (Ω) 8/4 8/4 4 8 4/6/8 8/4
POUT,MAX (W) 13/23 20 80 13 130/99/74(1) 18/32
Efficiency η 90%/86% 90% >90% 88% 81%(1) 94%/91%
THD+N @ 1kHz -111.2/-106.6 -97.2(2)/-93.1(2) -88.6 -62.5 -94.9 -94(2)
DR (dB) 120.9 115.5 115 84 113 109
A-wt. Output Noise (μVRMS) 9.3 20 34 - - 36
PSRR (dB) in 20~20kHz 97~78 80~50 88~60 - - 88 (1kHz)
(1) Output stage is off-chip (2) Extracted from figure
This Work
Area (mm2) 7.5 4.3 - - 23(1) -
Supply (V) 14.4 8~20 25 18 35 4.5~16.5
IQ,PVDD (mA) 13.9 20.5 - 9.4 - 12.3
RLOAD (Ω) 8/4 8/4 4 8 4/6/8 8/4
POUT,MAX (W) 13/23 20 80 13 130/99/74(1) 18/32
Efficiency η 90%/86% 90% >90% 88% 81%(1) 94%/91%
THD+N @ 1kHz -111.2/-106.6 -97.2(2)/-93.1(2) -88.6 -62.5 -94.9 -94(2)
DR (dB) 120.9 115.5 115 84 113 109
PSRR (dB) in 20~20kHz 97~78 80~50 88~60 - - 88 (1kHz)
This Work
Area (mm2) 7.5 4.3 - - 23(1) -
Supply (V) 14.4 8~20 25 18 35 4.5~16.5
IQ,PVDD (mA) 13.9 20.5 - 9.4 - 12.3
RLOAD (Ω) 8/4 8/4 4 8 4/6/8 8/4
POUT,MAX (W) 13/23 20 80 13 130/99/74(1) 18/32
Efficiency η 90%/86% 90% >90% 88% 81%(1) 94%/91%
THD+N @ 1kHz -111.2/-106.6 -97.2(2)/-93.1(2) -88.6 -62.5 -94.9 -94(2)
DR (dB) 120.9 115.5 115 84 113 109
PSRR (dB) in 20~20kHz 97~78 80~50 88~60 - - 88 (1kHz)
Comparison with State-of-the-Art
Conclusion
 First digital-input capacitively coupled chopper CDA
 2x lower integrated noise, 5.4 dB higher DR,
14 dB better THD+N compared to state-of-the-art
 Capacitive coupling & chopping reduces noise
 Deadband mitigates DAC ISI and chopping glitches
 RTDEM with NS segmentation tackles DAC mismatch
Conclusion
 First digital-input capacitively coupled chopper CDA
 2x lower integrated noise, 5.4 dB higher DR,
14 dB better THD+N compared to state-of-the-art
 Capacitive coupling & chopping reduces noise
 Deadband mitigates DAC ISI and chopping glitches
 RTDEM with NS segmentation tackles DAC mismatch
Thank you for your attention!

A Chopper-Stabilized Amplifier with a
Relaxed Fill-in and 22.6pA Input
Current
Thije Rooijers1,2, Johan H. Huijsing1, Kofi A. A. Makinwa1
1DelftUniversity of Technology, Delft, The Netherlands

2now at Broadcom, Bunnik, The Netherlands
© 2023 IEEE 3.2: A Chopper-Stabilized Amplifier with a Relaxed Fill-in and 22.6pA Input Current
Chopper-induced IMD
I1
Input signal (Fin=80kHz)
Tdelay
Vin
CH
Chopping signal (FCH=20kHz)
CH
2GmVin
Iout
Chopper-induced IMD
Intermodulation Output spectrum:

between Fin and FCH Fin
Input signal (Fin=80kHz) FIMD=4FCH-Fin
Amplitude
Vin
Chopping signal (FCH=20kHz) FCH Frequency
• Fin @ even multiples of FCH

CH
→ IMD tones in-band

• Difficult to filter
Prior art: Spread-Spectrum Chopping
Intermodulation Output spectrum:

between Fin and FCH Fin
Input signal (Fin=80kHz)
Amplitude
FIMD=4FCH-Fin
Noise
Vin
floor
Spread-spectrum chopping FCH Frequency
• IMD tone → noise signal

CH
• Does not solve the

underlying problem
[A.Tang – ISCAS 2001]
Prior art: Fill-in
CH1
Quadrature
CH2
Iout1
Iout2
[T.Rooijers – ISSCC 2021]

Prior art: Fill-in
CH1
CH2
Iout1
Iout2
Pass
Low IMD
Iint

Prior art: Fill-in
CH1
CH2
Iout1 50% Duty-cycle

→ Low Vos1&2
Combined with AZ:

Iout2 • Noise “bump”
• High switching
activity (600pA)
Pass
Iint

This work: Relaxed Fill-in
CH1
Iout1
0.04% Duty-cycle
→ Only low Vos1
• No chopping Gm2
Iout2 • RRL
Pass
Iint
Chopper-stabilized amplifier
Chopper-stabilized amplifier
Ripple-reduction loop
Fin
RRL: 2nd IMD Source
Fin
Fin
RRL: 2nd IMD Source

• Gm1/GmRRL ratio (600×)
Fin
Ripple-reduction loop AZ INT out
Fin
RRL: 2nd IMD Source

Fin
Ripple-reduction loop AZ INT out
Fin
RRL: 2nd IMD Source

• S&H
Fin
Fin
RRL: 2nd IMD Source

• S&H
• Cs=0.5pF & Ch=7.2pF
Fin
Powerdown
Powerdown:
• Gm2 Ibias reduced by 11×
• LPF
• Isolation
20% duty-cyle
→ 76% power saving
Die micrograph
0.18µm CMOS BCD

process
0.54mm2 active area
Measured: Amplitude spectrum
Single-tone test (Fin=79kHz, 1Vrms):
Without Fill-in With Fill-in
IMD: IMD:
-102dB @ 1kHz -125.7dB @ 1kHz
FCH=20kHz
24dB Reduction
10 Averages
Measured: Amplitude spectrum
Two-tone test (Fin=79kHz & Fin=80kHz, both 0.5Vrms):
Un-chopped CH Without Fill-in CH With Fill-in
IMD: IMD: IMD:

-112.4dB @ 1kHz -106.9dB @ 1kHz -112.4dB @ 1kHz
Limited by linearity Limited by linearity & Limited by linearity

Chopper-induced IMD
Measured: Voltage noise density
AZ noise “bump”
Relaxed fill-in
Until 10Hz: 12 nV/√Hz
No 1/f penalty
Measured: Offset and Input current
Offset
≤ 0.8μV
No relaxed
fill-in penalty
ESD only
Input current Sample with high positive IDC
≤ 4pA Sample with typical IDC
Sample with high negative IDC
Vin = 2.5V
15 Samples
FCH = 20kHz
Comparison table
This work [1] Rooijers 2021 [2] AD8551 [3] AD8571 [4] Ivanov [5] Rooijers 2019
DOC
Chopping + RRL Chopping + AZ AZ AZ Chopping + RRL AZ + Chopping
technique(s)
DOC frequency
20 20 4 2 to 4 50 to 150 15
(kHz)
fin=79kHz fin=79kHz fin=0.5kHz fin=0.5kHz fin=1kHz fin=16kHz
IMD tone (dB) -102 (No Fill-in) -97.7 (No Fill-in) -80 (Single) - -103 (Single) -44 (Single)
-125.7 (Fill-in) -125.9 (Fill-in) - -90 (Spread) -122.7 (Spread) -
Offset (Max) 0.8µV 0.8µV 5µV 5µV 3.5µV 0.6µV
Input current
22.6pA 600pA 50pA 50pA 200pA 0.2pA
(Max)
Voltage Noise
12 16 42 51 6.5 20
Density (nV/√Hz)
Supply current 0.62 (Duty off)
0.55 0.85 0.85 1.65 0.21
(mA) 0.53 (Duty on)
Die Area (mm2) 1.25 1.25 - - 1.626 1.4
Comparison table
DOC
technique(s)
DOC frequency
20 20 4 2 to 4 50 to 150 15
(kHz)
Input current
22.6pA 600pA 50pA 50pA 200pA 0.2pA
(Max)
Voltage Noise
12 16 42 51 6.5 20
Density (nV/√Hz)
0.55 0.85 0.85 1.65 0.21
(mA) 0.53 (Duty on)
Die Area (mm2) 1.25 1.25 - - 1.626 1.4
Comparison table
DOC
technique(s)
DOC frequency
20 20 4 2 to 4 50 to 150 15
(kHz)
Input current
22.6pA 600pA 50pA 50pA 200pA 0.2pA
(Max)
Voltage Noise
12 16 42 51 6.5 20
Density (nV/√Hz)
0.55 0.85 0.85 1.65 0.21
(mA) 0.53 (Duty on)
Die Area (mm2) 1.25 1.25 - - 1.626 1.4
Conclusions
Relaxed fill-in technique:
Simple implementation
• Similar IMD (-125.7dB with fin=79kHz)

• 25× lower input current (22.6pA)
• Flat lower noise floor (12nV/√Hz), same power

Bandpass Filter and Oscillator ICs with
THD < -140dBc at
10Vppd for Testing High-Resolution ADCs
Subha Sarkar 1,2, Rajat Agarwal 1, Nagendra Krishnapura 2
1 Texas Instruments, Bangalore, India

2 Indian Institute of Technology, Madras, India
© 2023 IEEE
International Solid-State Circuits Conference 3.3 : Bandpass Filter and Oscillator ICs with THD < -140dBc at 10Vppd for Testing High-Resolution ADCs 1 of 27
Outline
 Problem statement
 Low-distortion band-pass filter
 Low-distortion oscillator
 Distortion mitigation techniques
 Capacitor nonlinearity cancellation
 Regulated cascode output stage for the opamps
 ESD diode nonlinearity
 Results
© 2023 IEEE
Problem statement
 IC solution to test linearity of > 18 bit ADCs
 THD < -140 dBc (1kHz/10kHz) for 10Vppd output at 5.6V supply
 Small form factor and test scalability
 Two approaches:
 DAC to generate a sinusoid (THD ~ -80dBc)
+ active band-pass filter(HD2 attenuation ~ 60dB)
 Sinusoidal oscillator(band-pass filter in a positive feedback loop)
© 2023 IEEE
Prior art: Filter [TCAS-I 2018]
 8th order active-RC BPF
 4 stages, each with Q=4
 Two-stage opamp
 Buffer after the first stage to
reduce nonlinear current of
the parasitic cap of second
stage
 THD ~ -115/-118 dBc at
1/10 kHz for 10Vppd
output
© 2023 IEEE
Prior art: Oscillator [TCAS-I 2018]
 BPF in a loop
with amplitude
stabilization
 THD ~ -115/-121
dBc at 1/10 kHz
for 8Vppd output
© 2023 IEEE
Achieving -140dBc: Suppress residual distortion
 Capacitor nonlinearity
 Not suppressed by loop gain
 Cancelled by injecting opposite nonlinear current
 Opamp output conductance nonlinearity
 Suppressed using local negative feedback (Regulated cascode)
 ESD diode nonlinearity
 Four-wire connection
© 2023 IEEE
Proposed solution – Approach 1
6th Order(3-stage) BPF
Cancel capacitor nonlinearity
Limit VDS swing (Regulated cascode)
© 2023 IEEE
Proposed Solution – Approach 2
Oscillator (BPF + Amplitude stabilization)
© 2023 IEEE
BPF Distortion
Capacitor nonlinear current –

parallel current source
© 2023 IEEE
Extracting nonlinear current
- V +
- V +
- V +
1 2
Identical linear part; Scaled nonlinear part

© 2023 IEEE
Extracting nonlinear current
1
Linear part cancelled; Nonlinear part remains

Smaller ac ⇒ Smaller area; More excess noise
© 2023 IEEE
More practical circuit : + Cstb, Rg, Rp, Rs
© 2023 IEEE
Isyn=inl2+inlC1; Nonlinearity cancelled
© 2023 IEEE
Complete improved single stage BPF
Bandpass Filter Non-linearity extraction circuit
© 2023 IEEE
Opamp Architecture
© 2023 IEEE
Output conductance nonlinearity mitigation
Conventional Regulated cascode
 Small swing at node vy ⇒ negligible iNL2

 Distortion iNL4 is suppressed by factor of Argm4(1)/gds2(1)
© 2023 IEEE
ESD diode nonlinearity
 Four-wire connection suppresses the effect of Rparasitic.

 Both HD2 and HD3 nonlinearity due to ESD diode reduced
© 2023 IEEE
Prototype IC
 Sixth-order band-pass filter
 Sinusoidal oscillator
 Switchable to 1kHz/10kHz
+ Test chips
 Amplifier: conventional and
regulated-cascode output
 2nd order filter: With and w/o
nonlinearity cancellation
© 2023 IEEE
Amplifier test chip
© 2023 IEEE
Amplifier test chip: Measured results
20dB better
At 10 kHz 5 Vpp single-ended amplitude
© 2023 IEEE
Second-order BPF test chip: Measured results
© 2023 IEEE
Sixth-order BPF: Measured magnitude response
© 2023 IEEE
Measured THD – 1kHz and 10kHz
THD < -140 dBc

© 2023 IEEE
BPF performance summary
© 2023 IEEE
Oscillator performance summary
THD = -133.8 dB at 1kHz,

-111.1 dB at 10kHz
© 2023 IEEE
Conclusion
 Two techniques to suppress distortion to < -140dB
 Capacitor HD3 cancellation technique
 Regulated cascode output stage for the opamp
 Low-distortion sinusoid generation demonstrated

 Band-pass filter with -142dBc THD
 Oscillator with -133dBc THD
© 2023 IEEE
References
[1] S. Kumar et al., “Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing
High-Resolution ADCs,” IEEE TCAS-I, vol. 66, no. 9, pp. 3393-3401, Sept. 2019.
[2] E. Sackinger and W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit,”
IEEE JSSC, vol. 25, no. 1, pp. 289-298, Feb. 1990.
[3] A. M. Durham et al., “High-Linearity Continuous-Time Filter in 5-V VLSI CMOS,” IEEE JSSC,
vol. 27, no. 9, pp. 1270-1276, Sept. 1992.
[4] Un-Ku Moon and Bang-Sup Song, “Design of a Low-Distortion 22-kHz Fifth-Order Bessel
Filter,” IEEE JSSC, vol. 28, no. 12, pp. 1254-1264, Dec. 1993.
[5] S. Wen et al., “A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio
Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes,” ISSCC,
pp. 294-295, Feb. 2019.
[6] Wen, S.H. et al., “A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-
Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation
Effect of Poly Resistors,” ISSCC, Vol. 65, pp. 482-483, Feb. 2022.
© 2023 IEEE
A 0.01mm2 10MHz RC Frequency Reference with
a 1-Point On-Chip-Trimmed Inaccuracy of ±0.28%
from −45°C to 125°C in 0.18μm CMOS
Xiaomeng An, Sining Pan, Hui Jiang, and Kofi A. A. Makinwa

Electronic Instrumentation Laboratory
Delft University of Technology
Delft, The Netherlands
© 2023 IEEE
International Solid-State Circuits Conference 3.4: A 0.01mm2 10MHz RC Frequency Reference with a 1-Point On-Chip-Trimmed Inaccuracy of ±0.28% from −45°C to 125°C in 0.18μm CMOS 1 of 30
Motivation
 IoT applications need
low cost frequency references
 Quartz/MEMS resonators
are very accurate, but bulky
 RC frequency references are low

cost and can be accurately trimmed
 But are they stable? Internet of Things (SAP)
© 2023 IEEE
Design Goals
5
10
Lee,
■ Moderate JSSC'20
Cao,
inaccuracy ISSCC'13
Lee,
4
■ Low cost
Tokunaga, ISSCC'15
10
JSSC'10
⇒ Low area
Inaccuracy (ppm)
⇒ 1-point trim Khashaba,
JSSC'22
Ji,
■ Facilitate stability
3
10
Our Goal ISSCC'22
measurements Jiang,
ISSCC'21
Gürleyük,
JSSC'22
Choi,
JSSC'21
2
10
-2 -1
10 10
2
Chip Area (mm )
© 2023 IEEE
Conventional RC Oscillator
Comparator
delay
■ Compact architecture
■ But comparator delay limits accuracy
© 2023 IEEE
Frequency-Locked Loop
[A. Abidi, JSSC ‘89]

[A. Khashaba, JSSC ’22]
■ Feedback loop locks the frequency FOUT of a VCO to R0C0

■ Now accuracy is not limited by circuit delay
© 2023 IEEE
Proposed Architecture
Reset Phase ΦRST
■ Reset VC to VDD
t/TVCRO
© 2023 IEEE
Discharge Phase ΦDCHG
■ C0 is discharged via R0
t/TVCRO
© 2023 IEEE
Integration Phase ΦINT
■ Sample and hold VC

■ Integrate VR - VC
t/TVCRO
© 2023 IEEE
Frequency-Locked Loop
t/TVCRO
■ Steady-state ⇒ FOUT only depends on R0C0 and R1/R2

■ Challenges: Temp compensation (R0) & Freq trimming (R0C0) ??
© 2023 IEEE
Temperature Compensation
■ Conventional: Combine two resistors with complementary TCs

● Not possible in all CMOS processes 
● Adds (code-dependent) parasitic caps to R0 
© 2023 IEEE
Proposed Temperature Compensation
VR
■ Trim TC of VR
 Accurate: no parasitic caps added to R0
 Versatile: resistor TCs may all have the same polarity
© 2023 IEEE
Nominal Frequency Trim
■ Compact ⇒ 6-bit Coarse + 6-bit Fine Trim

 ±30% trimming range & 0.1% trimming resolution
 Compact: MIM capacitors above circuitry
© 2023 IEEE
■ 40MHz voltage-controlled ring oscillator (VCRO)

■ Timing logic generates 10MHz FOUT and 3 control phases
© 2023 IEEE
Integrator & Notch Filter
■ Chopping suppresses
integrator offset and 1/f noise
■ But chopper ripple ⇒ large CINT
■ Notch filter ⇒ much smaller CINT
[P. Park, JSSC ’15]
© 2023 IEEE
Integrator & Notch Filter Design
■ Compact
⇒ Telescopic amplifier w/
simple biasing scheme
⇒ 12.5pF total filter cap
MVT
devices
© 2023 IEEE
Voltage-Controlled Oscillator
■ Corner spread
⇒ 3-level trim DAC
■ Compact
⇒ 3-inverter ring oscillator
⇒ self-cascoded Gm stage
© 2023 IEEE
Fabricated Prototype 0.18μm CMOS:
● Active area: 0.01mm2
● 16 FLLs per chip
⇒ good statistics
● Packaged in
ceramic and plastic
● 85μW @ 1.5V supply
Power Breakdown @1.5V
Driver
Power
100µm
Analog
Power (19.2µA)
(27.5µA)
Digital
Power
(10µA)
© 2023 IEEE 100µm

Measured Start-up Time
■ Start-up time = 30µs
after resetting VCTRL to ground
■ Notch filter has negligible
effect on start-up time
© 2023 IEEE
Period Jitter
■ Notch filter effectively
reduces chopper ripple
■ Residual jitter is VCO dominated
© 2023 IEEE
Allan Deviation
w/o and w/ chopping
w/o chopping: 10.5ppm
w/ chopping: 2.3ppm
© 2023 IEEE
Measured Residual Frequency Error
Ceramic-packaged 112 samples
Fixed TC trim + 1p Freq trim
⇒ ±0.28% (-45°C to 125°C)
⇒ 31.5ppm/°C (box method)
⇒ 1500ppm hysteresis !!
© 2023 IEEE
Measured Aging Frequency Error
Averaged value of 112 samples
Baked at 150°C for one week

⇒ 10ppm/°C TC error
⇒ 5000ppm frequency drift !!!!
© 2023 IEEE
Measured Residual Frequency Error
Plastic-packaged 112 samples
10.05
10.04
Averaged value
Fixed TC trim + 1p Freq trim
10.03
⇒ ±0.3% (-45°C to 125°C)
10.02 ⇒ 35.3ppm/°C (box method)
10.01 ⇒ 1200ppm hysteresis
Frequency (MHz)
10
9.99
TC=35.3ppm/ ° C
9.98
9.97
Cooling Heating
9.96
-40 -20 0 20 40 60 80 100 120
° C)
Temperature (
© 2023 IEEE
Measured Aging Frequency Error
Averaged value of plastic-packaged 112 samples
Baked at 150℃ for one week
⇒ 7ppm/°C TC error
⇒ 2000ppm frequency drift !!
© 2023 IEEE
What’s Going On?
Ceramic package Plastic package
50 50
40
One coarse trim step Sample Number= 112
Mean= 1509 40
Sample Number= 112
Mean= 1541
Std Dev= 64.2057 Std Dev= 109.1759
30 30
Count
Count
20 20
10 10
0 0
1300 1400 1500 1600 1700 1300 1400 1500 1600 1700
Trim Code Trim Code
Hypothesis: plastic packaging ⇒

■ More packaging stress ⇒ more resistor spread
■ Chips are effectively pre-aged @ ~180°C ⇒ lower drift
© 2023 IEEE
Summary
© 2023 IEEE aIncluding driver b Estimated3.4:from

International Solid-State Circuits Conference
inaccuracy plots c Box method d LDO used
A 0.01mm2 10MHz RC Frequency Reference with a 1-Point On-Chip-Trimmed Inaccuracy of ±0.28% from −45°C to 125°C in 0.18μm CMOS 26 of 30
Summary
© 2023 IEEE
a Including driver b Estimated from inaccuracy plots c Box method d LDO used
Benchmarking
5
10
Lee,
JSSC'20
Cao,
ISSCC'13
Lee,
4 Tokunaga,
10 ISSCC'15
JSSC'10
Inaccuracy (ppm)
This Work Khashaba,
JSSC'22
Ji,
3
10
ISSCC'22
Jiang, Gürleyük,
ISSCC'21 JSSC'22
Choi,
JSSC'21
2
10
-2 -1
10 10
2
Chip Area (mm )
© 2023 IEEE
Conclusions
■ 10MHz RC frequency reference with
 Low area (0.01mm2)
 Moderate accuracy with 1-point trim
(±0.28% from -45°C to 125°C)
 Versatile temp compensation scheme
(works in all CMOS processes)
■ BUT poly resistor hysteresis and drift limits long-term accuracy

⇒ explore other resistors: metal, silicided, diffusion …
© 2023 IEEE
Conclusions
■ 10MHz RC frequency reference with
 Low area (0.01mm2)
 Moderate accuracy with 1-point trim
(±0.28% from -45°C to 125°C)
 Versatile temp compensation scheme
(works in all CMOS processes)
■ BUT poly resistor hysteresis and drift limits long-term accuracy

⇒ explore other resistors: metal, silicided, diffusion …

© 2023 IEEE
A 1.4μW/MHz 100MHz RC oscillator with
±1030ppm inaccuracy from -40°C to 85°C
after accelerated aging for 500 hours at 125°C
Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia,
Tianyu Wang, Ahmed Abdelrahman, and Pavan Kumar Hanumolu
University of Illinois at Urbana-Champaign
© 2023 IEEE
International Solid-State Circuits Conference 3.5: A 1.4μW/MHz 100MHz RC oscillator with ±1030ppm inaccuracy from -40ºC to 85ºC after accelerated aging for 500 hours at 125ºC 1 of 62
Outline
• Motivation
• Proposed architecture
• Implementation details
• Measurement results
• Summary
© 2023 IEEE
Frequency stability requirements1/4
Microcontroller module BLE module
Source of Microcontroller: https://www.st.com/en/microcontrollers-microprocessors/stm32f103c8.html

Source of BLE: https://www.digikey.com/catalog/en/partgroup/bluetooth-v4-0-hm-11-ble-module/60471
© 2023 IEEE
XO
•μ-controllers: ±1%
•RTC: ±250ppm1
•BLE radios: ±40ppm1
*XO: crystal oscillator

© 2023 IEEE
XO XO
•BLE RTC: ±500ppm1
•BLE radios: ±40ppm1
[1] Bluetooth core specification version 5.2 *RTC: real-time clock

© 2023 IEEE
XO XO
•BLE RTC: ±500ppm1
XO
•BLE RF: ±40ppm1
[1] Bluetooth core specification version 5.2

© 2023 IEEE
Crystal oscillators
XO XO  Accurate frequency
 Bulky
 High cost
XO
Microcontroller module BLE module  Physical clock attack
© 2023 IEEE
On-chip RC oscillators1/3
 Low power consumption (nW ~ μW)

 Small area
 Fully integrated on-chip
 Poor short- and long-term stability
© 2023 IEEE

 Small area
 Temperature fluctuation and aging
© 2023 IEEE

 Small area
 Temperature fluctuation and aging
Prior art’s focus: improve short-term stability

© 2023 IEEE
Temperature stability vs year1/3
© 2023 IEEE
© 2023 IEEE
Can we guarantee this performance over TCOs’ lifetime?
© 2023 IEEE
RC oscillator aging with P-poly resistor
ΔF =a∙ln(b∙Time+c)
F
−5200ppm after 1000hours
© 2023 IEEE
Proposed aging-compensated RC oscillator1/6
Main TCO Reference TCO
Large Ea resistors
FOUT Aging FREF
Calibration AC current stress
Logic Low duty cycle
•Compensate using less-aged reference TCO
*TCO: temperature-compensated oscillator

© 2023 IEEE
Large Ea resistors
FOUT Aging FREF
© 2023 IEEE
*Ea: activation energy
Large Ea resistors
FOUT Aging FREF
Ea
Time to fail (TTF) ∝ e kT
Use of higher Ea resistors can improve TCO’s lifetime
J. Gambino, “BEOL reliability for more-than-Moore devices,” IPFA 2018

© 2023 IEEE
*Ea: activation energy
Large Ea resistors
FOUT Aging FREF
Ea
Time to fail (TTF) ∝ e kT
Use of higher Ea resistors can improve TCO’s lifetime

e.g. Ea of N-poly/metal resistor > Ea of P-poly resistor
J. Gambino, “BEOL reliability for more-than-Moore devices,” IPFA 2018
© 2023 IEEE
Large Ea resistors
FOUT Aging FREF
Temperature-
Compensated RC
R0 VRC VC CKOUT
I C0
R1 VREF
I C1 SEL
÷N
E. I. Cole et al., “OBIC analysis of stressed, thermally-isolated polysilicon resistors,” RELPHY 1995
© 2023 IEEE
Large Ea resistors
FOUT Aging FREF
Ref. TCO power
0.1% on-time duty cycle
Time
C. Kendrick et al., “Polysilicon resistor stability under voltage stress for safe-operating area characterization,” IRPS 2018
© 2023 IEEE
Outline
• Motivation
• Summary
© 2023 IEEE
Proposed TCO1/16
RC1_SIGN DECHOP
SEL ΦCHG CINT
R0 Path0 VCRO
C0 0 VRC
VC Main TCO Reference TCO
ΦBUF ΦRST −GM
1 VREF
α0VDD CKOUT
0 SEL
VDAC0 (1-α0)VDD ÷25 FOUT Aging FREF
1 SEL=β CKPHG Calibration
R1 Path1 ΦINT
ΦCHG Logic
C1 ΔΣSEL Phase
ΦBUF ΦRST ΦRST
17 Gen
α1VDD ΦBUF
VDAC1 (1-α1)VDD
0
DSEL
1
© 2023 IEEE
Proposed TCO2/16
RC1_SIGN DECHOP
SEL ΦCHG CINT
R0 Path0 VCRO
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD CKOUT
0 SEL
VDAC0 (1-α0)VDD ÷25
1 SEL=β CKPHG
R1 Path1 ΦINT
ΦCHG Phase
C1 ΔΣSEL
ΦBUF ΦRST ΦRST
17 Gen
α1VDD ΦBUF
VDAC1 (1-α1)VDD
0
DSEL
1
*VCRO: voltage-controlled ring oscillator

*VDAC: voltage digital-to-analog converter
© 2023 IEEE
Proposed TCO3/16
RC1_SIGN DECHOP
SEL ΦCHG CINT
R0 Path0 VCRO
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD CKOUT
0 SEL
1 SEL=β CKPHG
R1 Path1 ΦINT
ΦCHG Phase
C1 ΔΣSEL
ΦBUF ΦRST ΦRST
17 Gen
α1VDD ΦBUF
VDAC1 (1-α1)VDD
0
DSEL
1
© 2023 IEEE
Proposed TCO4/16
1 234
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD VSS
1
ΦCHG=0
• 1st phase: C0 is reset to VDD
© 2023 IEEE
Proposed TCO5/16
1 23 4
RC1_SIGN
SEL
DECHOP ΦCHG  − TP 
ΦCHG CINT
R0 ΦRST 
R C

C0
Path0
0 VRC
VC
VCRO
ΦBUF
BUF
VRC = VDD e  0 0
ΦBUF ΦRST −GM
CKOUT ΦINT VREF = VDDα 0

1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD ÷25 SEL
1 SEL=β
ΦINT
CKPHG TP TP = 25 / FOUT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF
α1VDD ΦBUF
0
DSEL
1
ΦCHG=0
• 2nd phase: C0 discharges for TP duration
© 2023 IEEE
Proposed TCO6/16
1 234
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF
α1VDD ΦBUF
0
DSEL
1
ΦCHG=0
• 3rd phase: redistribution of charge in R0’s parasitic capacitor
© 2023 IEEE
Proposed TCO7/16
1 234
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF
α1VDD ΦBUF
0
DSEL
1
ΦCHG=0
• 4th phase: integration of voltage difference between VRC and VREF
© 2023 IEEE
Proposed TCO8/16
1
RC1_SIGN
SEL
DECHOP ΦCHG
CHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
RST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
1
ΦCHG=1
• ΦCHG=01 and C0 is reset to VSS
© 2023 IEEE
Proposed TCO9/16
1 2
RC1_SIGN DECHOP ΦCHG  
 − TP 
SEL ΦCHG CINT 
R0 Path0 VCRO ΦRST =
R C
VRC VDD  1 − e  0 0  
VRC  
C0 0
VC ΦBUF
BUF
ΦBUF ΦRST −GM
 
CKOUT ΦINT
1 VREF
α0VDD 0 SEL VREF VDD (1 − α 0 )
=
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
1
ΦCHG=1 TP
• C0 charges for TP duration
© 2023 IEEE
Proposed TCO10/16
1 234
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
1
ΦCHG=1
• Integration of voltage difference between VRC and VREF
© 2023 IEEE
Proposed TCO11/16
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD
1
VSS
• AC current reduces stress on R0

© 2023 IEEE
Proposed TCO12/16
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD
1
VSS
• Duty cycle of current in R0 is 20%, slowing down aging rate

© 2023 IEEE
Proposed TCO13/16
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α0VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α0)VDD
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD
1
VSS
25
F=
OUT F=
OUT0
R 0 C0 ln(1/ α 0 )
© 2023 IEEE
Proposed TCO14/16
RC1_SIGN DECHOP
SEL ΦCHG CINT
R0 Path0 VCRO
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD CKOUT
0 SEL
1 SEL=β CKPHG
R1 Path1 ΦINT
ΦCHG Phase
C1 ΔΣSEL
ΦBUF ΦRST ΦRST
17 Gen
α1VDD ΦBUF
VDAC1 (1-α1)VDD
0
DSEL
1
• R1C1 with different TC is added to compensate for TC of R0C0

© 2023 IEEE
Proposed TCO15/16
1 234 1 234
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD α1VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF (1-α1)VDD
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD
1
VSS
25
F=
OUT F=
OUT1
R 1C1 ln(1/ α1 )
© 2023 IEEE
Proposed TCO16/16
RC1_SIGN
SEL
DECHOP ΦCHG
ΦCHG CINT
R0 Path0 VCRO ΦRST
VRC
C0
ΦRST
0
−GM
VC ΦBUF
BUF
ΦBUF
CKOUT ΦINT
1 VREF
α0VDD 0 SEL
VDAC0 (1-α0)VDD
1 SEL=β
÷25 SEL
CKPHG
ΦINT
R1 Path1
ΦCHG
VDD
C1 ΔΣSEL Phase
ΦBUF ΦRST
17 ΦRST Gen VVRC
RC
VREF
α1VDD ΦBUF
0
DSEL
VDAC1 (1-α1)VDD
1
VSS
FOUT =
(1 − β )FOUT 0 + βFOUT1
β = average of SEL sequence
© 2023 IEEE
Two-point trimming1/2
RC1_SIGN DECHOP
SEL
R0
ΦCHG
Path0
CINT
VCRO
FOUT =
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD 0 SEL
CKOUT FOUT
VDAC0 (1-α0)VDD
1 SEL=β
÷25 FTAR
CKPHG
R1 Path1 ΦINT
ΦCHG
ΦBUF
C1
ΦRST
ΔΣSEL Phase T1 T2
17 ΦRST Gen
α1VDD ΦBUF @ T2 = 85°C
0
DSEL
VDAC1 (1-α1)VDD
1
▪ Set SEL=0 & Find α0 for FOUT=FOUT0=FTAR
▪ Set SEL=1 & Find α1 for FOUT=FOUT1=FTAR
© 2023 IEEE
Two-point trimming2/2
RC1_SIGN DECHOP
SEL
R0
ΦCHG
Path0
CINT
VCRO
FOUT =
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD 0 SEL
CKOUT FOUT
VDAC0 (1-α0)VDD
1 SEL=β
÷25 FTAR
CKPHG
R1 Path1 ΦINT
ΦCHG
ΦBUF
C1
ΦRST
ΔΣSEL Phase T1 T2
17 ΦRST Gen
α1VDD ΦBUF @ T1 = −40°C
0
DSEL
VDAC1 (1-α1)VDD
1
▪ If all RCs have positive TCs, set RC1_SIGN=1.
Otherwise, RC1_SIGN=0.
▪ Find β for FOUT=FTAR
© 2023 IEEE
Key building blocks
RC1_SIGN DECHOP
SEL ΦCHG CINT
R0 Path0 VCRO
0 VRC
C0 VC
ΦBUF ΦRST −GM
1 VREF
α0VDD CKOUT
0 SEL
VDAC0 (1-α0)VDD ÷25 FOUT Aging FREF
1 SEL=β CKPHG Calibration
R1 Path1 ΦINT
ΦCHG Logic
C1 ΔΣSEL Phase
ΦBUF ΦRST ΦRST
17 Gen
α1VDD ΦBUF
VDAC1 (1-α1)VDD
0
DSEL
1
© 2023 IEEE
Voltage ∆Σ-DAC
VDD
VSS 0 α0/1VDD
17 S0/1 1
ΔΣ
DREF0/1
0 (1-α0/1)VDD
1
CKVDAC
~10MHz
÷10 CKOUT ΦRST
• Rail-to-rail 1-bit sequence conversion for reliable voltage generation
• Unity-gain buffers prevents charge sharing between integrator and LPF
© 2023 IEEE
GM-C Integrator
VBP1
DECHOP
MP0 MP1 MP2 MP3
VBP2 RC VC
ΦINT
VRC VBN2 CINT
VREF
VBN1
• MP0~3 switches enable/disable integration

• Chopping/de-chopping suppresses integrator offset
© 2023 IEEE
On-chip aging calibration logic
Duty-cycled
reference TCO
CKPHG
÷216 Calibration Logic
~4MHz
err
Always-on 22
+
−
+ DLF
main TCO
CKOUT Frequency 22
Counter
17 DREF0 DCNT
*DLF: digital-loop filter

© 2023 IEEE
Outline
• Motivation
• Summary
© 2023 IEEE
Die photograph
Main TCO 250µm
• Fabricated in 65nm CMOS

Test RCs
• Packaged in a plastic QFN
VCO
Reference
485µm
• Active area: 0.22mm2 GM − C
Integrator
Digital TCO
• 12 test RC branches
VDAC0
• Temp. range: −40° to 85°C
VDAC1
• Power consumption: 142µW
© 2023 IEEE
Aging behavior of TCOs at 125°C1/2
TCO with N-poly resistor
© 2023 IEEE
Aging behavior of TCOs at 125°C2/2
TCO with N-poly resistor TCO with VIA resistor
© 2023 IEEE
AC stress and chopping
Without AC stress & chopping With AC stress & chopping
© 2023 IEEE
Aging test using N-poly and VIA resistors
FOUT Aging FREF

Calibration
Logic
Main TCO: R0→N-poly; R1→VIA

Ref. TCO: R0→N-poly; R1→VIA
© 2023 IEEE
Frequency inaccuracy without aging compensation1/2
Before aging After aging for 500hrs at 125°C

FERR=±760ppm FERR=±1500ppm
© 2023 IEEE
Frequency inaccuracy without aging compensation2/2

© 2023 IEEE
Frequency inaccuracy with aging compensation

© 2023 IEEE
Aging test using P-poly and VIA resistors
FOUT Aging FREF

Calibration
Logic
Main TCO: R0→P-poly; R1→VIA

Ref. TCO: R0→N-poly; R1→VIA
© 2023 IEEE
Frequency inaccuracy without aging compensation
© 2023 IEEE
Frequency inaccuracy with aging compensation
© 2023 IEEE
Output frequency supply stability
1440ppm/V for supply voltage 1.1V to 1.3V
© 2023 IEEE
With N-poly and VIA resistors
Period Jitter performance
Period jitter = 5.1psrms
5mV
50ps
© 2023 IEEE
Allan deviation
8.1ppm Allan deviation in 1s stride
40ppm
8.1ppm
© 2023 IEEE
Performance comparison1/2
Ji Gurleyuk Park Jiang Khashaba
This Work
ISSCC22 JSSC22 JSSC22 ISSCC21 ISSCC20
Process 65nm 180nm 180nm 65nm 180nm 65nm
Frequency [Hz] 100M 2.3M 16M 100M 16M 32M
Power Efficiency
1.4 3.3 13.8 1.0 10 1.1
[µW/MHz]
P-poly Resistor Used No Yes Yes
Aging Compensation Yes No
Frequency Inaccuracy
±760 ±760 ±1550 ±385 ±140 ±400 ±530
w/o Aging [ppm]
w/ Aging [ppm] ±1500/ ±4210/
-
Uncompensated/ ±1030 ±960
Compensated
# of Trim Points 2 2 2 3 1+Batch 2
Temp. Range [°C] -40 to 85 -40 to 125 -45 to 85 -40 to 95 -45 to 85 -40 to 85
Supply Sensitivity [%/V] 0.14 0.51 0.12 0.0083 0.2 0.008
Supply Range [V] 1.1 to 1.3 1.3 to 2.0 1.6 to 2.0 1.1 to 2.5 1.6 to 2.0 1.1 to 2.3
# of Samples 11 3 11 20 20 18 6
Period Jitter [psrms] 5.1 - 39.9 13.3 10.2 24
ADEV@τ=1s [ppm] 8.1 9 1 1.6 0.8 2.5
© 2023 IEEE
Area [mm2] 0.22 0.07 0.3 0.19 0.14 0.18
Performance comparison2/2
Ji Gurleyuk Park Jiang Khashaba
This Work
ISSCC22 JSSC22 JSSC22 ISSCC21 ISSCC20
Process 65nm 180nm 180nm 65nm 180nm 65nm
Frequency [Hz] 100M 2.3M 16M 100M 16M 32M
Power Efficiency
1.4 3.3 13.8 1.0 10 1.1
[µW/MHz]
P-poly Resistor Used No Yes Yes
Aging Compensation Yes No
±760 ±760 ±1550 ±385 ±140 ±400 ±530
w/o Aging [ppm]
w/ Aging [ppm] ±1500/ ±4210/
-
Uncompensated/ ±1030 ±960
Compensated
# of Trim Points 2 2 2 3 1+Batch 2
Temp. Range [°C] -40 to 85 -40 to 125 -45 to 85 -40 to 95 -45 to 85 -40 to 85
Supply Sensitivity [%/V] 0.14 0.51 0.12 0.0083 0.2 0.008
Supply Range [V] 1.1 to 1.3 1.3 to 2.0 1.6 to 2.0 1.1 to 2.5 1.6 to 2.0 1.1 to 2.3
# of Samples 11 3 11 20 20 18 6
Period Jitter [psrms] 5.1 - 39.9 13.3 10.2 24
ADEV@τ=1s [ppm] 8.1 9 1 1.6 0.8 2.5
© 2023 IEEE
Area [mm2] 0.22 0.07 0.3 0.19 0.14 0.18
Summary
FOUT Aging FREF

Calibration
Logic
 A power-efficient TCO with aging compensation

– Use of large Ea resistors (N-poly and VIA)
– AC stress on resistors
– Heavily duty-cycled reference TCO for aging compensation
– ±1030ppm inaccuracy with 1.4μW/MHz power efficiency
© 2023 IEEE
Thank you
 Acknowledgement
• This work was supported by Semiconductor Research Corporation
(SRC) under GRC Task 2810.036
• Thanks to Stefano Pietri, John Pigott, and Domenico Liberti at NXP
and Danielle Griffith at Texas Instruments for critical feedback
© 2023 IEEE
A 12/13.56MHz Crystal Oscillator with
Binary-Search-Assisted Two-Step
Injection Achieving 5.0nJ Startup Energy
and 45.8µs Startup Time
Haihua Li 1, Ka-Meng Lei 1, Pui-In Mak 1, Rui P. Martins 1,2
University of Macau, Macau, China1

Instituto Superior Técnico/UL, Portugal2
© 2023 IEEE 3.6 A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection
International Solid-State Circuits Conference Achieving 5.0nJ Startup Energy and 45.8µs Startup Time 1 of 49
Outline
 Motivation
 Proposed Architecture
 Measurement Result
 Comparison & Conclusion
Outline
 Motivation
Motivation
Crystal Oscillator (XO)

 Low phase noise
 Superior stability
☒ Long startup time
XO for Duty-cycled Operation
[Datasheet SLOA184]
 Startup time (ts): 2.74ms
 Startup energy (Es): 13.1μJ
XO for Duty-cycled Operation
 XO fast start-up technique → Significant energy and latency reduction!
XO Fast Startup: Frequency Injection
300
Δf = 1 − fIN J/fs
250 1000ppm 10000ppm
LM RM CM 500ppm 5000ppm
200 200ppm 2500ppm
iM,env (μA)
100ppm 1500ppm
VINJ iM 150 0ppm
100
50
0
0 5 10 15 20 25 30 35 40
Time (µs)
 An accurate fINJ matching fs is required
Two-step Injection Technique (1/2)
VREF,D
VREF
gm
VDCO PFD
DC
VDCO
DLF TDC
D-PLL
ISSCC' 19
ISSCC' 22
Megawer et al.
1 st Inj PLL lock 2 nd Inj Steady State Jung et al.
Calibrate DCO after 1st injection
Calibrate i-VCO after 1st injection
 Accurate calibration
☒ 325 cycles for calibration
☒ Phase alignment trimming
VREF,D
VREF
gm
VDCO PFD
DC
VDCO
DLF TDC
D-PLL
ISSCC' 19 ISSCC' 22
1 st Inj PLL lock 2 nd Inj Steady State Megawer et al. Jung et al.
☑ Accurate calibration
VREF,D
VREF
gm
VDCO PFD
DC
VDCO
DLF TDC
D-PLL
ISSCC' 19 ISSCC' 22
1 st Inj PLL lock 2 nd Inj Steady State Megawer et al. Jung et al.
☑ Accurate calibration
Accurate calibration
How can we shorten thecalibration time?
Outline
 Motivation
Binary-search-assisted TSI: Concept
 Δf < 10,000 ppm

 T1 = 4 μs
 Frequency locking
 T2 = 3.5 μs
 2nd injection
 T3 = 36 μs
 Steady state
 VXO ≈ 0.32Vpp
Outline
 Motivation
Binary-search-assisted TSI: Schematic
*SSG: Stepwise Signal Generator
Frequency Comparison
 Frequency Comparison: Extract and compare td1 and td2

 TDC resolution: <500ppm of fXO
Frequency Comparison
 Large td → TDC area↑ and power consumption ↑

 Solution: DCO resetter & Edge Aligner
Binary-search Frequency Locking
Binary-search Frequency Calibration
Jitter Analysis
Jitter Analysis
Jitter Analysis
 Error definition: Calibrated Δf >500ppm

 P6bit(Error) = 8.6% → P8bit(Error) =4.9%
DCO Implementation
 fDCO = 12/13.56MHz
 fDCO tuning range: ±1%
 fDCO LSB: 78ppm
 Requiring: fine RC delay cell
DCO Implementation
 fDCO = 12/13.56MHz
 fDCO tuning range: ±1%
 fDCO LSB: 78ppm
 Requiring: fine RC delay cell
Sandwich Capacitor
DCO Implementation: Stabilization
Sandwich Capacitor
 Without DCO startup aid → 3 cycles for fDCO stabilization

DCO Implementation: Stabilization
Sandwich Capacitor
 With DCO startup aid → 1 cycle for fDCO stabilization

2nd Injection: Phase Alignment
First injection:
𝑑𝑑(𝑖𝑖𝑀𝑀 ) 1 4𝑉𝑉𝑖𝑖𝑖𝑖𝑖𝑖
𝐿𝐿𝑀𝑀 + 𝑅𝑅𝑀𝑀 𝑖𝑖𝑀𝑀 + � 𝑖𝑖𝑀𝑀 𝑑𝑑𝑑𝑑 = cos(𝜔𝜔𝑖𝑖𝑖𝑖𝑖𝑖 𝑡𝑡)
𝑑𝑑𝑑𝑑 𝐶𝐶𝑀𝑀 𝜋𝜋
LM RM CM
𝑖𝑖𝑀𝑀 = 0
Initial condition: �𝑑𝑑(𝑖𝑖𝑀𝑀 )
=0
VINJ
𝑑𝑑𝑑𝑑
iM
Second injection:
𝑑𝑑(𝑖𝑖𝑀𝑀 ) 1 4𝑉𝑉𝑖𝑖𝑖𝑖𝑖𝑖
𝐿𝐿𝑀𝑀 + 𝑅𝑅𝑀𝑀 𝑖𝑖𝑀𝑀 + � 𝑖𝑖𝑀𝑀 𝑑𝑑𝑑𝑑 = cos(𝜔𝜔𝑖𝑖𝑖𝑖𝑖𝑖 𝑡𝑡 + 𝜃𝜃)
𝑑𝑑𝑑𝑑 𝐶𝐶𝑀𝑀 𝜋𝜋
𝑖𝑖𝑀𝑀 = 𝐼𝐼𝑀𝑀0
Initial condition: �𝑑𝑑(𝑖𝑖𝑀𝑀 )
=0
𝑑𝑑𝑑𝑑
 1st injection: no iM within crystal
 2nd injection: iM= IM0 within crystal
300
LM RM CM θ = 0°
200
iM,env (µA)
VINJ iM 100
IM0 θ = -180°
0
θ 0 6 12 18 24 30
Time (µs)
 Vinj and iM out-of-phase → iM decreases → ts increases
 Keep Vinj and iM in-phase
 VNO/V0 and iM is apart by 90º during calibration

V0 INJ1st & INJ2nd
V1 V4
To crystal
V2 V3
60
Ideal V in-phase with iM
V0 V1 V2
40 V3 V4
iM,env (µA)
20
0
0 2 4 6 8 10
Time (µs)
 Shift from V0 to V3 during 2nd injection
 VINJ&iM in-phase: safeguard the IM increase
Outline
 Motivation
Measurement Results
 Process: 65nm CMOS
 Active area: 0.134mm2
 VDD: 0.7V
 fXO: 12 & 13.56 MHz
Measurement Results
ts: 8ms (w/o FSA) → 45.8μs (w/i FSA) @13.56MHz

ts: 12ms (w/o FSA) → 43.6μs (w/i FSA) @12MHz
Measurement Results
 Calibration:
Delay cal.: 3 cycles
Freq. cal.: 24 cycles
Total: 48 cycles
 P(Δf>500ppm)=4.1%
Measurement Results
 Avg. ES: 4.2nJ @12MHz; 5.0nJ @13.56MHz

 ts variation: ±2.2% over -40 to 85 ºC
Measurement Results
 35.7% of ES transduced to EM
1
 Crystal’s energy: EM = LM i2M
2
Measurement Results
-115
13.56MHz
 Phase Noise
12MHz
-125 -143.7 dBc/Hz @1kHz (13.56 MHz)
Phase Noise (dBc/Hz)
-145.5 dBc/Hz @1kHz (12 MHz)

-135
 FoM
-241.8 dBc/Hz @1kHz (13.56 MHz)
-145
-242.6 dBc/Hz @1kHz (12 MHz)
-155
0 1k 10k 100k
Offset Frequency (Hz)
Outline
 Motivation
Benchmark with Literature
ISSCC’18 [5] ISSCC’19 [6] JSSC'19 [2] JSSC’21 [4] ISSCC’22 [3] This work
Inductive 3- Synchronized TSI with PLL Self-injection + TSI with S-PLL Binary-Search-
Fast Startup Technique
stage gm + SSCI Signal Injection Calibration SI Calibration Assisted TSI + SI
Technology [nm] 65 55 65 65 28 65
VDD [V] 0.3-0.5 1.2 1 1.15 1.2 0.67-0.73
Steady-State Power [µW] 31.8 N/A 198 19 1,080 28.4
PN [dBc/Hz @1kHz] −134 N/A −139.5 −137.4 −134.0 −145.5 −143.7
FoM [dBc/Hz @1kHz] β 233 N/A 241.1 242.2 231.4 242.6 241.8
Frequency [MHz] 16 32 54 24 76.8 12 13.56
CL [pF] 6 6 12 6 12 7 7 8
Steady-State VPO [Vpp] 0.28 0.37 N/A 0.7 0.08 1.2 0.16 0.16
ts [μs] 460 23 32 19 9.7 39.6 43.6 45.8
Startup Cycles 7,360 529 1,024 1,026 233 3,046 523 621
ts Reduction 3.25× 1.3× 90.6× 31.5× N/A 18.2× 183× 175×
ts Variation over Temp. 7.5% ±10% ±21% ±1.25% 3.1% 6.8% ±2.1% ±2.2%
ES [nJ] 15.8 20.2 44.2 34.9 3.3 92.8 4.2 5.0
ES Reduction 2.96x N/A N/A 3.4x N/A 6.4x 53.6x 45.0x
EM/ES # N/A N/A 20.8%▲ 14.5% N/A 39.3% 35.7%
Temperature Range [°C] −40 to 90 −40 to 140 −40 to 85 −40 to 85 −40 to 90 −35 to 85 −40 to 85
Core Area [mm2] 0.023 0.049 0.075 0.07 2.58 ‡ 0.134
β FoM: 1
#𝐸𝐸 = 𝐿𝐿 𝑖𝑖 2 , from simulation
[−PN + 20log(f/foffset) − 10log(P/1mW)] 𝑀𝑀
▲Estimation ‡ Full SOC area
2 𝑀𝑀 𝑀𝑀
TSI: Two-step injection SI: Stepwise injection
Technology [nm] 65 55 65 65 28 65
VDD [V] 0.3-0.5 1.2 1 1.15 1.2 0.67-0.73
PN [dBc/Hz @1kHz] −134 N/A −139.5 −137.4 −134.0 −145.5 −143.7
FoM [dBc/Hz @1kHz] β 233 N/A 241.1 242.2 231.4 242.6 241.8
Frequency [MHz] 16 32 54 24 76.8 12 13.56
CL [pF] 6 6 12 6 12 7 7 8
ts [μs] 460 23 32 19 9.7 39.6 43.6 45.8
Startup Cycles 7,360 529 1,024 1,026 233 3,046 523 621
ts Reduction 3.25× 1.3× 90.6× 31.5× N/A 18.2× 183× 175×
ES [nJ] 15.8 20.2 44.2 34.9 3.3 92.8 4.2 5.0
EM/ES # N/A N/A 20.8%▲ 14.5% N/A 39.3% 35.7%
Core Area [mm2] 0.023 0.049 0.075 0.07 2.58 ‡ 0.134
β FoM: 1
2 𝑀𝑀 𝑀𝑀
Technology [nm] 65 55 65 65 28 65
VDD [V] 0.3-0.5 1.2 1 1.15 1.2 0.67-0.73
PN [dBc/Hz @1kHz] −134 N/A −139.5 −137.4 −134.0 −145.5 −143.7
FoM [dBc/Hz @1kHz] β 233 N/A 241.1 242.2 231.4 242.6 241.8
Frequency [MHz] 16 32 54 24 76.8 12 13.56
CL [pF] 6 6 12 6 12 7 7 8
ts [μs] 460 23 32 19 9.7 39.6 43.6 45.8
Startup Cycles 7,360 529 1,024 1,026 233 3,046 523 621
ts Reduction 3.25× 1.3× 90.6× 31.5× N/A 18.2× 183× 175×
ES [nJ] 15.8 20.2 44.2 34.9 3.3 92.8 4.2 5.0
EM/ES # N/A N/A 20.8%▲ 14.5% N/A 39.3% 35.7%
Core Area [mm2] 0.023 0.049 0.075 0.07 2.58 ‡ 0.134
β FoM: 1
2 𝑀𝑀 𝑀𝑀
Conclusion
 Fast startup XO with two-step injection using binary-search-
assisted frequency calibration
 Delay and frequency calibration to ease the hardware
overhead
 Fast DCO stabilization to safeguard the comparison
 48 cycles for frequency locking
 Swift startup in 45.8 μs with low startup energy of 5.0 nJ
 ts reduction by 175× and ES reduction by 45×
Conclusion
 Fast startup XO with two-step injection using binary-search-
assisted frequency calibration
 Delay and frequency calibration to ease the hardware
overhead
 Fast DCO stabilization to safeguard the comparison
 48 cycles for frequency locking
 Swift startup in 45.8 μs with low startup energy of 5.0 nJ
 ts reduction by 175× and ES reduction by 45×
Demo today from 5pm
A 16MHz XO with 17.5μs Startup Time
Under 104ppm-ΔF Injection Using Automatic
Phase-Error Correction Technique
Zhikuang Cai1, Xin Wang1, Zixuan Wang1, Yunjin Yin1,

Wenjing Zhang1, Tailong Xu2, Yufeng Guo1
1 - Nanjing University of Posts and Telecommunications, China

2 - Hefei University, China
© 2023 IEEE 3.7: A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique
Energy-Saving & Duty-Cycled IoT systems
Power ULP Wireless Systems
Supply (e.g. IoT)
PLL
XO TRX
SEN
 MHz XOs are common in ULP wireless systems

 The scarce energy supply demands a duty-cycled operation for
energy saving
Power Lengthy startup time
XO startup
Sleep
Wakeup
Work
Time
 Lengthy start-up time

 Research purpose: Faster start-up and less start-up energy
Power Reduced startup time
Sleep
Wakeup
Work
Time

Power Reduced startup energy
Sleep
Wakeup
Work
Time

Injection Technique
Injection Source Differential Injection
RM CM LM
XOIN XOOUT
iM
RM CM LM Single-Ended Injection
RM CM LM
iM
XOIN XOOUT iM
XOIN XOOUT
CP Cpar2
Cpar1 Cpar2
CP
© 2023 IEEE
∆φ 3.7: A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique
6 of 37
Injection Technique
Injection Source Differential Injection
RM CM LM
FINJ
XOIN XOOUT
iM
RM CM LM Single-Ended Injection
RM CM LM Available for
iM
FXO
detection
XOIN XOOUT iM
XOIN XOOUT
CP Cpar2
Cpar1 Cpar2
∆F=FINJ-FXO CP
© 2023 IEEE
∆φ 3.7: A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique
7 of 37
Automatic Phase-Error Correction (APEC)
XOIN XOOUT
16MHz Crystal
RO
EN[7:0] Phase[7:0] Available for

detection
APEC
 XOIN for energy injection and XOOUT for ∆φ detection

 8 signals with different phases (0, π/4, π/2, … , 2π) are available
 The APEC selects the right injection signal to correct ∆φ
Automatic Phase-Error Correction (APEC)
XOIN XOOUT
16MHz Crystal
RO
EN[7:0] Phase[7:0] Available for

detection
APEC
 Solid line: differential. Dotted line: single-ended w/ APEC.

 Pro: XOOUT is available for detection, and ∆φ is easier to correct
 Con: lower motional-current growth rate
Theoretical Analysis
Single-Ended Injection Superposition Theorem
RM CM LM RM CM LM
iM XOOUT iM XOOUT1
Cpar2 Cpar2
CP CP
+
RM CM LM
 Differential equation
iM XOOUT2
 Initial conditions
Cpar2
 Laplace Transform CP
 Equation of XOOUT
Theoretical Analysis
XOOUT1
+
XOOUT2
=
XOOUT
Definition of ∆φ
Peak point shift
XOOUT1
+
XOOUT2
=
XOOUT
 As the injection goes on, the peak points of XOOUT will gradually
move far away from the falling edge of the injection signal
 The redefinition of ∆φ is based on this peak point shift
Definition of ∆φ
∆φ = (∆t/TINJ)·2π = ∆t·2π·FINJ ∆t
XOOUT1
+
XOOUT2
=
XOOUT
 ∆t: time difference between the peak and the falling edge of XOOUT
 ∆φ = ∆t·2π·FINJ: normalizing ∆t with respect to the period of the
injection signal and getting the equation of ∆φ
Criteria for ∆φ Detection
∆φ=π/4
XOOUT
XOIN
(Phase[i])
Phase[i-1]
∆t=TINJ/8
 Phase[7:0]: Phase[i-1] is π/4 ahead of Phase[i] ( 0<i<8 )
 Assuming Phase[i] is used for injection, ∆φ = π/4 means that the
peak point of XOOUT reaches the falling edge of Phase[i-1]
∆φ=π/4
XOOUT
XOIN
(Phase[i])
Phase[i-1]
FINJ < FXO ∆t=TINJ/8

 Phase[7:0]: Phase[i-1] is π/4 ahead of Phase[i] ( 0<i<8 )
 Assuming Phase[i] is used for injection, ∆φ = π/4 means that the
peak point of XOOUT reaches the falling edge of Phase[i-1]
Criteria for ∆φ Detection——FINJ > FXO
XOOUT1
+
XOOUT2
=
XOOUT
XOIN
(Phase[i])
Phase[i+1]
 The peak point of the growing sine wave is not the peak of XOOUT
 Hard to detect the peak point of the sine wave
Criteria for ∆φ Detection——FINJ > FXO
iM
Envelope
XOOUT
Envelope
∆φ
0 π/4 π/2 3π/4 π
π/4
 ∆φ goes from 0 to π
 XOOUT envelope stops increasing once Δφ accumulates to π/4
 Criterion for ∆φ Detection when FINJ > FXO
XOOUT
t
Crystal Resonant Peak Peak Voltage Value
XOOUT
∆φ=0 ∆φ=π/4 ∆φ=π/2 t
 Tracking the peak of XOOUT for both FINJ < FXO and FINJ > FXO
 Determining whether ∆φ > π/4
Block Diagram of the proposed XO
ENINJ XOIN XOOUT ENINJ
Crystal
CL CL
Gm
Phase[7:0] Johnson CLK

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
ENINJ Digital Buffer
Detector
PKDEN
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 The RO oscillates around 1.024GHz

 64× higher than FXO (16MHz)
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 The reference clock of the peak detector (PKD)

 PKD is responsible for detecting the peak positions of XOOUT
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 A divide-by-8 prescaler and a Johnson Counter

 Phase[7:0] (~16MHz) generation
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 Phase[7:0] are sent to the MUX where Phase[i] is enabled for

injection by EN[i] from the digital controller (DC).
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 The output of PKD passes through a customized buffer to

broaden pulse width, ensuring reliable data capture of DC.
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 Working mechanism : Injecting energy at XOIN
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 Working mechanism: Detecting ∆φ at XOOUT. The APEC will

automatically correct the phase error by switching the injection
signal.
© 2023 IEEE
3.7: A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique
26 of 37
Crystal
CL CL
Gm

MUX
Counter ÷8
RO
PDIN EN[7:0] APEC
BUFFOUT PKDOUT Peak
Detector
PKDEN
 After sufficient growth of iM, a Gm amplifier is enabled to maintain

the steady-state oscillation
Circuit Implementation
Johnson Counter Peak Detector
Phase[0] Phase[1] Phase[2] Phase[3] Iref

A PKDOUT
DCMP
D Q D Q D Q D Q
B
DFF DFF DFF DFF
Qn Qn Qn Qn
RST
CPKD
Phase[4] Phase[5] Phase[6] Phase[7]
CLK
 Johnson Counter consists of 4 DFFs

 Providing 8 injection signals with different phases
Circuit Implementation
Johnson Counter Peak Detector
Phase[0] Phase[1] Phase[2] Phase[3] Iref

A PKDOUT
DCMP
D Q D Q D Q D Q
B
DFF DFF DFF DFF
Qn Qn Qn Qn
RST
CPKD
Phase[4] Phase[5] Phase[6] Phase[7]
CLK
 Peak Detector consists of a dynamic comparator (DCMP), et al.

 Since the input offset is stored on the capacitor CPKD, the DCMP has
good tolerance for the offset
Timing Sequence
XOOUT
XOIN
PDIN
PKDEN
FINJ < FXO
PKDOUT
BUFFOUT
EN[i]
EN[i-1]
∆φ
 ∆φ between PDIN (Phase[i-1]) and XOIN (Phase[i]) is π/4

 BUFFOUT represents the peak positions with the rising edges
 DC samples BUFFOUT at the falling edge of PDIN (Phase[i-1])
Timing Sequence
XOOUT
XOIN
PKDEN
PKDOUT FINJ > FXO
BUFFOUT
EN[i]
EN[i+1]
∆φ
 XOOUT envelope stops increasing once Δφ accumulates to π/4

 BUFFOUT represents the envelope increasement with the pulses
 DC samples BUFFOUT at the falling edge of PKDEN (Phase[i+1])
Three Working Stages
iM
SEI W/ APEC DI Gm AMP  Single-Ended Injection
With APEC technique
 T1 = T2 = T3 = …
 T0 is larger than T1
 T2 is stored and aligned to T3~Tn
0
 Differential Injection
 To accelerate the iM growth
 Gm Amplifier
 A common-source amplifier
T0 T1 T2 T3~Tn-2 Tn-1 Tn
 To maintain the oscillation
0 t
Chip Photo
APEC
FPGA
Oscilloscope (To trigger VDD and
switch APEC)
220μm
Power
Temperature
Chamber
300μm
Device
under test
 Fabricated in 40nm CMOS  Core area: 0.05 mm2

 FXO = 16 MHz, VDD = 1 V, CL = 6 pF, Q = 6.5 × 104
Measurement Results
W/ APEC
4μs
3μs
W/O APEC
 ∆F: 104 ppm  TS: 17.5 μs  ES: 9.2 nJ

Measured XO Startup across ∆F
Max:17.5μs@1.01x104ppm
 Robust against ∆F : 1.27% across 3000 to 104 ppm

Performance Summary
ISSCC'2016 [1] ISSCC'2019 [2] ISSCC'2019 [3] JSSC'2022 [4] JSSC'2018 [5] This work
Dithered Synchronized 2-Step IGCI & Precisely timed Automatic Phase-

Technique
frequency injection Singal Injection Injection Boosted Rn injection Error Correction
Technology (nm ) 65 55 65 22 65 40
Core area (mm 2 ) 0.08 0.084 0.069 0.144 0.09 0.05
Supply (V ) 1.68 1.2 1 1 1 1
Frequency (MHz ) 24 32 54 12 38.4 10 16
Load capacitance,C L (pF ) 6 9 6 12 6 3.75 8 6
Startup time,T S (μs ) 64 435 23 32 19 340 58 10 to 250* 17.5
Startup cycles 1536 10440 736 1024 1026 4080 2227 100 to 2500 280
△F tolerance (ppm ) 2x104 N/A N/A 5000 N/A 104 10
4
Startup energy (nJ ) N/A 20.2 44.2 34.9 180.5 45.6 12 9.2
Steady state core power (μW ) 393 693 N/A 198 450 800 45.5 84
T S variation with Temp ±35% ±20% ±10% ±20.9% ±1.25% N/A N/A 3% ±4.5%
Temperature range (°C) -40 to 90 -40 to 140 -40 to 85 N/A -40 to 85 -20 to 85
* TS approximates 250μs when △F=104ppm.
Summary
Automatic Phase-Error Correction (APEC) XO
 Startup Performance  Characteristics
 Start-up time of 17.5 μs  Employment of the single-ended injection
(280 cycles)  Interpretation of the waveform of XOOUT
 Start-up energy of 9.2 nJ  Interpretation of the envelopes of iM and
 Robust against ∆F XOOUT
(-104 ppm ~ +104 ppm)  Injecting energy and correcting ∆φ
 Robust against temperature simultaneously
(-25 oC to 85 oC)  A ∆F tolerance of 104 ppm
 Loosening the tightness of trimming FINJ
A 0.954nW 32kHz Crystal Oscillator in
22nm CMOS with Gm-C-Based
Current Injection Control
Yihan Zhang, You You, Wenjie Ren, Xinhang Xu,
Linxiao Shen, Jiayoon Ru, Ru Huang, and Le Ye*
Peking University, Beijing China

Advanced Institute of Information Technology of Peking University, Hangzhou China
© 2023 IEEE
International Solid-State Circuits Conference 3.8: A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control 1 of 27
Outline
 Motivation
 Circuit Implementation
 Conclusion
© 2023 IEEE
Wake-Up Timer in IoT Nodes
Transceivers, etc.
Wake-up timer (XO)
Power
sleep time
Wake-up guard time

Extra wake-up power
 Reducing IoT nodes’ power with periodic wake ups [1]

 Wake-up timer with low power
 Wake-up timer with high frequency stability
[1] D. Griffith, Synchronization Clocks for Ultra-Low Power Wireless Networks, Springer, 2015
© 2023 IEEE
Pulse-Injection Crystal Oscillator (PIXO)
 Discrete-time negative resistance

 Generation of the Injected Pulses
© 2023 IEEE
Controlling the Injected Pulses
Timing Generation
 Minimize phase noise [2, 3]
 Maximize energy efficiency
Amplitude Control
 Feedback-based
[2] L. Xu, et al., IEEE JSSC 2022

[3] A. Hajimiri and T. H. Lee, IEEE JSSC 1998
© 2023 IEEE
System Highlight
Timing Generation
Gm-C Cell
 Small-signal
 Frequency response
Amplitude Control
 Large-signal
 Nonlinearity
© 2023 IEEE
Outline
 Motivation
 Conclusion
© 2023 IEEE
System Overview
@
@270˚
90˚
© 2023 IEEE
System Overview
© 2023 IEEE
System Overview
© 2023 IEEE
System Overview
© 2023 IEEE
System Overview
© 2023 IEEE
Timing Generator
270˚ Injection
Control
90˚ Injection
Control
Amplitude:
100mV ~300mV Digital Digital
Phase:
0˚/180˚ + ~83˚ (Analog) + ~7˚ (Digital) 90˚/270˚
© 2023 IEEE
Timing Generator
 AC-coupled input
 CL is mostly linear:
wiring parasitic dominates the load capacitance
© 2023 IEEE
Timing Generator
 A(ω0) = gm/(CL+CF)/ω0
 PTAT current bias [4] for gm
Temperature compensation in deep-subthreshold
[4] H. Esmaeelzadeh, et al., IEEE JSSC 2019
© 2023 IEEE
Timing Generator
 Cross-coupled CF
LHP zero @ ωZ ≈ gm/CF
 Now, ∠(ω0) ≈ 90˚ - arctan(CF/A(CL+CF) + gds/ω0(CL+CF))
© 2023 IEEE
Amplitude Regulator: The Feedback Loop
© 2023 IEEE
The Amplitude Detector: The Gm Cell
 9T-amplifier-based gm cell
 Duplicated output with reverse current polarity
 Asymmetric large-signal I-V transfer curve with input offset
© 2023 IEEE
Amplitude Detector: A Thought Experiment
 Non-linearity and input offset induced amplitude sensitivity

 Average IOUT on C as a function of VAMP is continuous
 The VAMP makes average IOUT = 0 is a function of VOS
© 2023 IEEE
Amplitude Detector: Simulation Results
 PSS simulation for average IOUT vs. VAMP at different VOS

 At each VOS, VAMP stabilizes when average IOUT = 0
 Use VOS to set the desired VAMP
© 2023 IEEE
Outline
 Motivation
 Conclusion
© 2023 IEEE
Die photo
 Fabricated in 22nm CMOS
 Total area: 0.029 mm2
 ECS-2X6X tuning fork crystal

R1 ≤ 30kΩ, C0 ≈ 1.35pF
© 2023 IEEE
Measurement Results
 Increasing VOS leads to higher power consumption

Showcasing gm-C-based amplitude regulation
 Allan Deviation floor: 6ppb
© 2023 IEEE
Measurement Results
 0.954nW power consumption @ 0.46V & 25˚C (5 chips)

0.46V is the minimum voltage to work across -20˚C and 80˚C
 Less than 2nW average power between -20˚C and 80˚C (5 chips)
© 2023 IEEE
Comparison
K.-M. Kim L. Xu Y. Zeng K.-J. Hsiao H. Esmaeelzadeh
This Work
JSSC 21 ISSCC 20 VLSI 17 ISSCC 14 ISSCC 19
Process 22nm 55nm 40 nm 55nm 28 nm 65 nm
Resonance Mode Parallel Parallel Parallel Parallel Parallel Series
# of Supplies 1 (VDD) 1 (VDD) 2 (VDD + VDDL) 2 (VDDM+VDDL) 1 (VDD) 1 (VDD)
Injection
Frequency (Hz)
32k 2k 32k 4k 32k 32k 32k N/A
Power
@ 25ºC (nW)
0.954 0.74 2.53 0.51 0.98 1.7 1.89 0.55
Power
@ 80ºC (nW)
1.90 4.24 6.31 1.61 N/A 16 30 3.5
Power Sensitivity to
Temperature (nW/˚C)
0.017 0.063 0.068 0.02 N/A 0.26 0.511 0.053
Area (mm2) 0.029 0.019 0.02 0.16 0.03 0.027

Temperature Range -20/80 -20/80 -25/85 -20/80 -20/80 -20/80
Line Sensitivity (ppm/V) 22.5 101 18 6.7 85 13

(for VDDL only)
Allan Deviation
Floor (ppb)
6 19 2 25 10 14
© 2023 IEEE
Outline
 Motivation
 Conclusion
© 2023 IEEE
Conclusion
 22nm CMOS PIXO for IoT applications
 Gm-C-based analog solution for PIXO
 Achieves stable power over a wide temperature range
 State-of-the-art performance
 0.954nW power consumption, 6ppb Allan deviation floor
 Feedback-based injection amplitude control

© 2023 IEEE
A 0.5-to-400MHz Programmable BAW
Oscillator with Fractional Output Divider
Achieving 4ppm Frequency Stability over
Temperature and <95fs Jitter
Subhashish Mukherjee1, Yogesh Darwhekar1, Jayawardan Janardhanan1, Peeyoosh
Mirajkar1, Raghavendra Reddy1, Harish Ramesh1, Bichoy Bahr1, Jagdish Chand1, Uday
Meda1, Baher Haroun1, Shankar Karantha1, Ernest Yen1, Keegan Martin1, Daniel Gan1,
Amin Sijelmassi1, Sankaran Aniruddhan2
1Texas Instruments 2IIT Madras
Acknowledgement: Apoorva Bhatia, Arpan Thakkar, Rakhav R, Ashish J, Prajwal S,

Arshad K, Guru S, Swaminathan Sankaran, Amin Eshraghi, C P Ong, Y F Chek, Ricky
Jackson, Prathap G, Xiaofan Qiu and Michael Perrott at Texas Instruments
© 2023 IEEE 3.9: A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm
International Solid-State Circuits Conference Frequency Stability over Temperature and <95fs Jitter 1 of 33
Outline
 Advantages of BAW technology for oscillators
 BAW based oscillator: characteristics, requirements and
architecture
 Temperature sensing and frequency control
 Core oscillator implementation
 Fractional output divider (FOD) implementation and calibration
 Silicon measurement results
 Conclusions
BAW Resonator Technology
 Standard high volume manufacturing process
 A piezoelectric layer sandwiched between metal films
 Easy to co-package with other ICs in industry standard
packages: both wire-bond and flip-chip
 Wide -50C to +150C temperature capability
 Superior Reliability and Robustness
 Displacement of ~0.1nm (compared to 1nm - 1um for MEMS):
 robust against vibration
 No hermetic sealing/ vacuum packaging requirement
 Insensitive to contaminants like moisture, Helium, particulate
matter
 High Resonance Frequency
 Frequency range from 2.4GHz to 2.6GHz with Q > 1000
 Fast startup time (< 5us)
 Direct division to generate most common frequencies
 High frequency clocking
BAW Characteristics
• BAW process variation: +/-2000ppm
+2000
• BAW temperature variation: ~ +/-150ppm

Spec: +/- 20ppm • Absolute accuracy target of 20ppm
includes solder shift and 10 year aging
PPM
• Temperature compensation needs to be

about 7ppm
~300ppm • To achieve target frequency, we need:
-2000
• Temperature based frequency control

• Fractional frequency divider
BAW Based Oscillator
• Implemented as a die-on-die MCM
• Employ a free running BAW oscillator (~ 2.5GHz)
– Minimum loading to preserve BAW Q (~ 1000)
– Optimum oscillator noise
• FOD to generate any user-programmable output

BAW Die
up to 400MHz
Circuit Die
-gm /N.F
Fractional Output
Divider (FOD)
BAW Based Oscillator
• Implemented as a die-on-die MCM
• Employ a free running BAW oscillator (~ 2.5GHz)
– Minimum loading to preserve BAW Q (~ 1000)
– Optimum oscillator noise
• FOD to generate any user-programmable output

BAW Die
up to 400MHz
Circuit Die • FOD provides several advantages over frac. PLL
– Compact die size fitting into a 2.5mmX2.0mm
-gm /N.F package
Fractional Output – Improved startup time
Divider (FOD) – Better jitter for the same power consumption
BAW Based Oscillator: Architecture
PPM Deviation
Temp Device 2
Sense
T1 T2 T3
Temp
Freq
correction Device 1
Control
LUT
Temp Sensor Code
-gm /N.F
• Multi-temp characterization of every
Fractional Output device to generate Frequency vs.
Divider (FOD) Sensor Code characteristics
• Correction look-up table (LUT) created
and stored in non-volatile memory
Temperature Sensing and Control
BAW die and circuit die may not be in thermal equilibrium

• Use dual temp sensor: Moly-sensor in BAW die and Poly-sensor
in circuit die
• Blend Readouts to provide the overall frequency-sensing code
• Weights (G1/G2) selected based on simulation/ characterization
Post processing smoothens out

frequency correction reducing
in-band spurs and phase jumps
Results: ppm control across temperature
16 devices measured
Slope= 1oC/min
BAW Oscillator Core Design
VDD=1.7V
M3 M4
M1 M2
M5 Cs M6
Class-A BAW Oscillator,

D. Griffith 2020
Class-C BAW Oscillator =1.2V
VDD=1.7V Proposed Class-C
• M3 & M4
M3 M4 • gm for –ve R
• Current control
• Lower VDD=1.2V
• Cs single-Ended
M1 M2 • Class-C operation
• 2nd Harmonic Phase Control
M5 Cs M6 and ISF optimization
• Flicker suppression
Class-A BAW Oscillator,
• Ctune
D. Griffith 2020
• Freq tuning
• Spur optimization
FOD Function Example: BAW frequency ÷ 2.7
0 2.7 5.4 8.1 10.8 13.5 16.2
BAW
Integer 2 3 3 2 3 3
division
Variable
0.7 0.4 0.1 0.8 0.5 0.2
delay
BAW edges ~400ps

Fbaw /N DTC
∆∑ Integer Integer
Digital to
 FOD synthesizes delay to create a + division
Time
carry Converter
fine grid (phase interpolation)
+
 Oscillator target: <100fs jitter frac Fractional
delay
 FOD: 13 bit (50fs grid)
Evolution of DTC: Variable-slope DTC
• There are many reported approaches to achieve phase interpolation,
like the variable slope interpolator:
T
T • Code dependent comparator
VC
delay-modulation contributes
significantly to INL.
ε
• Architecture sensitive to
I
temperature, comparator
C threshold, I, C etc.
Evolution of DTC: Constant-slope DTC
• Code dependent comparator delay-modulation issue can be resolved
using constant slope DTC
• Signal slope near comparator threshold independent of delay code
T
• Insensitive to comparator delay
T
VC modulation, comparator
threshold, absolute pre-charge
DAC voltage
ε=0
I • Sensitive to DAC voltage
Voltage settling, temperature, I, C
pre-charge
C
J Z Ru, et al., “A High-Linearity Digital-to-Time Converter Technique:

Constant-Slope Charging”, JSSC, pp. 1412-1423, June 2015
Evolution of DTC: Dual-slope DTC (DSDTC)
• In DSDTC, charging current is split between:
• Code dependent current (phase 1) and
• Constant (max) current (phase 2)
T
T
VC
ε=0
αI, I
Evolution of DTC: Dual-slope DTC (DSDTC)
• In DSDTC, charging current is split between:
• Code dependent current (phase 1) and
• Constant (max) current (phase 2)
• Insensitive to comparator delay
T modulation, comparator
T threshold, temperature, I, C
VC
• Helps in implementation of a fine
DTC grid over a large BAW
ε=0 period of 400ps
αI, I
C
parallelogram
FOD Implementation
Ph-1 Ph-3
Ph-2 Ph-4
Io
αIo
FOD Implementation
Ph-1
Io
αIo
FOD Implementation
Ph-1
Ph-2
Io
αIo
FOD Implementation
Ph-1 Ph-3
Ph-2
Io
αIo
FOD Implementation
Ph-1 Ph-3
Ph-2 Ph-4
Io
αIo
INL Calibration
Problem: Non-linearity of DSDTC results in output spurs
INL Calibration
Solution: Configure DSDTC as relaxation oscillator (RO) to capture dynamic
INL impairments accurately and correct using digital means
αI, I
Delay
VP1, VP2
INL Calibration
Solution: Configure DSDTC as relaxation oscillator (RO) to capture dynamic
INL impairments accurately and correct using digital means
• Feedback pulses VP1/VP2 synthesized to

be close to BAW cycle period.
• RO time period linearly proportional to αI, I
DSDTC code “α”
C
• INL is measured, needed correction
computed and stored in NVM
Delay
• Correction per code is applied via INL VP1, VP2
DAC during normal operation
Results: INL Calibration
Pre-correction
Measured INL, pre and

post correction
Post-correction
Oscillator System Overview
Signal Path
• DSDTC produces narrow output pulses

• Divide-by-two is needed to restore 50% duty-cycle
• DSDTC runs at max speed of 400MHz
• For Fout > 200MHz, two FOD channels are utilized
Frequency Control
for separate rising- and falling-edge generation
Results: Jitter (12kHz – 20MHz)
Jitter
86.205fs
Measured PN/ Jitter for 156.25MHz (single FOD operation)

Results: Jitter (12kHz – 20MHz)
Jitter
92.531fs
Measured PN/ Jitter for 400MHz (dual FOD operation)

Summary of Results
Process 65nm
Freq Range 0.5-400MHz
Freq control with temperature (-40 +85) <+/-4ppm
Phase Noise @156.25MHz @ 1MHz -157 dBc/Hz
Jitter@156.25MHz (LVPECL) 88fs
Power @ 156.25MHz (LVPECL) 69mA^ (typ)
Package 2.5X2.0
Mechanical shock tolerance (MIL-STD-883F, 2002) 1500g
Mechanical Vibration tolerance (MIL-STD-883F, 2007) 20g
Vibration tolerance 1 ppb/g
^ Excluding load termination current
Conclusion
 A programmable BAW based
oscillator has been implemented as
a die-on-die MCM in a
2.5mmX2.0mm package
 A class-C BAW oscillator has been
implemented with flicker suppression
 Achieves +/-4ppm temperature
control and 88fs jitter at 156.25MHz DTC-1 OP
BAW DRIVER
 Any frequency output till 400MHz is OSC
DTC-2
achieved using a Dual Slope FOD
TEMP
DIGITAL
 The device is found to be robust SENSOR
under shock and vibration tests
Thank you!

ISSCC2023-Amplifiers and Oscillators

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ISSCC

1Delft University of Technology, Delft, The Netherlands

 Switching output stage  high efficiency

[T. Ido, ISSCC’06]

 Feedback loop suppresses output-stage distortion

[D. Schinkel, JSSC’17]

 ADC senses LC output  LC distortion suppressed

[H. Zhang, ISSCC’22]

 Noiseless feedback network

 Potential distortion due to mismatch, ISI, and IMD

 Capacitively coupled front-end

 fCHOP = fS/2 (384kHz) avoids quantization noise folding

 fS = 768kHz limits swing

 20ns DB blocks chopping glitches

 Feedback around LC filter (88kHz nominal) [H. Zhang, VLSI’21]

 Loop bandwidth ~500kHz  ~50dB nonlinearity suppression

 ~500kHz loop vs. 88kHz LC  large overshoot

 8-bit DAC limits signal range loss under 0.5dB

 256 control lines needed to DEM 8-bit unary DAC

 DSM reduces bit width, shapes gain error

 2nd order less prone to idle tones than 1st order

[E. van Tuijl, ISSCC’04]

*Illustrated for a 3-bit DAC

 Mismatch averaged within each sample period (TS)

[E. van Tuijl, ISSCC’04]

*Illustrated for a 3-bit DAC

 Signal-dependent # transitions between samples

 1% ISI on rising edges

*Illustrated for a 3-bit DAC

 Deadband blocks signal-dependent transitions

 1% ISI on rising edges

 12fF CU using custom MOM caps

[H. Zhang, JSSC’22]

[H. Zhang, JSSC’22]

 So far: DAC + capacitively coupled front-end

 3-stage loop filter + PWM output stage [H. Zhang, VLSI’21]

 ~−80dBc spurs present with 1st-order segmentation

 Peak THD+N = -112.1 dB

 Peak THD+N = -112.1 dB

Thank you for your attention!

1DelftUniversity of Technology, Delft, The Netherlands

Intermodulation Output spectrum:

Chopping signal (FCH=20kHz) FCH Frequency

• Fin @ even multiples of FCH

→ IMD tones in-band

Intermodulation Output spectrum:

Spread-spectrum chopping FCH Frequency

• IMD tone → noise signal

• Does not solve the

[T.Rooijers – ISSCC 2021]

[T.Rooijers – ISSCC 2021]

Iout1 50% Duty-cycle

Combined with AZ:

[T.Rooijers – ISSCC 2021]

RRL: 2nd IMD Source

RRL: 2nd IMD Source

RRL: 2nd IMD Source

RRL: 2nd IMD Source

RRL: 2nd IMD Source

0.18µm CMOS BCD

0.54mm2 active area

Un-chopped CH Without Fill-in CH With Fill-in

IMD: IMD: IMD:

Limited by linearity Limited by linearity & Limited by linearity